| stats.txt (9229:65f927bda74d) | stats.txt (9285:9901180cd573) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.064346 # Number of seconds simulated 4sim_ticks 64346040000 # Number of ticks simulated 5final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.061487 # Number of seconds simulated 4sim_ticks 61487437500 # Number of ticks simulated 5final_tick 61487437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 132449 # Simulator instruction rate (inst/s) 8host_op_rate 233222 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53944275 # Simulator tick rate (ticks/s) 10host_mem_usage 365660 # Number of bytes of host memory used 11host_seconds 1192.82 # Real time elapsed on the host | 7host_inst_rate 86290 # Simulator instruction rate (inst/s) 8host_op_rate 151942 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33582980 # Simulator tick rate (ticks/s) 10host_mem_usage 365956 # Number of bytes of host memory used 11host_seconds 1830.91 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192462 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192462 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 1893056 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1961408 # Number of bytes read from this memory |
| 17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory | 17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory |
| 19system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20416 # Number of bytes written to this memory | 19system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20288 # Number of bytes written to this memory |
| 21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory | 21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 319 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.num_reads::cpu.data 29579 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30647 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 317 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1111642 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 30787687 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 31899329 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1111642 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1111642 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 329954 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 329954 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 329954 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1111642 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 30787687 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32229283 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.workload.num_syscalls 444 # Number of system calls | 37system.cpu.workload.num_syscalls 444 # Number of system calls |
| 38system.cpu.numCycles 128692081 # number of cpu cycles simulated | 38system.cpu.numCycles 122974876 # number of cpu cycles simulated |
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 41system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups 45system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits | 41system.cpu.BPredUnit.lookups 35563581 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 35563581 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 1083908 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 25421016 # Number of BTB lookups 45system.cpu.BPredUnit.BTBHits 25287599 # Number of BTB hits |
| 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 49system.cpu.fetch.icacheStallCycles 27884150 # Number of cycles fetch is stalled on an Icache miss 50system.cpu.fetch.Insts 193525000 # Number of instructions fetch has processed 51system.cpu.fetch.Branches 35576702 # Number of branches that fetch encountered 52system.cpu.fetch.predictedBranches 25270525 # Number of branches that fetch has predicted taken 53system.cpu.fetch.Cycles 58636506 # Number of cycles fetch has run and was not squashing or blocked 54system.cpu.fetch.SquashCycles 7358089 # Number of cycles fetch has spent squashing 55system.cpu.fetch.BlockedCycles 35916291 # Number of cycles fetch has spent blocked 56system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 57system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps 58system.cpu.fetch.CacheLines 27160167 # Number of cache lines fetched 59system.cpu.fetch.IcacheSquashes 295674 # Number of outstanding Icache misses that were squashed 60system.cpu.fetch.rateDist::samples 128658357 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::mean 2.644591 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::stdev 3.372169 # Number of instructions fetched each cycle (Total) | 49system.cpu.fetch.icacheStallCycles 27814300 # Number of cycles fetch is stalled on an Icache miss 50system.cpu.fetch.Insts 193613700 # Number of instructions fetch has processed 51system.cpu.fetch.Branches 35563581 # Number of branches that fetch encountered 52system.cpu.fetch.predictedBranches 25287599 # Number of branches that fetch has predicted taken 53system.cpu.fetch.Cycles 58598336 # Number of cycles fetch has run and was not squashing or blocked 54system.cpu.fetch.SquashCycles 7345607 # Number of cycles fetch has spent squashing 55system.cpu.fetch.BlockedCycles 30298263 # Number of cycles fetch has spent blocked 56system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 57system.cpu.fetch.PendingTrapStallCycles 223 # Number of stall cycles due to pending traps 58system.cpu.fetch.CacheLines 27172491 # Number of cache lines fetched 59system.cpu.fetch.IcacheSquashes 322176 # Number of outstanding Icache misses that were squashed 60system.cpu.fetch.rateDist::samples 122946211 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::mean 2.768410 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::stdev 3.402032 # Number of instructions fetched each cycle (Total) |
| 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 64system.cpu.fetch.rateDist::0 72765830 56.56% 56.56% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::1 2056683 1.60% 58.16% # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::2 3006413 2.34% 60.49% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::3 4027268 3.13% 63.62% # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::4 8003806 6.22% 69.84% # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::5 5026752 3.91% 73.75% # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.rateDist::6 2893556 2.25% 76.00% # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::7 1437345 1.12% 77.12% # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::8 29440704 22.88% 100.00% # Number of instructions fetched each cycle (Total) | 64system.cpu.fetch.rateDist::0 67085101 54.56% 54.56% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::1 2067083 1.68% 56.25% # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::2 2985500 2.43% 58.67% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::3 3997651 3.25% 61.93% # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::4 7978379 6.49% 68.42% # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::5 5028202 4.09% 72.50% # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.rateDist::6 2861375 2.33% 74.83% # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::7 1431598 1.16% 76.00% # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::8 29511322 24.00% 100.00% # Number of instructions fetched each cycle (Total) |
| 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 76system.cpu.fetch.rateDist::total 128658357 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.branchRate 0.276448 # Number of branch fetches per cycle 78system.cpu.fetch.rate 1.503783 # Number of inst fetches per cycle 79system.cpu.decode.IdleCycles 39452105 # Number of cycles decode is idle 80system.cpu.decode.BlockedCycles 27727798 # Number of cycles decode is blocked 81system.cpu.decode.RunCycles 46961382 # Number of cycles decode is running 82system.cpu.decode.UnblockCycles 8295915 # Number of cycles decode is unblocking 83system.cpu.decode.SquashCycles 6221157 # Number of cycles decode is squashing 84system.cpu.decode.DecodedInsts 336436945 # Number of instructions handled by decode 85system.cpu.rename.SquashCycles 6221157 # Number of cycles rename is squashing 86system.cpu.rename.IdleCycles 44164076 # Number of cycles rename is idle 87system.cpu.rename.BlockCycles 5970160 # Number of cycles rename is blocking 88system.cpu.rename.serializeStallCycles 9070 # count of cycles rename stalled for serializing inst 89system.cpu.rename.RunCycles 50268632 # Number of cycles rename is running 90system.cpu.rename.UnblockCycles 22025262 # Number of cycles rename is unblocking 91system.cpu.rename.RenamedInsts 331751360 # Number of instructions processed by rename 92system.cpu.rename.ROBFullEvents 262 # Number of times rename has blocked due to ROB full 93system.cpu.rename.IQFullEvents 6842 # Number of times rename has blocked due to IQ full 94system.cpu.rename.LSQFullEvents 20121054 # Number of times rename has blocked due to LSQ full 95system.cpu.rename.FullRegisterEvents 216 # Number of times there has been no free registers 96system.cpu.rename.RenamedOperands 334012838 # Number of destination operands rename has renamed 97system.cpu.rename.RenameLookups 880453680 # Number of register rename lookups that rename has made 98system.cpu.rename.int_rename_lookups 880451759 # Number of integer rename lookups 99system.cpu.rename.fp_rename_lookups 1921 # Number of floating rename lookups | 76system.cpu.fetch.rateDist::total 122946211 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.branchRate 0.289194 # Number of branch fetches per cycle 78system.cpu.fetch.rate 1.574417 # Number of inst fetches per cycle 79system.cpu.decode.IdleCycles 38912587 # Number of cycles decode is idle 80system.cpu.decode.BlockedCycles 22600530 # Number of cycles decode is blocked 81system.cpu.decode.RunCycles 48050125 # Number of cycles decode is running 82system.cpu.decode.UnblockCycles 7147919 # Number of cycles decode is unblocking 83system.cpu.decode.SquashCycles 6235050 # Number of cycles decode is squashing 84system.cpu.decode.DecodedInsts 336030812 # Number of instructions handled by decode 85system.cpu.rename.SquashCycles 6235050 # Number of cycles rename is squashing 86system.cpu.rename.IdleCycles 43304200 # Number of cycles rename is idle 87system.cpu.rename.BlockCycles 3170225 # Number of cycles rename is blocking 88system.cpu.rename.serializeStallCycles 8978 # count of cycles rename stalled for serializing inst 89system.cpu.rename.RunCycles 50645325 # Number of cycles rename is running 90system.cpu.rename.UnblockCycles 19582433 # Number of cycles rename is unblocking 91system.cpu.rename.RenamedInsts 332156996 # Number of instructions processed by rename 92system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full 93system.cpu.rename.IQFullEvents 3311 # Number of times rename has blocked due to IQ full 94system.cpu.rename.LSQFullEvents 17907327 # Number of times rename has blocked due to LSQ full 95system.cpu.rename.FullRegisterEvents 182 # Number of times there has been no free registers 96system.cpu.rename.RenamedOperands 334503257 # Number of destination operands rename has renamed 97system.cpu.rename.RenameLookups 881229115 # Number of register rename lookups that rename has made 98system.cpu.rename.int_rename_lookups 881227036 # Number of integer rename lookups 99system.cpu.rename.fp_rename_lookups 2079 # Number of floating rename lookups |
| 100system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed | 100system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed |
| 101system.cpu.rename.UndoneMaps 54800094 # Number of HB maps that are undone due to squashing 102system.cpu.rename.serializingInsts 485 # count of serializing insts renamed 103system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed 104system.cpu.rename.skidInsts 50437110 # count of insts added to the skid buffer 105system.cpu.memDep0.insertedLoads 104594760 # Number of loads inserted to the mem dependence unit. 106system.cpu.memDep0.insertedStores 36334761 # Number of stores inserted to the mem dependence unit. 107system.cpu.memDep0.conflictingLoads 41480583 # Number of conflicting loads. 108system.cpu.memDep0.conflictingStores 6245732 # Number of conflicting stores. 109system.cpu.iq.iqInstsAdded 323452648 # Number of instructions added to the IQ (excludes non-spec) | 101system.cpu.rename.UndoneMaps 55290513 # Number of HB maps that are undone due to squashing 102system.cpu.rename.serializingInsts 484 # count of serializing insts renamed 103system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed 104system.cpu.rename.skidInsts 44388140 # count of insts added to the skid buffer 105system.cpu.memDep0.insertedLoads 104937995 # Number of loads inserted to the mem dependence unit. 106system.cpu.memDep0.insertedStores 36474446 # Number of stores inserted to the mem dependence unit. 107system.cpu.memDep0.conflictingLoads 41500364 # Number of conflicting loads. 108system.cpu.memDep0.conflictingStores 5836392 # Number of conflicting stores. 109system.cpu.iq.iqInstsAdded 323873529 # Number of instructions added to the IQ (excludes non-spec) |
| 110system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ | 110system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ |
| 111system.cpu.iq.iqInstsIssued 307818254 # Number of instructions issued 112system.cpu.iq.iqSquashedInstsIssued 198387 # Number of squashed instructions issued 113system.cpu.iq.iqSquashedInstsExamined 45033296 # Number of squashed instructions iterated over during squash; mainly for profiling 114system.cpu.iq.iqSquashedOperandsExamined 65280307 # Number of squashed operands that are examined and possibly removed from graph | 111system.cpu.iq.iqInstsIssued 307729409 # Number of instructions issued 112system.cpu.iq.iqSquashedInstsIssued 216713 # Number of squashed instructions issued 113system.cpu.iq.iqSquashedInstsExamined 45479887 # Number of squashed instructions iterated over during squash; mainly for profiling 114system.cpu.iq.iqSquashedOperandsExamined 66424397 # Number of squashed operands that are examined and possibly removed from graph |
| 115system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed | 115system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed |
| 116system.cpu.iq.issued_per_cycle::samples 128658357 # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::mean 2.392524 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::stdev 1.788521 # Number of insts issued each cycle | 116system.cpu.iq.issued_per_cycle::samples 122946211 # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::mean 2.502960 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::stdev 1.799833 # Number of insts issued each cycle |
| 119system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 119system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 120system.cpu.iq.issued_per_cycle::0 25721748 19.99% 19.99% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::1 18649480 14.50% 34.49% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::2 23014823 17.89% 52.38% # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::3 27362657 21.27% 73.64% # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::4 17010472 13.22% 86.87% # Number of insts issued each cycle 125system.cpu.iq.issued_per_cycle::5 9600725 7.46% 94.33% # Number of insts issued each cycle 126system.cpu.iq.issued_per_cycle::6 6243189 4.85% 99.18% # Number of insts issued each cycle 127system.cpu.iq.issued_per_cycle::7 895594 0.70% 99.88% # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::8 159669 0.12% 100.00% # Number of insts issued each cycle | 120system.cpu.iq.issued_per_cycle::0 21631935 17.59% 17.59% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::1 17051158 13.87% 31.46% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::2 24526773 19.95% 51.41% # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::3 23966381 19.49% 70.91% # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::4 19143829 15.57% 86.48% # Number of insts issued each cycle 125system.cpu.iq.issued_per_cycle::5 9189049 7.47% 93.95% # Number of insts issued each cycle 126system.cpu.iq.issued_per_cycle::6 5012385 4.08% 98.03% # Number of insts issued each cycle 127system.cpu.iq.issued_per_cycle::7 2266917 1.84% 99.87% # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::8 157784 0.13% 100.00% # Number of insts issued each cycle |
| 129system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 129system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 132system.cpu.iq.issued_per_cycle::total 128658357 # Number of insts issued each cycle | 132system.cpu.iq.issued_per_cycle::total 122946211 # Number of insts issued each cycle |
| 133system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 133system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 134system.cpu.iq.fu_full::IntAlu 35279 1.70% 1.70% # attempts to use FU when none available 135system.cpu.iq.fu_full::IntMult 0 0.00% 1.70% # attempts to use FU when none available 136system.cpu.iq.fu_full::IntDiv 0 0.00% 1.70% # attempts to use FU when none available 137system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.70% # attempts to use FU when none available 138system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.70% # attempts to use FU when none available 139system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.70% # attempts to use FU when none available 140system.cpu.iq.fu_full::FloatMult 0 0.00% 1.70% # attempts to use FU when none available 141system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.70% # attempts to use FU when none available 142system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.70% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.70% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.70% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.70% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.70% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.70% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.70% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdMult 0 0.00% 1.70% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.70% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdShift 0 0.00% 1.70% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.70% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.70% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.70% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.70% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.70% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.70% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.70% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.70% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.70% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.70% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.70% # attempts to use FU when none available 163system.cpu.iq.fu_full::MemRead 1868126 90.18% 91.88% # attempts to use FU when none available 164system.cpu.iq.fu_full::MemWrite 168108 8.12% 100.00% # attempts to use FU when none available | 134system.cpu.iq.fu_full::IntAlu 50945 1.97% 1.97% # attempts to use FU when none available 135system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available 136system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available 137system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available 138system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available 139system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available 140system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available 141system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available 142system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 163system.cpu.iq.fu_full::MemRead 1871750 72.23% 74.20% # attempts to use FU when none available 164system.cpu.iq.fu_full::MemWrite 668572 25.80% 100.00% # attempts to use FU when none available |
| 165system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 165system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 167system.cpu.iq.FU_type_0::No_OpClass 29245 0.01% 0.01% # Type of FU issued 168system.cpu.iq.FU_type_0::IntAlu 174946374 56.83% 56.84% # Type of FU issued | 167system.cpu.iq.FU_type_0::No_OpClass 33168 0.01% 0.01% # Type of FU issued 168system.cpu.iq.FU_type_0::IntAlu 174887442 56.83% 56.84% # Type of FU issued |
| 169system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued 170system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued | 169system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued 170system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued |
| 171system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.84% # Type of FU issued | 171system.cpu.iq.FU_type_0::FloatAdd 52 0.00% 56.84% # Type of FU issued |
| 172system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued 173system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued 174system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued 175system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued 176system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 189system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued | 172system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued 173system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued 174system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued 175system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued 176system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 189system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued |
| 197system.cpu.iq.FU_type_0::MemRead 99043059 32.18% 89.02% # Type of FU issued 198system.cpu.iq.FU_type_0::MemWrite 33799538 10.98% 100.00% # Type of FU issued | 197system.cpu.iq.FU_type_0::MemRead 98817076 32.11% 88.95% # Type of FU issued 198system.cpu.iq.FU_type_0::MemWrite 33991671 11.05% 100.00% # Type of FU issued |
| 199system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 200system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 199system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 200system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 201system.cpu.iq.FU_type_0::total 307818254 # Type of FU issued 202system.cpu.iq.rate 2.391897 # Inst issue rate 203system.cpu.iq.fu_busy_cnt 2071513 # FU busy when requested 204system.cpu.iq.fu_busy_rate 0.006730 # FU busy rate (busy events/executed inst) 205system.cpu.iq.int_inst_queue_reads 746564211 # Number of integer instruction queue reads 206system.cpu.iq.int_inst_queue_writes 368519272 # Number of integer instruction queue writes 207system.cpu.iq.int_inst_queue_wakeup_accesses 304587112 # Number of integer instruction queue wakeup accesses 208system.cpu.iq.fp_inst_queue_reads 554 # Number of floating instruction queue reads 209system.cpu.iq.fp_inst_queue_writes 943 # Number of floating instruction queue writes 210system.cpu.iq.fp_inst_queue_wakeup_accesses 186 # Number of floating instruction queue wakeup accesses 211system.cpu.iq.int_alu_accesses 309860246 # Number of integer alu accesses 212system.cpu.iq.fp_alu_accesses 276 # Number of floating point alu accesses 213system.cpu.iew.lsq.thread0.forwLoads 52574701 # Number of loads that had data forwarded from stores | 201system.cpu.iq.FU_type_0::total 307729409 # Type of FU issued 202system.cpu.iq.rate 2.502376 # Inst issue rate 203system.cpu.iq.fu_busy_cnt 2591267 # FU busy when requested 204system.cpu.iq.fu_busy_rate 0.008421 # FU busy rate (busy events/executed inst) 205system.cpu.iq.int_inst_queue_reads 741212334 # Number of integer instruction queue reads 206system.cpu.iq.int_inst_queue_writes 369384855 # Number of integer instruction queue writes 207system.cpu.iq.int_inst_queue_wakeup_accesses 304533759 # Number of integer instruction queue wakeup accesses 208system.cpu.iq.fp_inst_queue_reads 675 # Number of floating instruction queue reads 209system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes 210system.cpu.iq.fp_inst_queue_wakeup_accesses 209 # Number of floating instruction queue wakeup accesses 211system.cpu.iq.int_alu_accesses 310287186 # Number of integer alu accesses 212system.cpu.iq.fp_alu_accesses 322 # Number of floating point alu accesses 213system.cpu.iew.lsq.thread0.forwLoads 52324197 # Number of loads that had data forwarded from stores |
| 214system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 214system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 215system.cpu.iew.lsq.thread0.squashedLoads 13815376 # Number of loads squashed 216system.cpu.iew.lsq.thread0.ignoredResponses 44181 # Number of memory responses ignored because the instruction is squashed 217system.cpu.iew.lsq.thread0.memOrderViolation 33341 # Number of memory ordering violations 218system.cpu.iew.lsq.thread0.squashedStores 4895010 # Number of stores squashed | 215system.cpu.iew.lsq.thread0.squashedLoads 14158611 # Number of loads squashed 216system.cpu.iew.lsq.thread0.ignoredResponses 53020 # Number of memory responses ignored because the instruction is squashed 217system.cpu.iew.lsq.thread0.memOrderViolation 31592 # Number of memory ordering violations 218system.cpu.iew.lsq.thread0.squashedStores 5034695 # Number of stores squashed |
| 219system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 220system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 219system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 220system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 221system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled 222system.cpu.iew.lsq.thread0.cacheBlocked 36659 # Number of times an access to memory failed due to the cache being blocked | 221system.cpu.iew.lsq.thread0.rescheduledLoads 3174 # Number of loads that were rescheduled 222system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked |
| 223system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 223system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 224system.cpu.iew.iewSquashCycles 6221157 # Number of cycles IEW is squashing 225system.cpu.iew.iewBlockCycles 782061 # Number of cycles IEW is blocking 226system.cpu.iew.iewUnblockCycles 89817 # Number of cycles IEW is unblocking 227system.cpu.iew.iewDispatchedInsts 323454406 # Number of instructions dispatched to IQ 228system.cpu.iew.iewDispSquashedInsts 362446 # Number of squashed instructions skipped by dispatch 229system.cpu.iew.iewDispLoadInsts 104594760 # Number of dispatched load instructions 230system.cpu.iew.iewDispStoreInsts 36334761 # Number of dispatched store instructions 231system.cpu.iew.iewDispNonSpecInsts 480 # Number of dispatched non-speculative instructions 232system.cpu.iew.iewIQFullEvents 611 # Number of times the IQ has become full, causing a stall 233system.cpu.iew.iewLSQFullEvents 22270 # Number of times the LSQ has become full, causing a stall 234system.cpu.iew.memOrderViolationEvents 33341 # Number of memory order violations 235system.cpu.iew.predictedTakenIncorrect 595275 # Number of branches that were predicted taken incorrectly 236system.cpu.iew.predictedNotTakenIncorrect 582931 # Number of branches that were predicted not taken incorrectly 237system.cpu.iew.branchMispredicts 1178206 # Number of branch mispredicts detected at execute 238system.cpu.iew.iewExecutedInsts 305708901 # Number of executed instructions 239system.cpu.iew.iewExecLoadInsts 98426933 # Number of load instructions executed 240system.cpu.iew.iewExecSquashedInsts 2109353 # Number of squashed instructions skipped in execute | 224system.cpu.iew.iewSquashCycles 6235050 # Number of cycles IEW is squashing 225system.cpu.iew.iewBlockCycles 247932 # Number of cycles IEW is blocking 226system.cpu.iew.iewUnblockCycles 19449 # Number of cycles IEW is unblocking 227system.cpu.iew.iewDispatchedInsts 323875287 # Number of instructions dispatched to IQ 228system.cpu.iew.iewDispSquashedInsts 344865 # Number of squashed instructions skipped by dispatch 229system.cpu.iew.iewDispLoadInsts 104937995 # Number of dispatched load instructions 230system.cpu.iew.iewDispStoreInsts 36474446 # Number of dispatched store instructions 231system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions 232system.cpu.iew.iewIQFullEvents 247 # Number of times the IQ has become full, causing a stall 233system.cpu.iew.iewLSQFullEvents 894 # Number of times the LSQ has become full, causing a stall 234system.cpu.iew.memOrderViolationEvents 31592 # Number of memory order violations 235system.cpu.iew.predictedTakenIncorrect 595265 # Number of branches that were predicted taken incorrectly 236system.cpu.iew.predictedNotTakenIncorrect 583416 # Number of branches that were predicted not taken incorrectly 237system.cpu.iew.branchMispredicts 1178681 # Number of branch mispredicts detected at execute 238system.cpu.iew.iewExecutedInsts 305536893 # Number of executed instructions 239system.cpu.iew.iewExecLoadInsts 98199399 # Number of load instructions executed 240system.cpu.iew.iewExecSquashedInsts 2192516 # Number of squashed instructions skipped in execute |
| 241system.cpu.iew.exec_swp 0 # number of swp insts executed 242system.cpu.iew.exec_nop 0 # number of nop insts executed | 241system.cpu.iew.exec_swp 0 # number of swp insts executed 242system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 243system.cpu.iew.exec_refs 131805652 # number of memory reference insts executed 244system.cpu.iew.exec_branches 31122940 # Number of branches executed 245system.cpu.iew.exec_stores 33378719 # Number of stores executed 246system.cpu.iew.exec_rate 2.375507 # Inst execution rate 247system.cpu.iew.wb_sent 305078305 # cumulative count of insts sent to commit 248system.cpu.iew.wb_count 304587298 # cumulative count of insts written-back 249system.cpu.iew.wb_producers 225979119 # num instructions producing a value 250system.cpu.iew.wb_consumers 311384301 # num instructions consuming a value | 243system.cpu.iew.exec_refs 131640830 # number of memory reference insts executed 244system.cpu.iew.exec_branches 31219911 # Number of branches executed 245system.cpu.iew.exec_stores 33441431 # Number of stores executed 246system.cpu.iew.exec_rate 2.484547 # Inst execution rate 247system.cpu.iew.wb_sent 304949933 # cumulative count of insts sent to commit 248system.cpu.iew.wb_count 304533968 # cumulative count of insts written-back 249system.cpu.iew.wb_producers 225863686 # num instructions producing a value 250system.cpu.iew.wb_consumers 311805704 # num instructions consuming a value |
| 251system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 251system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 252system.cpu.iew.wb_rate 2.366791 # insts written-back per cycle 253system.cpu.iew.wb_fanout 0.725724 # average fanout of values written-back | 252system.cpu.iew.wb_rate 2.476392 # insts written-back per cycle 253system.cpu.iew.wb_fanout 0.724373 # average fanout of values written-back |
| 254system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 254system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 255system.cpu.commit.commitSquashedInsts 45269554 # The number of squashed insts skipped by commit | 255system.cpu.commit.commitSquashedInsts 45684582 # The number of squashed insts skipped by commit |
| 256system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards | 256system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards |
| 257system.cpu.commit.branchMispredicts 1085338 # The number of times a branch was mispredicted 258system.cpu.commit.committed_per_cycle::samples 122437200 # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::mean 2.272124 # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::stdev 2.827291 # Number of insts commited each cycle | 257system.cpu.commit.branchMispredicts 1083935 # The number of times a branch was mispredicted 258system.cpu.commit.committed_per_cycle::samples 116711161 # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::mean 2.383598 # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::stdev 2.781080 # Number of insts commited each cycle |
| 261system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 261system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 262system.cpu.commit.committed_per_cycle::0 46942462 38.34% 38.34% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::1 21185475 17.30% 55.64% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::2 15973782 13.05% 68.69% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::3 12948459 10.58% 79.27% # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::4 1961875 1.60% 80.87% # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::5 1887285 1.54% 82.41% # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::6 1388960 1.13% 83.54% # Number of insts commited each cycle 269system.cpu.commit.committed_per_cycle::7 594855 0.49% 84.03% # Number of insts commited each cycle 270system.cpu.commit.committed_per_cycle::8 19554047 15.97% 100.00% # Number of insts commited each cycle | 262system.cpu.commit.committed_per_cycle::0 38716768 33.17% 33.17% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::1 22386952 19.18% 52.35% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::2 17053265 14.61% 66.97% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::3 13105313 11.23% 78.20% # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::4 2048873 1.76% 79.95% # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::5 3220721 2.76% 82.71% # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::6 1361336 1.17% 83.88% # Number of insts commited each cycle 269system.cpu.commit.committed_per_cycle::7 627536 0.54% 84.41% # Number of insts commited each cycle 270system.cpu.commit.committed_per_cycle::8 18190397 15.59% 100.00% # Number of insts commited each cycle |
| 271system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 272system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 273system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 271system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 272system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 273system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 274system.cpu.commit.committed_per_cycle::total 122437200 # Number of insts commited each cycle | 274system.cpu.commit.committed_per_cycle::total 116711161 # Number of insts commited each cycle |
| 275system.cpu.commit.committedInsts 157988547 # Number of instructions committed 276system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed 277system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 278system.cpu.commit.refs 122219135 # Number of memory references committed 279system.cpu.commit.loads 90779384 # Number of loads committed 280system.cpu.commit.membars 0 # Number of memory barriers committed 281system.cpu.commit.branches 29309705 # Number of branches committed 282system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 283system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. 284system.cpu.commit.function_calls 0 # Number of function calls committed. | 275system.cpu.commit.committedInsts 157988547 # Number of instructions committed 276system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed 277system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 278system.cpu.commit.refs 122219135 # Number of memory references committed 279system.cpu.commit.loads 90779384 # Number of loads committed 280system.cpu.commit.membars 0 # Number of memory barriers committed 281system.cpu.commit.branches 29309705 # Number of branches committed 282system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 283system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. 284system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 285system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached | 285system.cpu.commit.bw_lim_events 18190397 # number cycles where commit BW limit reached |
| 286system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 286system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 287system.cpu.rob.rob_reads 426345169 # The number of ROB reads 288system.cpu.rob.rob_writes 653150724 # The number of ROB writes 289system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself 290system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling | 287system.cpu.rob.rob_reads 422397808 # The number of ROB reads 288system.cpu.rob.rob_writes 653994696 # The number of ROB writes 289system.cpu.timesIdled 646 # Number of times that the entire CPU went into an idle state and unscheduled itself 290system.cpu.idleCycles 28665 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 291system.cpu.committedInsts 157988547 # Number of Instructions Simulated 292system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated 293system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 291system.cpu.committedInsts 157988547 # Number of Instructions Simulated 292system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated 293system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 294system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction 295system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads 296system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle 297system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads 298system.cpu.int_regfile_reads 598601369 # number of integer regfile reads 299system.cpu.int_regfile_writes 305356910 # number of integer regfile writes 300system.cpu.fp_regfile_reads 165 # number of floating regfile reads 301system.cpu.fp_regfile_writes 88 # number of floating regfile writes 302system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads 303system.cpu.icache.replacements 92 # number of replacements 304system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use 305system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. 306system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. 307system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. | 294system.cpu.cpi 0.778378 # CPI: Cycles Per Instruction 295system.cpu.cpi_total 0.778378 # CPI: Total CPI of All Threads 296system.cpu.ipc 1.284722 # IPC: Instructions Per Cycle 297system.cpu.ipc_total 1.284722 # IPC: Total IPC of All Threads 298system.cpu.int_regfile_reads 598611638 # number of integer regfile reads 299system.cpu.int_regfile_writes 305159096 # number of integer regfile writes 300system.cpu.fp_regfile_reads 198 # number of floating regfile reads 301system.cpu.fp_regfile_writes 109 # number of floating regfile writes 302system.cpu.misc_regfile_reads 195504004 # number of misc regfile reads 303system.cpu.icache.replacements 86 # number of replacements 304system.cpu.icache.tagsinuse 846.025687 # Cycle average of tags in use 305system.cpu.icache.total_refs 27171094 # Total number of references to valid blocks. 306system.cpu.icache.sampled_refs 1075 # Sample count of references to valid blocks. 307system.cpu.icache.avg_refs 25275.436279 # Average number of references to valid blocks. |
| 308system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 308system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 309system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor 310system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy 311system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy 312system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits 313system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits 314system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits 315system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits 316system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits 317system.cpu.icache.overall_hits::total 27158782 # number of overall hits 318system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses 319system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses 320system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses 321system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses 322system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses 323system.cpu.icache.overall_misses::total 1385 # number of overall misses 324system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles 325system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles 326system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles 327system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles 328system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles 329system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles 330system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) 331system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses 333system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses 334system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses 335system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses | 309system.cpu.icache.occ_blocks::cpu.inst 846.025687 # Average occupied blocks per requestor 310system.cpu.icache.occ_percent::cpu.inst 0.413098 # Average percentage of cache occupancy 311system.cpu.icache.occ_percent::total 0.413098 # Average percentage of cache occupancy 312system.cpu.icache.ReadReq_hits::cpu.inst 27171094 # number of ReadReq hits 313system.cpu.icache.ReadReq_hits::total 27171094 # number of ReadReq hits 314system.cpu.icache.demand_hits::cpu.inst 27171094 # number of demand (read+write) hits 315system.cpu.icache.demand_hits::total 27171094 # number of demand (read+write) hits 316system.cpu.icache.overall_hits::cpu.inst 27171094 # number of overall hits 317system.cpu.icache.overall_hits::total 27171094 # number of overall hits 318system.cpu.icache.ReadReq_misses::cpu.inst 1397 # number of ReadReq misses 319system.cpu.icache.ReadReq_misses::total 1397 # number of ReadReq misses 320system.cpu.icache.demand_misses::cpu.inst 1397 # number of demand (read+write) misses 321system.cpu.icache.demand_misses::total 1397 # number of demand (read+write) misses 322system.cpu.icache.overall_misses::cpu.inst 1397 # number of overall misses 323system.cpu.icache.overall_misses::total 1397 # number of overall misses 324system.cpu.icache.ReadReq_miss_latency::cpu.inst 49824500 # number of ReadReq miss cycles 325system.cpu.icache.ReadReq_miss_latency::total 49824500 # number of ReadReq miss cycles 326system.cpu.icache.demand_miss_latency::cpu.inst 49824500 # number of demand (read+write) miss cycles 327system.cpu.icache.demand_miss_latency::total 49824500 # number of demand (read+write) miss cycles 328system.cpu.icache.overall_miss_latency::cpu.inst 49824500 # number of overall miss cycles 329system.cpu.icache.overall_miss_latency::total 49824500 # number of overall miss cycles 330system.cpu.icache.ReadReq_accesses::cpu.inst 27172491 # number of ReadReq accesses(hits+misses) 331system.cpu.icache.ReadReq_accesses::total 27172491 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.demand_accesses::cpu.inst 27172491 # number of demand (read+write) accesses 333system.cpu.icache.demand_accesses::total 27172491 # number of demand (read+write) accesses 334system.cpu.icache.overall_accesses::cpu.inst 27172491 # number of overall (read+write) accesses 335system.cpu.icache.overall_accesses::total 27172491 # number of overall (read+write) accesses |
| 336system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 337system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 338system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 339system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 341system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses | 336system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 337system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 338system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 339system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 341system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses |
| 342system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37151.985560 # average ReadReq miss latency 343system.cpu.icache.ReadReq_avg_miss_latency::total 37151.985560 # average ReadReq miss latency 344system.cpu.icache.demand_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency 345system.cpu.icache.demand_avg_miss_latency::total 37151.985560 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::total 37151.985560 # average overall miss latency | 342system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35665.354331 # average ReadReq miss latency 343system.cpu.icache.ReadReq_avg_miss_latency::total 35665.354331 # average ReadReq miss latency 344system.cpu.icache.demand_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency 345system.cpu.icache.demand_avg_miss_latency::total 35665.354331 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::total 35665.354331 # average overall miss latency |
| 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed | 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 356system.cpu.icache.ReadReq_mshr_hits::cpu.inst 307 # number of ReadReq MSHR hits 357system.cpu.icache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits 358system.cpu.icache.demand_mshr_hits::cpu.inst 307 # number of demand (read+write) MSHR hits 359system.cpu.icache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits 360system.cpu.icache.overall_mshr_hits::cpu.inst 307 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 307 # number of overall MSHR hits 362system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses 363system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses 364system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses 365system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses 366system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses 367system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39438000 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 39438000 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39438000 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 39438000 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39438000 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 39438000 # number of overall MSHR miss cycles | 356system.cpu.icache.ReadReq_mshr_hits::cpu.inst 320 # number of ReadReq MSHR hits 357system.cpu.icache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits 358system.cpu.icache.demand_mshr_hits::cpu.inst 320 # number of demand (read+write) MSHR hits 359system.cpu.icache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits 360system.cpu.icache.overall_mshr_hits::cpu.inst 320 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 320 # number of overall MSHR hits 362system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses 363system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses 364system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses 365system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses 366system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses 367system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39164500 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 39164500 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39164500 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 39164500 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39164500 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 39164500 # number of overall MSHR miss cycles |
| 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 376system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 377system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 378system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 379system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 376system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 377system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 378system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 379system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 380system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36584.415584 # average ReadReq mshr miss latency 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36584.415584 # average ReadReq mshr miss latency 382system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency | 380system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36364.438254 # average ReadReq mshr miss latency 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36364.438254 # average ReadReq mshr miss latency 382system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency |
| 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 387system.cpu.dcache.replacements 2072148 # number of replacements 388system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use 389system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks. 390system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks. 391system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks. 392system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit. 393system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor 394system.cpu.dcache.occ_percent::cpu.data 0.994148 # Average percentage of cache occupancy 395system.cpu.dcache.occ_percent::total 0.994148 # Average percentage of cache occupancy 396system.cpu.dcache.ReadReq_hits::cpu.data 43467724 # number of ReadReq hits 397system.cpu.dcache.ReadReq_hits::total 43467724 # number of ReadReq hits 398system.cpu.dcache.WriteReq_hits::cpu.data 31357249 # number of WriteReq hits 399system.cpu.dcache.WriteReq_hits::total 31357249 # number of WriteReq hits 400system.cpu.dcache.demand_hits::cpu.data 74824973 # number of demand (read+write) hits 401system.cpu.dcache.demand_hits::total 74824973 # number of demand (read+write) hits 402system.cpu.dcache.overall_hits::cpu.data 74824973 # number of overall hits 403system.cpu.dcache.overall_hits::total 74824973 # number of overall hits 404system.cpu.dcache.ReadReq_misses::cpu.data 2321557 # number of ReadReq misses 405system.cpu.dcache.ReadReq_misses::total 2321557 # number of ReadReq misses 406system.cpu.dcache.WriteReq_misses::cpu.data 82502 # number of WriteReq misses 407system.cpu.dcache.WriteReq_misses::total 82502 # number of WriteReq misses 408system.cpu.dcache.demand_misses::cpu.data 2404059 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 2404059 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 2404059 # number of overall misses 411system.cpu.dcache.overall_misses::total 2404059 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 19393584000 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 19393584000 # number of ReadReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571938000 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 1571938000 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 20965522000 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 20965522000 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 20965522000 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 20965522000 # number of overall miss cycles 420system.cpu.dcache.ReadReq_accesses::cpu.data 45789281 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 45789281 # number of ReadReq accesses(hits+misses) | 387system.cpu.dcache.replacements 2071944 # number of replacements 388system.cpu.dcache.tagsinuse 4071.467534 # Cycle average of tags in use 389system.cpu.dcache.total_refs 74936342 # Total number of references to valid blocks. 390system.cpu.dcache.sampled_refs 2076040 # Sample count of references to valid blocks. 391system.cpu.dcache.avg_refs 36.095808 # Average number of references to valid blocks. 392system.cpu.dcache.warmup_cycle 21468323000 # Cycle when the warmup percentage was hit. 393system.cpu.dcache.occ_blocks::cpu.data 4071.467534 # Average occupied blocks per requestor 394system.cpu.dcache.occ_percent::cpu.data 0.994011 # Average percentage of cache occupancy 395system.cpu.dcache.occ_percent::total 0.994011 # Average percentage of cache occupancy 396system.cpu.dcache.ReadReq_hits::cpu.data 43578741 # number of ReadReq hits 397system.cpu.dcache.ReadReq_hits::total 43578741 # number of ReadReq hits 398system.cpu.dcache.WriteReq_hits::cpu.data 31357591 # number of WriteReq hits 399system.cpu.dcache.WriteReq_hits::total 31357591 # number of WriteReq hits 400system.cpu.dcache.demand_hits::cpu.data 74936332 # number of demand (read+write) hits 401system.cpu.dcache.demand_hits::total 74936332 # number of demand (read+write) hits 402system.cpu.dcache.overall_hits::cpu.data 74936332 # number of overall hits 403system.cpu.dcache.overall_hits::total 74936332 # number of overall hits 404system.cpu.dcache.ReadReq_misses::cpu.data 2256554 # number of ReadReq misses 405system.cpu.dcache.ReadReq_misses::total 2256554 # number of ReadReq misses 406system.cpu.dcache.WriteReq_misses::cpu.data 82160 # number of WriteReq misses 407system.cpu.dcache.WriteReq_misses::total 82160 # number of WriteReq misses 408system.cpu.dcache.demand_misses::cpu.data 2338714 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 2338714 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 2338714 # number of overall misses 411system.cpu.dcache.overall_misses::total 2338714 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 9114703500 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 9114703500 # number of ReadReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 1290980000 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 1290980000 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 10405683500 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 10405683500 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 10405683500 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 10405683500 # number of overall miss cycles 420system.cpu.dcache.ReadReq_accesses::cpu.data 45835295 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 45835295 # number of ReadReq accesses(hits+misses) |
| 422system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) | 422system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) |
| 424system.cpu.dcache.demand_accesses::cpu.data 77229032 # number of demand (read+write) accesses 425system.cpu.dcache.demand_accesses::total 77229032 # number of demand (read+write) accesses 426system.cpu.dcache.overall_accesses::cpu.data 77229032 # number of overall (read+write) accesses 427system.cpu.dcache.overall_accesses::total 77229032 # number of overall (read+write) accesses 428system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050701 # miss rate for ReadReq accesses 429system.cpu.dcache.ReadReq_miss_rate::total 0.050701 # miss rate for ReadReq accesses 430system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses 431system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses 432system.cpu.dcache.demand_miss_rate::cpu.data 0.031129 # miss rate for demand accesses 433system.cpu.dcache.demand_miss_rate::total 0.031129 # miss rate for demand accesses 434system.cpu.dcache.overall_miss_rate::cpu.data 0.031129 # miss rate for overall accesses 435system.cpu.dcache.overall_miss_rate::total 0.031129 # miss rate for overall accesses 436system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8353.697109 # average ReadReq miss latency 437system.cpu.dcache.ReadReq_avg_miss_latency::total 8353.697109 # average ReadReq miss latency 438system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19053.332040 # average WriteReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::total 19053.332040 # average WriteReq miss latency 440system.cpu.dcache.demand_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency 441system.cpu.dcache.demand_avg_miss_latency::total 8720.884970 # average overall miss latency 442system.cpu.dcache.overall_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::total 8720.884970 # average overall miss latency | 424system.cpu.dcache.demand_accesses::cpu.data 77275046 # number of demand (read+write) accesses 425system.cpu.dcache.demand_accesses::total 77275046 # number of demand (read+write) accesses 426system.cpu.dcache.overall_accesses::cpu.data 77275046 # number of overall (read+write) accesses 427system.cpu.dcache.overall_accesses::total 77275046 # number of overall (read+write) accesses 428system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049232 # miss rate for ReadReq accesses 429system.cpu.dcache.ReadReq_miss_rate::total 0.049232 # miss rate for ReadReq accesses 430system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002613 # miss rate for WriteReq accesses 431system.cpu.dcache.WriteReq_miss_rate::total 0.002613 # miss rate for WriteReq accesses 432system.cpu.dcache.demand_miss_rate::cpu.data 0.030265 # miss rate for demand accesses 433system.cpu.dcache.demand_miss_rate::total 0.030265 # miss rate for demand accesses 434system.cpu.dcache.overall_miss_rate::cpu.data 0.030265 # miss rate for overall accesses 435system.cpu.dcache.overall_miss_rate::total 0.030265 # miss rate for overall accesses 436system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4039.213553 # average ReadReq miss latency 437system.cpu.dcache.ReadReq_avg_miss_latency::total 4039.213553 # average ReadReq miss latency 438system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15712.999026 # average WriteReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::total 15712.999026 # average WriteReq miss latency 440system.cpu.dcache.demand_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency 441system.cpu.dcache.demand_avg_miss_latency::total 4449.318514 # average overall miss latency 442system.cpu.dcache.overall_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::total 4449.318514 # average overall miss latency |
| 444system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 445system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 446system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 449system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 450system.cpu.dcache.fast_writes 0 # number of fast writes performed 451system.cpu.dcache.cache_copies 0 # number of cache copies performed | 444system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 445system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 446system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 449system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 450system.cpu.dcache.fast_writes 0 # number of fast writes performed 451system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 452system.cpu.dcache.writebacks::writebacks 2064775 # number of writebacks 453system.cpu.dcache.writebacks::total 2064775 # number of writebacks 454system.cpu.dcache.ReadReq_mshr_hits::cpu.data 327358 # number of ReadReq MSHR hits 455system.cpu.dcache.ReadReq_mshr_hits::total 327358 # number of ReadReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::cpu.data 453 # number of WriteReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::total 453 # number of WriteReq MSHR hits 458system.cpu.dcache.demand_mshr_hits::cpu.data 327811 # number of demand (read+write) MSHR hits 459system.cpu.dcache.demand_mshr_hits::total 327811 # number of demand (read+write) MSHR hits 460system.cpu.dcache.overall_mshr_hits::cpu.data 327811 # number of overall MSHR hits 461system.cpu.dcache.overall_mshr_hits::total 327811 # number of overall MSHR hits 462system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994199 # number of ReadReq MSHR misses 463system.cpu.dcache.ReadReq_mshr_misses::total 1994199 # number of ReadReq MSHR misses 464system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82049 # number of WriteReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::total 82049 # number of WriteReq MSHR misses 466system.cpu.dcache.demand_mshr_misses::cpu.data 2076248 # number of demand (read+write) MSHR misses 467system.cpu.dcache.demand_mshr_misses::total 2076248 # number of demand (read+write) MSHR misses 468system.cpu.dcache.overall_mshr_misses::cpu.data 2076248 # number of overall MSHR misses 469system.cpu.dcache.overall_mshr_misses::total 2076248 # number of overall MSHR misses 470system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8452133500 # number of ReadReq MSHR miss cycles 471system.cpu.dcache.ReadReq_mshr_miss_latency::total 8452133500 # number of ReadReq MSHR miss cycles 472system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1314555500 # number of WriteReq MSHR miss cycles 473system.cpu.dcache.WriteReq_mshr_miss_latency::total 1314555500 # number of WriteReq MSHR miss cycles 474system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9766689000 # number of demand (read+write) MSHR miss cycles 475system.cpu.dcache.demand_mshr_miss_latency::total 9766689000 # number of demand (read+write) MSHR miss cycles 476system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9766689000 # number of overall MSHR miss cycles 477system.cpu.dcache.overall_mshr_miss_latency::total 9766689000 # number of overall MSHR miss cycles 478system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043552 # mshr miss rate for ReadReq accesses 479system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043552 # mshr miss rate for ReadReq accesses | 452system.cpu.dcache.writebacks::writebacks 2064785 # number of writebacks 453system.cpu.dcache.writebacks::total 2064785 # number of writebacks 454system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262571 # number of ReadReq MSHR hits 455system.cpu.dcache.ReadReq_mshr_hits::total 262571 # number of ReadReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99 # number of WriteReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::total 99 # number of WriteReq MSHR hits 458system.cpu.dcache.demand_mshr_hits::cpu.data 262670 # number of demand (read+write) MSHR hits 459system.cpu.dcache.demand_mshr_hits::total 262670 # number of demand (read+write) MSHR hits 460system.cpu.dcache.overall_mshr_hits::cpu.data 262670 # number of overall MSHR hits 461system.cpu.dcache.overall_mshr_hits::total 262670 # number of overall MSHR hits 462system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993983 # number of ReadReq MSHR misses 463system.cpu.dcache.ReadReq_mshr_misses::total 1993983 # number of ReadReq MSHR misses 464system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82061 # number of WriteReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::total 82061 # number of WriteReq MSHR misses 466system.cpu.dcache.demand_mshr_misses::cpu.data 2076044 # number of demand (read+write) MSHR misses 467system.cpu.dcache.demand_mshr_misses::total 2076044 # number of demand (read+write) MSHR misses 468system.cpu.dcache.overall_mshr_misses::cpu.data 2076044 # number of overall MSHR misses 469system.cpu.dcache.overall_mshr_misses::total 2076044 # number of overall MSHR misses 470system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4061724500 # number of ReadReq MSHR miss cycles 471system.cpu.dcache.ReadReq_mshr_miss_latency::total 4061724500 # number of ReadReq MSHR miss cycles 472system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125939500 # number of WriteReq MSHR miss cycles 473system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125939500 # number of WriteReq MSHR miss cycles 474system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5187664000 # number of demand (read+write) MSHR miss cycles 475system.cpu.dcache.demand_mshr_miss_latency::total 5187664000 # number of demand (read+write) MSHR miss cycles 476system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5187664000 # number of overall MSHR miss cycles 477system.cpu.dcache.overall_mshr_miss_latency::total 5187664000 # number of overall MSHR miss cycles 478system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043503 # mshr miss rate for ReadReq accesses 479system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043503 # mshr miss rate for ReadReq accesses |
| 480system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 481system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses | 480system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 481system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses |
| 482system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026884 # mshr miss rate for demand accesses 483system.cpu.dcache.demand_mshr_miss_rate::total 0.026884 # mshr miss rate for demand accesses 484system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026884 # mshr miss rate for overall accesses 485system.cpu.dcache.overall_mshr_miss_rate::total 0.026884 # mshr miss rate for overall accesses 486system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4238.360114 # average ReadReq mshr miss latency 487system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4238.360114 # average ReadReq mshr miss latency 488system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16021.590757 # average WriteReq mshr miss latency 489system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16021.590757 # average WriteReq mshr miss latency 490system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency 491system.cpu.dcache.demand_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency 492system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency 493system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency | 482system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for demand accesses 483system.cpu.dcache.demand_mshr_miss_rate::total 0.026866 # mshr miss rate for demand accesses 484system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for overall accesses 485system.cpu.dcache.overall_mshr_miss_rate::total 0.026866 # mshr miss rate for overall accesses 486system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2036.990536 # average ReadReq mshr miss latency 487system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2036.990536 # average ReadReq mshr miss latency 488system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13720.762603 # average WriteReq mshr miss latency 489system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13720.762603 # average WriteReq mshr miss latency 490system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency 491system.cpu.dcache.demand_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency 492system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency 493system.cpu.dcache.overall_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency |
| 494system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 494system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 495system.cpu.l2cache.replacements 1466 # number of replacements 496system.cpu.l2cache.tagsinuse 19909.538394 # Cycle average of tags in use 497system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks. 498system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks. 499system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks. | 495system.cpu.l2cache.replacements 1463 # number of replacements 496system.cpu.l2cache.tagsinuse 19632.807637 # Cycle average of tags in use 497system.cpu.l2cache.total_refs 4026981 # Total number of references to valid blocks. 498system.cpu.l2cache.sampled_refs 30627 # Sample count of references to valid blocks. 499system.cpu.l2cache.avg_refs 131.484670 # Average number of references to valid blocks. |
| 500system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 500system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 501system.cpu.l2cache.occ_blocks::writebacks 19409.012644 # Average occupied blocks per requestor 502system.cpu.l2cache.occ_blocks::cpu.inst 268.281425 # Average occupied blocks per requestor 503system.cpu.l2cache.occ_blocks::cpu.data 232.244324 # Average occupied blocks per requestor 504system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy 505system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy 506system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy 507system.cpu.l2cache.occ_percent::total 0.607591 # Average percentage of cache occupancy 508system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits 509system.cpu.l2cache.ReadReq_hits::cpu.data 1993503 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::total 1993511 # number of ReadReq hits 511system.cpu.l2cache.Writeback_hits::writebacks 2064775 # number of Writeback hits 512system.cpu.l2cache.Writeback_hits::total 2064775 # number of Writeback hits 513system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 514system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 515system.cpu.l2cache.ReadExReq_hits::cpu.data 53159 # number of ReadExReq hits 516system.cpu.l2cache.ReadExReq_hits::total 53159 # number of ReadExReq hits 517system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits 518system.cpu.l2cache.demand_hits::cpu.data 2046662 # number of demand (read+write) hits 519system.cpu.l2cache.demand_hits::total 2046670 # number of demand (read+write) hits 520system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits 521system.cpu.l2cache.overall_hits::cpu.data 2046662 # number of overall hits 522system.cpu.l2cache.overall_hits::total 2046670 # number of overall hits | 501system.cpu.l2cache.occ_blocks::writebacks 19126.604204 # Average occupied blocks per requestor 502system.cpu.l2cache.occ_blocks::cpu.inst 278.184174 # Average occupied blocks per requestor 503system.cpu.l2cache.occ_blocks::cpu.data 228.019260 # Average occupied blocks per requestor 504system.cpu.l2cache.occ_percent::writebacks 0.583698 # Average percentage of cache occupancy 505system.cpu.l2cache.occ_percent::cpu.inst 0.008490 # Average percentage of cache occupancy 506system.cpu.l2cache.occ_percent::cpu.data 0.006959 # Average percentage of cache occupancy 507system.cpu.l2cache.occ_percent::total 0.599146 # Average percentage of cache occupancy 508system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits 509system.cpu.l2cache.ReadReq_hits::cpu.data 1993318 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::total 1993325 # number of ReadReq hits 511system.cpu.l2cache.Writeback_hits::writebacks 2064785 # number of Writeback hits 512system.cpu.l2cache.Writeback_hits::total 2064785 # number of Writeback hits 513system.cpu.l2cache.ReadExReq_hits::cpu.data 53145 # number of ReadExReq hits 514system.cpu.l2cache.ReadExReq_hits::total 53145 # number of ReadExReq hits 515system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits 516system.cpu.l2cache.demand_hits::cpu.data 2046463 # number of demand (read+write) hits 517system.cpu.l2cache.demand_hits::total 2046470 # number of demand (read+write) hits 518system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits 519system.cpu.l2cache.overall_hits::cpu.data 2046463 # number of overall hits 520system.cpu.l2cache.overall_hits::total 2046470 # number of overall hits |
| 523system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses | 521system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses |
| 524system.cpu.l2cache.ReadReq_misses::cpu.data 588 # number of ReadReq misses 525system.cpu.l2cache.ReadReq_misses::total 1656 # number of ReadReq misses 526system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 527system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 528system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses 529system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses | 522system.cpu.l2cache.ReadReq_misses::cpu.data 586 # number of ReadReq misses 523system.cpu.l2cache.ReadReq_misses::total 1654 # number of ReadReq misses 524system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 525system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 526system.cpu.l2cache.ReadExReq_misses::cpu.data 28993 # number of ReadExReq misses 527system.cpu.l2cache.ReadExReq_misses::total 28993 # number of ReadExReq misses |
| 530system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses | 528system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses |
| 531system.cpu.l2cache.demand_misses::cpu.data 29584 # number of demand (read+write) misses 532system.cpu.l2cache.demand_misses::total 30652 # number of demand (read+write) misses | 529system.cpu.l2cache.demand_misses::cpu.data 29579 # number of demand (read+write) misses 530system.cpu.l2cache.demand_misses::total 30647 # number of demand (read+write) misses |
| 533system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses | 531system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses |
| 534system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses 535system.cpu.l2cache.overall_misses::total 30652 # number of overall misses 536system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37880000 # number of ReadReq miss cycles 537system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles 538system.cpu.l2cache.ReadReq_miss_latency::total 58846500 # number of ReadReq miss cycles 539system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles 540system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles 541system.cpu.l2cache.demand_miss_latency::cpu.inst 37880000 # number of demand (read+write) miss cycles 542system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles 543system.cpu.l2cache.demand_miss_latency::total 1047729000 # number of demand (read+write) miss cycles 544system.cpu.l2cache.overall_miss_latency::cpu.inst 37880000 # number of overall miss cycles 545system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles 546system.cpu.l2cache.overall_miss_latency::total 1047729000 # number of overall miss cycles 547system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) 548system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) 549system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) 550system.cpu.l2cache.Writeback_accesses::writebacks 2064775 # number of Writeback accesses(hits+misses) 551system.cpu.l2cache.Writeback_accesses::total 2064775 # number of Writeback accesses(hits+misses) | 532system.cpu.l2cache.overall_misses::cpu.data 29579 # number of overall misses 533system.cpu.l2cache.overall_misses::total 30647 # number of overall misses 534system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38066500 # number of ReadReq miss cycles 535system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21080500 # number of ReadReq miss cycles 536system.cpu.l2cache.ReadReq_miss_latency::total 59147000 # number of ReadReq miss cycles 537system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989282000 # number of ReadExReq miss cycles 538system.cpu.l2cache.ReadExReq_miss_latency::total 989282000 # number of ReadExReq miss cycles 539system.cpu.l2cache.demand_miss_latency::cpu.inst 38066500 # number of demand (read+write) miss cycles 540system.cpu.l2cache.demand_miss_latency::cpu.data 1010362500 # number of demand (read+write) miss cycles 541system.cpu.l2cache.demand_miss_latency::total 1048429000 # number of demand (read+write) miss cycles 542system.cpu.l2cache.overall_miss_latency::cpu.inst 38066500 # number of overall miss cycles 543system.cpu.l2cache.overall_miss_latency::cpu.data 1010362500 # number of overall miss cycles 544system.cpu.l2cache.overall_miss_latency::total 1048429000 # number of overall miss cycles 545system.cpu.l2cache.ReadReq_accesses::cpu.inst 1075 # number of ReadReq accesses(hits+misses) 546system.cpu.l2cache.ReadReq_accesses::cpu.data 1993904 # number of ReadReq accesses(hits+misses) 547system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) 548system.cpu.l2cache.Writeback_accesses::writebacks 2064785 # number of Writeback accesses(hits+misses) 549system.cpu.l2cache.Writeback_accesses::total 2064785 # number of Writeback accesses(hits+misses) |
| 552system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 553system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) | 550system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 551system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) |
| 554system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses) 555system.cpu.l2cache.ReadExReq_accesses::total 82155 # number of ReadExReq accesses(hits+misses) 556system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses 557system.cpu.l2cache.demand_accesses::cpu.data 2076246 # number of demand (read+write) accesses 558system.cpu.l2cache.demand_accesses::total 2077322 # number of demand (read+write) accesses 559system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses 560system.cpu.l2cache.overall_accesses::cpu.data 2076246 # number of overall (read+write) accesses 561system.cpu.l2cache.overall_accesses::total 2077322 # number of overall (read+write) accesses 562system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses 563system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses 564system.cpu.l2cache.ReadReq_miss_rate::total 0.000830 # miss rate for ReadReq accesses 565system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 566system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 567system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses 568system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses 569system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses 570system.cpu.l2cache.demand_miss_rate::cpu.data 0.014249 # miss rate for demand accesses 571system.cpu.l2cache.demand_miss_rate::total 0.014756 # miss rate for demand accesses 572system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses 573system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses 574system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses 575system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35468.164794 # average ReadReq miss latency 576system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency 577system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency 578system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency 579system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency 580system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency 581system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency 582system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency 583system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency 584system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency 585system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency | 552system.cpu.l2cache.ReadExReq_accesses::cpu.data 82138 # number of ReadExReq accesses(hits+misses) 553system.cpu.l2cache.ReadExReq_accesses::total 82138 # number of ReadExReq accesses(hits+misses) 554system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses 555system.cpu.l2cache.demand_accesses::cpu.data 2076042 # number of demand (read+write) accesses 556system.cpu.l2cache.demand_accesses::total 2077117 # number of demand (read+write) accesses 557system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses 558system.cpu.l2cache.overall_accesses::cpu.data 2076042 # number of overall (read+write) accesses 559system.cpu.l2cache.overall_accesses::total 2077117 # number of overall (read+write) accesses 560system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993488 # miss rate for ReadReq accesses 561system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000294 # miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses 563system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 564system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 565system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352979 # miss rate for ReadExReq accesses 566system.cpu.l2cache.ReadExReq_miss_rate::total 0.352979 # miss rate for ReadExReq accesses 567system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993488 # miss rate for demand accesses 568system.cpu.l2cache.demand_miss_rate::cpu.data 0.014248 # miss rate for demand accesses 569system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses 570system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993488 # miss rate for overall accesses 571system.cpu.l2cache.overall_miss_rate::cpu.data 0.014248 # miss rate for overall accesses 572system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses 573system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35642.790262 # average ReadReq miss latency 574system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35973.549488 # average ReadReq miss latency 575system.cpu.l2cache.ReadReq_avg_miss_latency::total 35759.975816 # average ReadReq miss latency 576system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34121.408616 # average ReadExReq miss latency 577system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34121.408616 # average ReadExReq miss latency 578system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency 579system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency 580system.cpu.l2cache.demand_avg_miss_latency::total 34209.841094 # average overall miss latency 581system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency 582system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency 583system.cpu.l2cache.overall_avg_miss_latency::total 34209.841094 # average overall miss latency |
| 586system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.l2cache.fast_writes 0 # number of fast writes performed 593system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 584system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 585system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 586system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 588system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 589system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 590system.cpu.l2cache.fast_writes 0 # number of fast writes performed 591system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 594system.cpu.l2cache.writebacks::writebacks 319 # number of writebacks 595system.cpu.l2cache.writebacks::total 319 # number of writebacks | 592system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks 593system.cpu.l2cache.writebacks::total 317 # number of writebacks |
| 596system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses | 594system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses |
| 597system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses 598system.cpu.l2cache.ReadReq_mshr_misses::total 1656 # number of ReadReq MSHR misses 599system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 600system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 601system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses 602system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses | 595system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 586 # number of ReadReq MSHR misses 596system.cpu.l2cache.ReadReq_mshr_misses::total 1654 # number of ReadReq MSHR misses 597system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 598system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 599system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses 600system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses |
| 603system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses | 601system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses |
| 604system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses 605system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses | 602system.cpu.l2cache.demand_mshr_misses::cpu.data 29579 # number of demand (read+write) MSHR misses 603system.cpu.l2cache.demand_mshr_misses::total 30647 # number of demand (read+write) MSHR misses |
| 606system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses | 604system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses |
| 607system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses 608system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses 609system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles 610system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles 611system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles 612system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles 613system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles 614system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles 615system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles 616system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles 617system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles 618system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles 619system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles 620system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles 621system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles 622system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses 624system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses 625system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 626system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 627system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses 628system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses 629system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses 630system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses 631system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses 632system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses 633system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses 634system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses 635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency 636system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency 637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency | 605system.cpu.l2cache.overall_mshr_misses::cpu.data 29579 # number of overall MSHR misses 606system.cpu.l2cache.overall_mshr_misses::total 30647 # number of overall MSHR misses 607system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34670500 # number of ReadReq MSHR miss cycles 608system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19225500 # number of ReadReq MSHR miss cycles 609system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53896000 # number of ReadReq MSHR miss cycles 610system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles 611system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles 612system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899128500 # number of ReadExReq MSHR miss cycles 613system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899128500 # number of ReadExReq MSHR miss cycles 614system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34670500 # number of demand (read+write) MSHR miss cycles 615system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918354000 # number of demand (read+write) MSHR miss cycles 616system.cpu.l2cache.demand_mshr_miss_latency::total 953024500 # number of demand (read+write) MSHR miss cycles 617system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34670500 # number of overall MSHR miss cycles 618system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918354000 # number of overall MSHR miss cycles 619system.cpu.l2cache.overall_mshr_miss_latency::total 953024500 # number of overall MSHR miss cycles 620system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses 622system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses 623system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 624system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 625system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352979 # mshr miss rate for ReadExReq accesses 626system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352979 # mshr miss rate for ReadExReq accesses 627system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for demand accesses 628system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses 629system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses 630system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for overall accesses 631system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses 632system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses 633system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32463.014981 # average ReadReq mshr miss latency 634system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32808.020478 # average ReadReq mshr miss latency 635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32585.247884 # average ReadReq mshr miss latency |
| 638system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 639system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency | 636system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 637system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency |
| 640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency 641system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency 642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency 643system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency 644system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency 645system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency 646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency | 638system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.916670 # average ReadExReq mshr miss latency 639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.916670 # average ReadExReq mshr miss latency 640system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency 641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency 642system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency 643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency 644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency 645system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency |
| 648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 649 650---------- End Simulation Statistics ---------- | 646system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 647 648---------- End Simulation Statistics ---------- |