| stats.txt (9223:be1c1059438b) | stats.txt (9229:65f927bda74d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.064346 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.064346 # Number of seconds simulated |
| 4sim_ticks 64346039000 # Number of ticks simulated 5final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 64346040000 # Number of ticks simulated 5final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 77016 # Simulator instruction rate (inst/s) 8host_op_rate 135613 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31367260 # Simulator tick rate (ticks/s) 10host_mem_usage 410996 # Number of bytes of host memory used 11host_seconds 2051.38 # Real time elapsed on the host | 7host_inst_rate 132449 # Simulator instruction rate (inst/s) 8host_op_rate 233222 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53944275 # Simulator tick rate (ticks/s) 10host_mem_usage 365660 # Number of bytes of host memory used 11host_seconds 1192.82 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192462 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20416 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 319 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192462 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20416 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 319 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) |
| 27system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s) |
| 28system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) | 28system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) |
| 35system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.workload.num_syscalls 444 # Number of system calls | 37system.cpu.workload.num_syscalls 444 # Number of system calls |
| 38system.cpu.numCycles 128692079 # number of cpu cycles simulated | 38system.cpu.numCycles 128692081 # number of cpu cycles simulated |
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups 45system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. --- 235 unchanged lines hidden (view full) --- 282system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 283system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. 284system.cpu.commit.function_calls 0 # Number of function calls committed. 285system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached 286system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 287system.cpu.rob.rob_reads 426345169 # The number of ROB reads 288system.cpu.rob.rob_writes 653150724 # The number of ROB writes 289system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself | 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups 45system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. --- 235 unchanged lines hidden (view full) --- 282system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 283system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. 284system.cpu.commit.function_calls 0 # Number of function calls committed. 285system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached 286system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 287system.cpu.rob.rob_reads 426345169 # The number of ROB reads 288system.cpu.rob.rob_writes 653150724 # The number of ROB writes 289system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 290system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling | 290system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 291system.cpu.committedInsts 157988547 # Number of Instructions Simulated 292system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated 293system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated 294system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction 295system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads 296system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle 297system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads 298system.cpu.int_regfile_reads 598601369 # number of integer regfile reads 299system.cpu.int_regfile_writes 305356910 # number of integer regfile writes 300system.cpu.fp_regfile_reads 165 # number of floating regfile reads 301system.cpu.fp_regfile_writes 88 # number of floating regfile writes 302system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads 303system.cpu.icache.replacements 92 # number of replacements | 291system.cpu.committedInsts 157988547 # Number of Instructions Simulated 292system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated 293system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated 294system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction 295system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads 296system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle 297system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads 298system.cpu.int_regfile_reads 598601369 # number of integer regfile reads 299system.cpu.int_regfile_writes 305356910 # number of integer regfile writes 300system.cpu.fp_regfile_reads 165 # number of floating regfile reads 301system.cpu.fp_regfile_writes 88 # number of floating regfile writes 302system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads 303system.cpu.icache.replacements 92 # number of replacements |
| 304system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use | 304system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use |
| 305system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. 306system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. 307system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. 308system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 305system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. 306system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. 307system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. 308system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 309system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor | 309system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor |
| 310system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy 311system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy 312system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits 313system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits 314system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits 315system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits 316system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits 317system.cpu.icache.overall_hits::total 27158782 # number of overall hits 318system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses 319system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses 320system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses 321system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses 322system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses 323system.cpu.icache.overall_misses::total 1385 # number of overall misses | 310system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy 311system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy 312system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits 313system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits 314system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits 315system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits 316system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits 317system.cpu.icache.overall_hits::total 27158782 # number of overall hits 318system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses 319system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses 320system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses 321system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses 322system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses 323system.cpu.icache.overall_misses::total 1385 # number of overall misses |
| 324system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles 325system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles 326system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles 327system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles 328system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles 329system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles | 324system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles 325system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles 326system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles 327system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles 328system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles 329system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles |
| 330system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) 331system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses 333system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses 334system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses 335system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses 336system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 337system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 338system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 339system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 341system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses | 330system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) 331system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses 333system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses 334system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses 335system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses 336system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 337system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 338system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 339system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 341system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses |
| 342system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency 343system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency 344system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency 345system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # average overall miss latency | 342system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37151.985560 # average ReadReq miss latency 343system.cpu.icache.ReadReq_avg_miss_latency::total 37151.985560 # average ReadReq miss latency 344system.cpu.icache.demand_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency 345system.cpu.icache.demand_avg_miss_latency::total 37151.985560 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::total 37151.985560 # average overall miss latency |
| 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 360system.cpu.icache.overall_mshr_hits::cpu.inst 307 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 307 # number of overall MSHR hits 362system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses 363system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses 364system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses 365system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses 366system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses 367system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses | 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 360system.cpu.icache.overall_mshr_hits::cpu.inst 307 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 307 # number of overall MSHR hits 362system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses 363system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses 364system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses 365system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses 366system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses 367system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses |
| 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39433000 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 39433000 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39433000 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 39433000 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39433000 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 39433000 # number of overall MSHR miss cycles | 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39438000 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 39438000 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39438000 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 39438000 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39438000 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 39438000 # number of overall MSHR miss cycles |
| 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 376system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 377system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 378system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 379system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 376system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 377system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 378system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 379system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 380system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency 382system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency | 380system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36584.415584 # average ReadReq mshr miss latency 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36584.415584 # average ReadReq mshr miss latency 382system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency |
| 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 387system.cpu.dcache.replacements 2072148 # number of replacements 388system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use 389system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks. 390system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks. 391system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks. 392system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit. 393system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor --- 94 unchanged lines hidden (view full) --- 488system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16021.590757 # average WriteReq mshr miss latency 489system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16021.590757 # average WriteReq mshr miss latency 490system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency 491system.cpu.dcache.demand_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency 492system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency 493system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency 494system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 495system.cpu.l2cache.replacements 1466 # number of replacements | 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 387system.cpu.dcache.replacements 2072148 # number of replacements 388system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use 389system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks. 390system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks. 391system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks. 392system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit. 393system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor --- 94 unchanged lines hidden (view full) --- 488system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16021.590757 # average WriteReq mshr miss latency 489system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16021.590757 # average WriteReq mshr miss latency 490system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency 491system.cpu.dcache.demand_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency 492system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency 493system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency 494system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 495system.cpu.l2cache.replacements 1466 # number of replacements |
| 496system.cpu.l2cache.tagsinuse 19909.538266 # Cycle average of tags in use | 496system.cpu.l2cache.tagsinuse 19909.538394 # Cycle average of tags in use |
| 497system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks. 498system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks. 499system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks. 500system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 497system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks. 498system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks. 499system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks. 500system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 501system.cpu.l2cache.occ_blocks::writebacks 19409.012511 # Average occupied blocks per requestor 502system.cpu.l2cache.occ_blocks::cpu.inst 268.281429 # Average occupied blocks per requestor 503system.cpu.l2cache.occ_blocks::cpu.data 232.244325 # Average occupied blocks per requestor | 501system.cpu.l2cache.occ_blocks::writebacks 19409.012644 # Average occupied blocks per requestor 502system.cpu.l2cache.occ_blocks::cpu.inst 268.281425 # Average occupied blocks per requestor 503system.cpu.l2cache.occ_blocks::cpu.data 232.244324 # Average occupied blocks per requestor |
| 504system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy 505system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy 506system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy 507system.cpu.l2cache.occ_percent::total 0.607591 # Average percentage of cache occupancy 508system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits 509system.cpu.l2cache.ReadReq_hits::cpu.data 1993503 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::total 1993511 # number of ReadReq hits 511system.cpu.l2cache.Writeback_hits::writebacks 2064775 # number of Writeback hits --- 16 unchanged lines hidden (view full) --- 528system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses 529system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses 530system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses 531system.cpu.l2cache.demand_misses::cpu.data 29584 # number of demand (read+write) misses 532system.cpu.l2cache.demand_misses::total 30652 # number of demand (read+write) misses 533system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses 534system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses 535system.cpu.l2cache.overall_misses::total 30652 # number of overall misses | 504system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy 505system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy 506system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy 507system.cpu.l2cache.occ_percent::total 0.607591 # Average percentage of cache occupancy 508system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits 509system.cpu.l2cache.ReadReq_hits::cpu.data 1993503 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::total 1993511 # number of ReadReq hits 511system.cpu.l2cache.Writeback_hits::writebacks 2064775 # number of Writeback hits --- 16 unchanged lines hidden (view full) --- 528system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses 529system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses 530system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses 531system.cpu.l2cache.demand_misses::cpu.data 29584 # number of demand (read+write) misses 532system.cpu.l2cache.demand_misses::total 30652 # number of demand (read+write) misses 533system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses 534system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses 535system.cpu.l2cache.overall_misses::total 30652 # number of overall misses |
| 536system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37875000 # number of ReadReq miss cycles | 536system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37880000 # number of ReadReq miss cycles |
| 537system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles | 537system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles |
| 538system.cpu.l2cache.ReadReq_miss_latency::total 58841500 # number of ReadReq miss cycles | 538system.cpu.l2cache.ReadReq_miss_latency::total 58846500 # number of ReadReq miss cycles |
| 539system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles 540system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles | 539system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles 540system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles |
| 541system.cpu.l2cache.demand_miss_latency::cpu.inst 37875000 # number of demand (read+write) miss cycles | 541system.cpu.l2cache.demand_miss_latency::cpu.inst 37880000 # number of demand (read+write) miss cycles |
| 542system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles | 542system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles |
| 543system.cpu.l2cache.demand_miss_latency::total 1047724000 # number of demand (read+write) miss cycles 544system.cpu.l2cache.overall_miss_latency::cpu.inst 37875000 # number of overall miss cycles | 543system.cpu.l2cache.demand_miss_latency::total 1047729000 # number of demand (read+write) miss cycles 544system.cpu.l2cache.overall_miss_latency::cpu.inst 37880000 # number of overall miss cycles |
| 545system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles | 545system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles |
| 546system.cpu.l2cache.overall_miss_latency::total 1047724000 # number of overall miss cycles | 546system.cpu.l2cache.overall_miss_latency::total 1047729000 # number of overall miss cycles |
| 547system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) 548system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) 549system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) 550system.cpu.l2cache.Writeback_accesses::writebacks 2064775 # number of Writeback accesses(hits+misses) 551system.cpu.l2cache.Writeback_accesses::total 2064775 # number of Writeback accesses(hits+misses) 552system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 553system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 554system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 567system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses 568system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses 569system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses 570system.cpu.l2cache.demand_miss_rate::cpu.data 0.014249 # miss rate for demand accesses 571system.cpu.l2cache.demand_miss_rate::total 0.014756 # miss rate for demand accesses 572system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses 573system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses 574system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses | 547system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) 548system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) 549system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) 550system.cpu.l2cache.Writeback_accesses::writebacks 2064775 # number of Writeback accesses(hits+misses) 551system.cpu.l2cache.Writeback_accesses::total 2064775 # number of Writeback accesses(hits+misses) 552system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 553system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 554system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 567system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses 568system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses 569system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses 570system.cpu.l2cache.demand_miss_rate::cpu.data 0.014249 # miss rate for demand accesses 571system.cpu.l2cache.demand_miss_rate::total 0.014756 # miss rate for demand accesses 572system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses 573system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses 574system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses |
| 575system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency | 575system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35468.164794 # average ReadReq miss latency |
| 576system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency | 576system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency |
| 577system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency | 577system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency |
| 578system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency 579system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency | 578system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency 579system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency |
| 580system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency | 580system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency |
| 581system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency | 581system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency |
| 582system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency 583system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency | 582system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency 583system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency |
| 584system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency | 584system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency |
| 585system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency | 585system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency |
| 586system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.l2cache.fast_writes 0 # number of fast writes performed 593system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 601system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses 602system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses 603system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses 604system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses 605system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses 606system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses 607system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses 608system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses | 586system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.l2cache.fast_writes 0 # number of fast writes performed 593system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 601system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses 602system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses 603system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses 604system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses 605system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses 606system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses 607system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses 608system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses |
| 609system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles 610system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles 611system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles | 609system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles 610system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles 611system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles |
| 612system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles 613system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles 614system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles 615system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles | 612system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles 613system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles 614system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles 615system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles |
| 616system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles 617system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles 618system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles 619system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles 620system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles 621system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles | 616system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles 617system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles 618system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles 619system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles 620system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles 621system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles |
| 622system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses 624system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses 625system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 626system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 627system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses 628system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses 629system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses 630system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses 631system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses 632system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses 633system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses 634system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses | 622system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses 624system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses 625system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 626system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 627system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses 628system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses 629system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses 630system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses 631system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses 632system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses 633system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses 634system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses |
| 635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency 636system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency 637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency | 635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency 636system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency 637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency |
| 638system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 639system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency 641system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency | 638system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 639system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency 641system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency |
| 642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency 643system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency 644system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency 645system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency 646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency | 642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency 643system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency 644system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency 645system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency 646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency |
| 648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 649 650---------- End Simulation Statistics ---------- | 648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 649 650---------- End Simulation Statistics ---------- |