1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.068408 # Number of seconds simulated
4sim_ticks 68408131000 # Number of ticks simulated
5final_tick 68408131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.064346 # Number of seconds simulated
4sim_ticks 64346039000 # Number of ticks simulated
5final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 92617 # Simulator instruction rate (inst/s)
8host_op_rate 163083 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 40102422 # Simulator tick rate (ticks/s)
10host_mem_usage 370556 # Number of bytes of host memory used
11host_seconds 1705.84 # Real time elapsed on the host
| 7host_inst_rate 77016 # Simulator instruction rate (inst/s)
8host_op_rate 135613 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 31367260 # Simulator tick rate (ticks/s)
10host_mem_usage 410996 # Number of bytes of host memory used
11host_seconds 2051.38 # Real time elapsed on the host
|
12sim_insts 157988547 # Number of instructions simulated
13sim_ops 278192462 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
| 12sim_insts 157988547 # Number of instructions simulated
13sim_ops 278192462 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
|
15system.physmem.bytes_read::cpu.data 1892736 # Number of bytes read from this memory
16system.physmem.bytes_read::total 1961088 # Number of bytes read from this memory
| 15system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory
16system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory
|
17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
| 17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
|
19system.physmem.bytes_written::writebacks 20352 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20352 # Number of bytes written to this memory
| 19system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20416 # Number of bytes written to this memory
|
21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
| 21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
|
22system.physmem.num_reads::cpu.data 29574 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 30642 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 318 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 318 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 999179 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 27668290 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 28667469 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 999179 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 999179 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 297508 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 297508 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 297508 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 999179 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 27668290 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 28964978 # Total bandwidth to/from this memory (bytes/s)
| 22system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 319 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s)
|
37system.cpu.workload.num_syscalls 444 # Number of system calls
| 37system.cpu.workload.num_syscalls 444 # Number of system calls
|
38system.cpu.numCycles 136816263 # number of cpu cycles simulated
| 38system.cpu.numCycles 128692079 # number of cpu cycles simulated
|
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
41system.cpu.BPredUnit.lookups 36128371 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 36128371 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 1086051 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 25676514 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 25568930 # Number of BTB hits
| 41system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits
|
46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
49system.cpu.fetch.icacheStallCycles 28040484 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 196465722 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 36128371 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 25568930 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 59455138 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 8440333 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 41957570 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 27323760 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 153045 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 136778320 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.524833 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.343005 # Number of instructions fetched each cycle (Total)
| 49system.cpu.fetch.icacheStallCycles 27884150 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 193525000 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 35576702 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 25270525 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 58636506 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 7358089 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 35916291 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 27160167 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 295674 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 128658357 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.644591 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.372169 # Number of instructions fetched each cycle (Total)
|
63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
64system.cpu.fetch.rateDist::0 80075177 58.54% 58.54% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 2168654 1.59% 60.13% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 2999031 2.19% 62.32% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 4111689 3.01% 65.33% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 8029506 5.87% 71.20% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 5053851 3.69% 74.89% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 2898853 2.12% 77.01% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 1472297 1.08% 78.09% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 29969262 21.91% 100.00% # Number of instructions fetched each cycle (Total)
| 64system.cpu.fetch.rateDist::0 72765830 56.56% 56.56% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 2056683 1.60% 58.16% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 3006413 2.34% 60.49% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 4027268 3.13% 63.62% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 8003806 6.22% 69.84% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 5026752 3.91% 73.75% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 2893556 2.25% 76.00% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 1437345 1.12% 77.12% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 29440704 22.88% 100.00% # Number of instructions fetched each cycle (Total)
|
73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
76system.cpu.fetch.rateDist::total 136778320 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.264065 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.435982 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 40775641 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 32574420 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 46270758 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 9832617 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 7324884 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 341365831 # Number of instructions handled by decode
85system.cpu.rename.SquashCycles 7324884 # Number of cycles rename is squashing
86system.cpu.rename.IdleCycles 46092133 # Number of cycles rename is idle
87system.cpu.rename.BlockCycles 6411510 # Number of cycles rename is blocking
88system.cpu.rename.serializeStallCycles 9224 # count of cycles rename stalled for serializing inst
89system.cpu.rename.RunCycles 50365166 # Number of cycles rename is running
90system.cpu.rename.UnblockCycles 26575403 # Number of cycles rename is unblocking
91system.cpu.rename.RenamedInsts 337580749 # Number of instructions processed by rename
92system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full
93system.cpu.rename.IQFullEvents 5005 # Number of times rename has blocked due to IQ full
94system.cpu.rename.LSQFullEvents 24325640 # Number of times rename has blocked due to LSQ full
95system.cpu.rename.FullRegisterEvents 73870 # Number of times there has been no free registers
96system.cpu.rename.RenamedOperands 414916926 # Number of destination operands rename has renamed
97system.cpu.rename.RenameLookups 1010481124 # Number of register rename lookups that rename has made
98system.cpu.rename.int_rename_lookups 1010477953 # Number of integer rename lookups
99system.cpu.rename.fp_rename_lookups 3171 # Number of floating rename lookups
100system.cpu.rename.CommittedMaps 341010848 # Number of HB maps that are committed
101system.cpu.rename.UndoneMaps 73906078 # Number of HB maps that are undone due to squashing
102system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
103system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed
104system.cpu.rename.skidInsts 57495301 # count of insts added to the skid buffer
105system.cpu.memDep0.insertedLoads 108229908 # Number of loads inserted to the mem dependence unit.
106system.cpu.memDep0.insertedStores 37227556 # Number of stores inserted to the mem dependence unit.
107system.cpu.memDep0.conflictingLoads 46399442 # Number of conflicting loads.
108system.cpu.memDep0.conflictingStores 8017088 # Number of conflicting stores.
109system.cpu.iq.iqInstsAdded 331952532 # Number of instructions added to the IQ (excludes non-spec)
110system.cpu.iq.iqNonSpecInstsAdded 2380 # Number of non-speculative instructions added to the IQ
111system.cpu.iq.iqInstsIssued 311468511 # Number of instructions issued
112system.cpu.iq.iqSquashedInstsIssued 188619 # Number of squashed instructions issued
113system.cpu.iq.iqSquashedInstsExamined 53509766 # Number of squashed instructions iterated over during squash; mainly for profiling
114system.cpu.iq.iqSquashedOperandsExamined 93151802 # Number of squashed operands that are examined and possibly removed from graph
115system.cpu.iq.iqSquashedNonSpecRemoved 1934 # Number of squashed non-spec instructions that were removed
116system.cpu.iq.issued_per_cycle::samples 136778320 # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::mean 2.277177 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::stdev 1.722818 # Number of insts issued each cycle
| 76system.cpu.fetch.rateDist::total 128658357 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.276448 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.503783 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 39452105 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 27727798 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 46961382 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 8295915 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 6221157 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 336436945 # Number of instructions handled by decode
85system.cpu.rename.SquashCycles 6221157 # Number of cycles rename is squashing
86system.cpu.rename.IdleCycles 44164076 # Number of cycles rename is idle
87system.cpu.rename.BlockCycles 5970160 # Number of cycles rename is blocking
88system.cpu.rename.serializeStallCycles 9070 # count of cycles rename stalled for serializing inst
89system.cpu.rename.RunCycles 50268632 # Number of cycles rename is running
90system.cpu.rename.UnblockCycles 22025262 # Number of cycles rename is unblocking
91system.cpu.rename.RenamedInsts 331751360 # Number of instructions processed by rename
92system.cpu.rename.ROBFullEvents 262 # Number of times rename has blocked due to ROB full
93system.cpu.rename.IQFullEvents 6842 # Number of times rename has blocked due to IQ full
94system.cpu.rename.LSQFullEvents 20121054 # Number of times rename has blocked due to LSQ full
95system.cpu.rename.FullRegisterEvents 216 # Number of times there has been no free registers
96system.cpu.rename.RenamedOperands 334012838 # Number of destination operands rename has renamed
97system.cpu.rename.RenameLookups 880453680 # Number of register rename lookups that rename has made
98system.cpu.rename.int_rename_lookups 880451759 # Number of integer rename lookups
99system.cpu.rename.fp_rename_lookups 1921 # Number of floating rename lookups
100system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed
101system.cpu.rename.UndoneMaps 54800094 # Number of HB maps that are undone due to squashing
102system.cpu.rename.serializingInsts 485 # count of serializing insts renamed
103system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed
104system.cpu.rename.skidInsts 50437110 # count of insts added to the skid buffer
105system.cpu.memDep0.insertedLoads 104594760 # Number of loads inserted to the mem dependence unit.
106system.cpu.memDep0.insertedStores 36334761 # Number of stores inserted to the mem dependence unit.
107system.cpu.memDep0.conflictingLoads 41480583 # Number of conflicting loads.
108system.cpu.memDep0.conflictingStores 6245732 # Number of conflicting stores.
109system.cpu.iq.iqInstsAdded 323452648 # Number of instructions added to the IQ (excludes non-spec)
110system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ
111system.cpu.iq.iqInstsIssued 307818254 # Number of instructions issued
112system.cpu.iq.iqSquashedInstsIssued 198387 # Number of squashed instructions issued
113system.cpu.iq.iqSquashedInstsExamined 45033296 # Number of squashed instructions iterated over during squash; mainly for profiling
114system.cpu.iq.iqSquashedOperandsExamined 65280307 # Number of squashed operands that are examined and possibly removed from graph
115system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed
116system.cpu.iq.issued_per_cycle::samples 128658357 # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::mean 2.392524 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::stdev 1.788521 # Number of insts issued each cycle
|
119system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 119system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
120system.cpu.iq.issued_per_cycle::0 29621399 21.66% 21.66% # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::1 18208303 13.31% 34.97% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::2 26183268 19.14% 54.11% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::3 31189173 22.80% 76.91% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::4 17472478 12.77% 89.69% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::5 8789771 6.43% 96.11% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::6 3781191 2.76% 98.88% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::7 1461656 1.07% 99.95% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::8 71081 0.05% 100.00% # Number of insts issued each cycle
| 120system.cpu.iq.issued_per_cycle::0 25721748 19.99% 19.99% # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::1 18649480 14.50% 34.49% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::2 23014823 17.89% 52.38% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::3 27362657 21.27% 73.64% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::4 17010472 13.22% 86.87% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::5 9600725 7.46% 94.33% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::6 6243189 4.85% 99.18% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::7 895594 0.70% 99.88% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::8 159669 0.12% 100.00% # Number of insts issued each cycle
|
129system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
130system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 129system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
130system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
132system.cpu.iq.issued_per_cycle::total 136778320 # Number of insts issued each cycle
| 132system.cpu.iq.issued_per_cycle::total 128658357 # Number of insts issued each cycle
|
133system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 133system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
134system.cpu.iq.fu_full::IntAlu 22736 1.09% 1.09% # attempts to use FU when none available
135system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
137system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
163system.cpu.iq.fu_full::MemRead 1942986 92.77% 93.86% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemWrite 128630 6.14% 100.00% # attempts to use FU when none available
| 134system.cpu.iq.fu_full::IntAlu 35279 1.70% 1.70% # attempts to use FU when none available
135system.cpu.iq.fu_full::IntMult 0 0.00% 1.70% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntDiv 0 0.00% 1.70% # attempts to use FU when none available
137system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.70% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.70% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.70% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatMult 0 0.00% 1.70% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.70% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.70% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.70% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.70% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.70% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.70% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.70% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.70% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMult 0 0.00% 1.70% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.70% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdShift 0 0.00% 1.70% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.70% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.70% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.70% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.70% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.70% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.70% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.70% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.70% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.70% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.70% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.70% # attempts to use FU when none available
163system.cpu.iq.fu_full::MemRead 1868126 90.18% 91.88% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemWrite 168108 8.12% 100.00% # attempts to use FU when none available
|
165system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
| 165system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
167system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued
168system.cpu.iq.FU_type_0::IntAlu 177262228 56.91% 56.92% # Type of FU issued
169system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued
170system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued
171system.cpu.iq.FU_type_0::FloatAdd 143 0.00% 56.92% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.92% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.92% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.92% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.92% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.92% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.92% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.92% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.92% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.92% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.92% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.92% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.92% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.92% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.92% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.92% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.92% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.92% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.92% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued
197system.cpu.iq.FU_type_0::MemRead 99693377 32.01% 88.93% # Type of FU issued
198system.cpu.iq.FU_type_0::MemWrite 34483516 11.07% 100.00% # Type of FU issued
| 167system.cpu.iq.FU_type_0::No_OpClass 29245 0.01% 0.01% # Type of FU issued
168system.cpu.iq.FU_type_0::IntAlu 174946374 56.83% 56.84% # Type of FU issued
169system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued
170system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued
171system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.84% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.84% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.84% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.84% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.84% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.84% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.84% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.84% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.84% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.84% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued
197system.cpu.iq.FU_type_0::MemRead 99043059 32.18% 89.02% # Type of FU issued
198system.cpu.iq.FU_type_0::MemWrite 33799538 10.98% 100.00% # Type of FU issued
|
199system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
200system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 199system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
200system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
201system.cpu.iq.FU_type_0::total 311468511 # Type of FU issued
202system.cpu.iq.rate 2.276546 # Inst issue rate
203system.cpu.iq.fu_busy_cnt 2094352 # FU busy when requested
204system.cpu.iq.fu_busy_rate 0.006724 # FU busy rate (busy events/executed inst)
205system.cpu.iq.int_inst_queue_reads 761997211 # Number of integer instruction queue reads
206system.cpu.iq.int_inst_queue_writes 385495678 # Number of integer instruction queue writes
207system.cpu.iq.int_inst_queue_wakeup_accesses 308386892 # Number of integer instruction queue wakeup accesses
208system.cpu.iq.fp_inst_queue_reads 1102 # Number of floating instruction queue reads
209system.cpu.iq.fp_inst_queue_writes 1693 # Number of floating instruction queue writes
210system.cpu.iq.fp_inst_queue_wakeup_accesses 371 # Number of floating instruction queue wakeup accesses
211system.cpu.iq.int_alu_accesses 313533109 # Number of integer alu accesses
212system.cpu.iq.fp_alu_accesses 507 # Number of floating point alu accesses
213system.cpu.iew.lsq.thread0.forwLoads 52559129 # Number of loads that had data forwarded from stores
| 201system.cpu.iq.FU_type_0::total 307818254 # Type of FU issued
202system.cpu.iq.rate 2.391897 # Inst issue rate
203system.cpu.iq.fu_busy_cnt 2071513 # FU busy when requested
204system.cpu.iq.fu_busy_rate 0.006730 # FU busy rate (busy events/executed inst)
205system.cpu.iq.int_inst_queue_reads 746564211 # Number of integer instruction queue reads
206system.cpu.iq.int_inst_queue_writes 368519272 # Number of integer instruction queue writes
207system.cpu.iq.int_inst_queue_wakeup_accesses 304587112 # Number of integer instruction queue wakeup accesses
208system.cpu.iq.fp_inst_queue_reads 554 # Number of floating instruction queue reads
209system.cpu.iq.fp_inst_queue_writes 943 # Number of floating instruction queue writes
210system.cpu.iq.fp_inst_queue_wakeup_accesses 186 # Number of floating instruction queue wakeup accesses
211system.cpu.iq.int_alu_accesses 309860246 # Number of integer alu accesses
212system.cpu.iq.fp_alu_accesses 276 # Number of floating point alu accesses
213system.cpu.iew.lsq.thread0.forwLoads 52574701 # Number of loads that had data forwarded from stores
|
214system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 214system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
215system.cpu.iew.lsq.thread0.squashedLoads 17450524 # Number of loads squashed
216system.cpu.iew.lsq.thread0.ignoredResponses 94828 # Number of memory responses ignored because the instruction is squashed
217system.cpu.iew.lsq.thread0.memOrderViolation 33225 # Number of memory ordering violations
218system.cpu.iew.lsq.thread0.squashedStores 5787805 # Number of stores squashed
| 215system.cpu.iew.lsq.thread0.squashedLoads 13815376 # Number of loads squashed
216system.cpu.iew.lsq.thread0.ignoredResponses 44181 # Number of memory responses ignored because the instruction is squashed
217system.cpu.iew.lsq.thread0.memOrderViolation 33341 # Number of memory ordering violations
218system.cpu.iew.lsq.thread0.squashedStores 4895010 # Number of stores squashed
|
219system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
220system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
| 219system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
220system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
221system.cpu.iew.lsq.thread0.rescheduledLoads 3313 # Number of loads that were rescheduled
222system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked
| 221system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled
222system.cpu.iew.lsq.thread0.cacheBlocked 36659 # Number of times an access to memory failed due to the cache being blocked
|
223system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 223system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
224system.cpu.iew.iewSquashCycles 7324884 # Number of cycles IEW is squashing
225system.cpu.iew.iewBlockCycles 821379 # Number of cycles IEW is blocking
226system.cpu.iew.iewUnblockCycles 106718 # Number of cycles IEW is unblocking
227system.cpu.iew.iewDispatchedInsts 331954912 # Number of instructions dispatched to IQ
228system.cpu.iew.iewDispSquashedInsts 49233 # Number of squashed instructions skipped by dispatch
229system.cpu.iew.iewDispLoadInsts 108229908 # Number of dispatched load instructions
230system.cpu.iew.iewDispStoreInsts 37227556 # Number of dispatched store instructions
231system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions
232system.cpu.iew.iewIQFullEvents 1080 # Number of times the IQ has become full, causing a stall
233system.cpu.iew.iewLSQFullEvents 29147 # Number of times the LSQ has become full, causing a stall
234system.cpu.iew.memOrderViolationEvents 33225 # Number of memory order violations
235system.cpu.iew.predictedTakenIncorrect 614391 # Number of branches that were predicted taken incorrectly
236system.cpu.iew.predictedNotTakenIncorrect 577456 # Number of branches that were predicted not taken incorrectly
237system.cpu.iew.branchMispredicts 1191847 # Number of branch mispredicts detected at execute
238system.cpu.iew.iewExecutedInsts 309549319 # Number of executed instructions
239system.cpu.iew.iewExecLoadInsts 99164391 # Number of load instructions executed
240system.cpu.iew.iewExecSquashedInsts 1919192 # Number of squashed instructions skipped in execute
| 224system.cpu.iew.iewSquashCycles 6221157 # Number of cycles IEW is squashing
225system.cpu.iew.iewBlockCycles 782061 # Number of cycles IEW is blocking
226system.cpu.iew.iewUnblockCycles 89817 # Number of cycles IEW is unblocking
227system.cpu.iew.iewDispatchedInsts 323454406 # Number of instructions dispatched to IQ
228system.cpu.iew.iewDispSquashedInsts 362446 # Number of squashed instructions skipped by dispatch
229system.cpu.iew.iewDispLoadInsts 104594760 # Number of dispatched load instructions
230system.cpu.iew.iewDispStoreInsts 36334761 # Number of dispatched store instructions
231system.cpu.iew.iewDispNonSpecInsts 480 # Number of dispatched non-speculative instructions
232system.cpu.iew.iewIQFullEvents 611 # Number of times the IQ has become full, causing a stall
233system.cpu.iew.iewLSQFullEvents 22270 # Number of times the LSQ has become full, causing a stall
234system.cpu.iew.memOrderViolationEvents 33341 # Number of memory order violations
235system.cpu.iew.predictedTakenIncorrect 595275 # Number of branches that were predicted taken incorrectly
236system.cpu.iew.predictedNotTakenIncorrect 582931 # Number of branches that were predicted not taken incorrectly
237system.cpu.iew.branchMispredicts 1178206 # Number of branch mispredicts detected at execute
238system.cpu.iew.iewExecutedInsts 305708901 # Number of executed instructions
239system.cpu.iew.iewExecLoadInsts 98426933 # Number of load instructions executed
240system.cpu.iew.iewExecSquashedInsts 2109353 # Number of squashed instructions skipped in execute
|
241system.cpu.iew.exec_swp 0 # number of swp insts executed
242system.cpu.iew.exec_nop 0 # number of nop insts executed
| 241system.cpu.iew.exec_swp 0 # number of swp insts executed
242system.cpu.iew.exec_nop 0 # number of nop insts executed
|
243system.cpu.iew.exec_refs 133267604 # number of memory reference insts executed
244system.cpu.iew.exec_branches 31551799 # Number of branches executed
245system.cpu.iew.exec_stores 34103213 # Number of stores executed
246system.cpu.iew.exec_rate 2.262518 # Inst execution rate
247system.cpu.iew.wb_sent 308913193 # cumulative count of insts sent to commit
248system.cpu.iew.wb_count 308387263 # cumulative count of insts written-back
249system.cpu.iew.wb_producers 227149501 # num instructions producing a value
250system.cpu.iew.wb_consumers 466434365 # num instructions consuming a value
| 243system.cpu.iew.exec_refs 131805652 # number of memory reference insts executed
244system.cpu.iew.exec_branches 31122940 # Number of branches executed
245system.cpu.iew.exec_stores 33378719 # Number of stores executed
246system.cpu.iew.exec_rate 2.375507 # Inst execution rate
247system.cpu.iew.wb_sent 305078305 # cumulative count of insts sent to commit
248system.cpu.iew.wb_count 304587298 # cumulative count of insts written-back
249system.cpu.iew.wb_producers 225979119 # num instructions producing a value
250system.cpu.iew.wb_consumers 311384301 # num instructions consuming a value
|
251system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 251system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
252system.cpu.iew.wb_rate 2.254025 # insts written-back per cycle
253system.cpu.iew.wb_fanout 0.486991 # average fanout of values written-back
| 252system.cpu.iew.wb_rate 2.366791 # insts written-back per cycle
253system.cpu.iew.wb_fanout 0.725724 # average fanout of values written-back
|
254system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
255system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions
256system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions
| 254system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
255system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions
256system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions
|
257system.cpu.commit.commitSquashedInsts 53766564 # The number of squashed insts skipped by commit
| 257system.cpu.commit.commitSquashedInsts 45269554 # The number of squashed insts skipped by commit
|
258system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
| 258system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
259system.cpu.commit.branchMispredicts 1086077 # The number of times a branch was mispredicted
260system.cpu.commit.committed_per_cycle::samples 129453436 # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::mean 2.148977 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::stdev 2.662392 # Number of insts commited each cycle
| 259system.cpu.commit.branchMispredicts 1085338 # The number of times a branch was mispredicted
260system.cpu.commit.committed_per_cycle::samples 122437200 # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::mean 2.272124 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::stdev 2.827291 # Number of insts commited each cycle
|
263system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 263system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
264system.cpu.commit.committed_per_cycle::0 48953386 37.82% 37.82% # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::1 24330343 18.79% 56.61% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::2 17047293 13.17% 69.78% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::3 12542277 9.69% 79.47% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::4 3298814 2.55% 82.02% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::5 3552746 2.74% 84.76% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::6 2756547 2.13% 86.89% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::7 1133806 0.88% 87.77% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::8 15838224 12.23% 100.00% # Number of insts commited each cycle
| 264system.cpu.commit.committed_per_cycle::0 46942462 38.34% 38.34% # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::1 21185475 17.30% 55.64% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::2 15973782 13.05% 68.69% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::3 12948459 10.58% 79.27% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::4 1961875 1.60% 80.87% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::5 1887285 1.54% 82.41% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::6 1388960 1.13% 83.54% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::7 594855 0.49% 84.03% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::8 19554047 15.97% 100.00% # Number of insts commited each cycle
|
273system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
274system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 273system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
274system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
276system.cpu.commit.committed_per_cycle::total 129453436 # Number of insts commited each cycle
| 276system.cpu.commit.committed_per_cycle::total 122437200 # Number of insts commited each cycle
|
277system.cpu.commit.committedInsts 157988547 # Number of instructions committed
278system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed
279system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
280system.cpu.commit.refs 122219135 # Number of memory references committed
281system.cpu.commit.loads 90779384 # Number of loads committed
282system.cpu.commit.membars 0 # Number of memory barriers committed
283system.cpu.commit.branches 29309705 # Number of branches committed
284system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
285system.cpu.commit.int_insts 278186170 # Number of committed integer instructions.
286system.cpu.commit.function_calls 0 # Number of function calls committed.
| 277system.cpu.commit.committedInsts 157988547 # Number of instructions committed
278system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed
279system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
280system.cpu.commit.refs 122219135 # Number of memory references committed
281system.cpu.commit.loads 90779384 # Number of loads committed
282system.cpu.commit.membars 0 # Number of memory barriers committed
283system.cpu.commit.branches 29309705 # Number of branches committed
284system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
285system.cpu.commit.int_insts 278186170 # Number of committed integer instructions.
286system.cpu.commit.function_calls 0 # Number of function calls committed.
|
287system.cpu.commit.bw_lim_events 15838224 # number cycles where commit BW limit reached
| 287system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached
|
288system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 288system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
289system.cpu.rob.rob_reads 445574238 # The number of ROB reads
290system.cpu.rob.rob_writes 671251501 # The number of ROB writes
291system.cpu.timesIdled 1985 # Number of times that the entire CPU went into an idle state and unscheduled itself
292system.cpu.idleCycles 37943 # Total number of cycles that the CPU has spent unscheduled due to idling
| 289system.cpu.rob.rob_reads 426345169 # The number of ROB reads
290system.cpu.rob.rob_writes 653150724 # The number of ROB writes
291system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself
292system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling
|
293system.cpu.committedInsts 157988547 # Number of Instructions Simulated
294system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
295system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
| 293system.cpu.committedInsts 157988547 # Number of Instructions Simulated
294system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
295system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
|
296system.cpu.cpi 0.865988 # CPI: Cycles Per Instruction
297system.cpu.cpi_total 0.865988 # CPI: Total CPI of All Threads
298system.cpu.ipc 1.154750 # IPC: Instructions Per Cycle
299system.cpu.ipc_total 1.154750 # IPC: Total IPC of All Threads
300system.cpu.int_regfile_reads 705392602 # number of integer regfile reads
301system.cpu.int_regfile_writes 373276329 # number of integer regfile writes
302system.cpu.fp_regfile_reads 441 # number of floating regfile reads
303system.cpu.fp_regfile_writes 230 # number of floating regfile writes
304system.cpu.misc_regfile_reads 197984249 # number of misc regfile reads
305system.cpu.icache.replacements 87 # number of replacements
306system.cpu.icache.tagsinuse 844.199846 # Cycle average of tags in use
307system.cpu.icache.total_refs 27322358 # Total number of references to valid blocks.
| 296system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction
297system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads
298system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle
299system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads
300system.cpu.int_regfile_reads 598601369 # number of integer regfile reads
301system.cpu.int_regfile_writes 305356910 # number of integer regfile writes
302system.cpu.fp_regfile_reads 165 # number of floating regfile reads
303system.cpu.fp_regfile_writes 88 # number of floating regfile writes
304system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads
305system.cpu.icache.replacements 92 # number of replacements
306system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use
307system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks.
|
308system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks.
| 308system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks.
|
309system.cpu.icache.avg_refs 25392.526022 # Average number of references to valid blocks.
| 309system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks.
|
310system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 310system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
311system.cpu.icache.occ_blocks::cpu.inst 844.199846 # Average occupied blocks per requestor
312system.cpu.icache.occ_percent::cpu.inst 0.412207 # Average percentage of cache occupancy
313system.cpu.icache.occ_percent::total 0.412207 # Average percentage of cache occupancy
314system.cpu.icache.ReadReq_hits::cpu.inst 27322358 # number of ReadReq hits
315system.cpu.icache.ReadReq_hits::total 27322358 # number of ReadReq hits
316system.cpu.icache.demand_hits::cpu.inst 27322358 # number of demand (read+write) hits
317system.cpu.icache.demand_hits::total 27322358 # number of demand (read+write) hits
318system.cpu.icache.overall_hits::cpu.inst 27322358 # number of overall hits
319system.cpu.icache.overall_hits::total 27322358 # number of overall hits
320system.cpu.icache.ReadReq_misses::cpu.inst 1402 # number of ReadReq misses
321system.cpu.icache.ReadReq_misses::total 1402 # number of ReadReq misses
322system.cpu.icache.demand_misses::cpu.inst 1402 # number of demand (read+write) misses
323system.cpu.icache.demand_misses::total 1402 # number of demand (read+write) misses
324system.cpu.icache.overall_misses::cpu.inst 1402 # number of overall misses
325system.cpu.icache.overall_misses::total 1402 # number of overall misses
326system.cpu.icache.ReadReq_miss_latency::cpu.inst 51713500 # number of ReadReq miss cycles
327system.cpu.icache.ReadReq_miss_latency::total 51713500 # number of ReadReq miss cycles
328system.cpu.icache.demand_miss_latency::cpu.inst 51713500 # number of demand (read+write) miss cycles
329system.cpu.icache.demand_miss_latency::total 51713500 # number of demand (read+write) miss cycles
330system.cpu.icache.overall_miss_latency::cpu.inst 51713500 # number of overall miss cycles
331system.cpu.icache.overall_miss_latency::total 51713500 # number of overall miss cycles
332system.cpu.icache.ReadReq_accesses::cpu.inst 27323760 # number of ReadReq accesses(hits+misses)
333system.cpu.icache.ReadReq_accesses::total 27323760 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.demand_accesses::cpu.inst 27323760 # number of demand (read+write) accesses
335system.cpu.icache.demand_accesses::total 27323760 # number of demand (read+write) accesses
336system.cpu.icache.overall_accesses::cpu.inst 27323760 # number of overall (read+write) accesses
337system.cpu.icache.overall_accesses::total 27323760 # number of overall (read+write) accesses
| 311system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor
312system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy
313system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy
314system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits
315system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits
316system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits
317system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits
318system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits
319system.cpu.icache.overall_hits::total 27158782 # number of overall hits
320system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses
321system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses
322system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses
323system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses
324system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses
325system.cpu.icache.overall_misses::total 1385 # number of overall misses
326system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles
327system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles
328system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles
329system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles
330system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles
331system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles
332system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses)
333system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses
335system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses
336system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses
337system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses
|
338system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses
339system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
340system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses
341system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
342system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
343system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
| 338system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses
339system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
340system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses
341system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
342system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
343system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
|
344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685 # average ReadReq miss latency
345system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685 # average ReadReq miss latency
346system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency
347system.cpu.icache.demand_avg_miss_latency::total 36885.520685 # average overall miss latency
348system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency
349system.cpu.icache.overall_avg_miss_latency::total 36885.520685 # average overall miss latency
| 344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency
345system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency
346system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency
347system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency
348system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency
349system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # average overall miss latency
|
350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
354system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
355system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
356system.cpu.icache.fast_writes 0 # number of fast writes performed
357system.cpu.icache.cache_copies 0 # number of cache copies performed
| 350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
354system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
355system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
356system.cpu.icache.fast_writes 0 # number of fast writes performed
357system.cpu.icache.cache_copies 0 # number of cache copies performed
|
358system.cpu.icache.ReadReq_mshr_hits::cpu.inst 325 # number of ReadReq MSHR hits
359system.cpu.icache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits
360system.cpu.icache.demand_mshr_hits::cpu.inst 325 # number of demand (read+write) MSHR hits
361system.cpu.icache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
362system.cpu.icache.overall_mshr_hits::cpu.inst 325 # number of overall MSHR hits
363system.cpu.icache.overall_mshr_hits::total 325 # number of overall MSHR hits
364system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses
365system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses
366system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses
367system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses
368system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses
369system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses
370system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39505500 # number of ReadReq MSHR miss cycles
371system.cpu.icache.ReadReq_mshr_miss_latency::total 39505500 # number of ReadReq MSHR miss cycles
372system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39505500 # number of demand (read+write) MSHR miss cycles
373system.cpu.icache.demand_mshr_miss_latency::total 39505500 # number of demand (read+write) MSHR miss cycles
374system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39505500 # number of overall MSHR miss cycles
375system.cpu.icache.overall_mshr_miss_latency::total 39505500 # number of overall MSHR miss cycles
376system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
377system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
378system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
379system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
380system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
381system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
382system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36681.058496 # average ReadReq mshr miss latency
383system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36681.058496 # average ReadReq mshr miss latency
384system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency
385system.cpu.icache.demand_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency
386system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency
387system.cpu.icache.overall_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency
| 358system.cpu.icache.ReadReq_mshr_hits::cpu.inst 307 # number of ReadReq MSHR hits
359system.cpu.icache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits
360system.cpu.icache.demand_mshr_hits::cpu.inst 307 # number of demand (read+write) MSHR hits
361system.cpu.icache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits
362system.cpu.icache.overall_mshr_hits::cpu.inst 307 # number of overall MSHR hits
363system.cpu.icache.overall_mshr_hits::total 307 # number of overall MSHR hits
364system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses
365system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses
366system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses
367system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses
368system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses
369system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses
370system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39433000 # number of ReadReq MSHR miss cycles
371system.cpu.icache.ReadReq_mshr_miss_latency::total 39433000 # number of ReadReq MSHR miss cycles
372system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39433000 # number of demand (read+write) MSHR miss cycles
373system.cpu.icache.demand_mshr_miss_latency::total 39433000 # number of demand (read+write) MSHR miss cycles
374system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39433000 # number of overall MSHR miss cycles
375system.cpu.icache.overall_mshr_miss_latency::total 39433000 # number of overall MSHR miss cycles
376system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
377system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
378system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
379system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
380system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
381system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
382system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency
383system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency
384system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency
385system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency
386system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency
387system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency
|
388system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 388system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
389system.cpu.dcache.replacements 2072121 # number of replacements
390system.cpu.dcache.tagsinuse 4072.371520 # Cycle average of tags in use
391system.cpu.dcache.total_refs 75597840 # Total number of references to valid blocks.
392system.cpu.dcache.sampled_refs 2076217 # Sample count of references to valid blocks.
393system.cpu.dcache.avg_refs 36.411339 # Average number of references to valid blocks.
394system.cpu.dcache.warmup_cycle 22802887000 # Cycle when the warmup percentage was hit.
395system.cpu.dcache.occ_blocks::cpu.data 4072.371520 # Average occupied blocks per requestor
396system.cpu.dcache.occ_percent::cpu.data 0.994231 # Average percentage of cache occupancy
397system.cpu.dcache.occ_percent::total 0.994231 # Average percentage of cache occupancy
398system.cpu.dcache.ReadReq_hits::cpu.data 44240568 # number of ReadReq hits
399system.cpu.dcache.ReadReq_hits::total 44240568 # number of ReadReq hits
400system.cpu.dcache.WriteReq_hits::cpu.data 31357263 # number of WriteReq hits
401system.cpu.dcache.WriteReq_hits::total 31357263 # number of WriteReq hits
402system.cpu.dcache.demand_hits::cpu.data 75597831 # number of demand (read+write) hits
403system.cpu.dcache.demand_hits::total 75597831 # number of demand (read+write) hits
404system.cpu.dcache.overall_hits::cpu.data 75597831 # number of overall hits
405system.cpu.dcache.overall_hits::total 75597831 # number of overall hits
406system.cpu.dcache.ReadReq_misses::cpu.data 2315103 # number of ReadReq misses
407system.cpu.dcache.ReadReq_misses::total 2315103 # number of ReadReq misses
408system.cpu.dcache.WriteReq_misses::cpu.data 82488 # number of WriteReq misses
409system.cpu.dcache.WriteReq_misses::total 82488 # number of WriteReq misses
410system.cpu.dcache.demand_misses::cpu.data 2397591 # number of demand (read+write) misses
411system.cpu.dcache.demand_misses::total 2397591 # number of demand (read+write) misses
412system.cpu.dcache.overall_misses::cpu.data 2397591 # number of overall misses
413system.cpu.dcache.overall_misses::total 2397591 # number of overall misses
414system.cpu.dcache.ReadReq_miss_latency::cpu.data 16770812000 # number of ReadReq miss cycles
415system.cpu.dcache.ReadReq_miss_latency::total 16770812000 # number of ReadReq miss cycles
416system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571570000 # number of WriteReq miss cycles
417system.cpu.dcache.WriteReq_miss_latency::total 1571570000 # number of WriteReq miss cycles
418system.cpu.dcache.demand_miss_latency::cpu.data 18342382000 # number of demand (read+write) miss cycles
419system.cpu.dcache.demand_miss_latency::total 18342382000 # number of demand (read+write) miss cycles
420system.cpu.dcache.overall_miss_latency::cpu.data 18342382000 # number of overall miss cycles
421system.cpu.dcache.overall_miss_latency::total 18342382000 # number of overall miss cycles
422system.cpu.dcache.ReadReq_accesses::cpu.data 46555671 # number of ReadReq accesses(hits+misses)
423system.cpu.dcache.ReadReq_accesses::total 46555671 # number of ReadReq accesses(hits+misses)
| 389system.cpu.dcache.replacements 2072148 # number of replacements
390system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use
391system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks.
392system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks.
393system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks.
394system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit.
395system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor
396system.cpu.dcache.occ_percent::cpu.data 0.994148 # Average percentage of cache occupancy
397system.cpu.dcache.occ_percent::total 0.994148 # Average percentage of cache occupancy
398system.cpu.dcache.ReadReq_hits::cpu.data 43467724 # number of ReadReq hits
399system.cpu.dcache.ReadReq_hits::total 43467724 # number of ReadReq hits
400system.cpu.dcache.WriteReq_hits::cpu.data 31357249 # number of WriteReq hits
401system.cpu.dcache.WriteReq_hits::total 31357249 # number of WriteReq hits
402system.cpu.dcache.demand_hits::cpu.data 74824973 # number of demand (read+write) hits
403system.cpu.dcache.demand_hits::total 74824973 # number of demand (read+write) hits
404system.cpu.dcache.overall_hits::cpu.data 74824973 # number of overall hits
405system.cpu.dcache.overall_hits::total 74824973 # number of overall hits
406system.cpu.dcache.ReadReq_misses::cpu.data 2321557 # number of ReadReq misses
407system.cpu.dcache.ReadReq_misses::total 2321557 # number of ReadReq misses
408system.cpu.dcache.WriteReq_misses::cpu.data 82502 # number of WriteReq misses
409system.cpu.dcache.WriteReq_misses::total 82502 # number of WriteReq misses
410system.cpu.dcache.demand_misses::cpu.data 2404059 # number of demand (read+write) misses
411system.cpu.dcache.demand_misses::total 2404059 # number of demand (read+write) misses
412system.cpu.dcache.overall_misses::cpu.data 2404059 # number of overall misses
413system.cpu.dcache.overall_misses::total 2404059 # number of overall misses
414system.cpu.dcache.ReadReq_miss_latency::cpu.data 19393584000 # number of ReadReq miss cycles
415system.cpu.dcache.ReadReq_miss_latency::total 19393584000 # number of ReadReq miss cycles
416system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571938000 # number of WriteReq miss cycles
417system.cpu.dcache.WriteReq_miss_latency::total 1571938000 # number of WriteReq miss cycles
418system.cpu.dcache.demand_miss_latency::cpu.data 20965522000 # number of demand (read+write) miss cycles
419system.cpu.dcache.demand_miss_latency::total 20965522000 # number of demand (read+write) miss cycles
420system.cpu.dcache.overall_miss_latency::cpu.data 20965522000 # number of overall miss cycles
421system.cpu.dcache.overall_miss_latency::total 20965522000 # number of overall miss cycles
422system.cpu.dcache.ReadReq_accesses::cpu.data 45789281 # number of ReadReq accesses(hits+misses)
423system.cpu.dcache.ReadReq_accesses::total 45789281 # number of ReadReq accesses(hits+misses)
|
424system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
425system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
| 424system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
425system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
|
426system.cpu.dcache.demand_accesses::cpu.data 77995422 # number of demand (read+write) accesses
427system.cpu.dcache.demand_accesses::total 77995422 # number of demand (read+write) accesses
428system.cpu.dcache.overall_accesses::cpu.data 77995422 # number of overall (read+write) accesses
429system.cpu.dcache.overall_accesses::total 77995422 # number of overall (read+write) accesses
430system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049728 # miss rate for ReadReq accesses
431system.cpu.dcache.ReadReq_miss_rate::total 0.049728 # miss rate for ReadReq accesses
| 426system.cpu.dcache.demand_accesses::cpu.data 77229032 # number of demand (read+write) accesses
427system.cpu.dcache.demand_accesses::total 77229032 # number of demand (read+write) accesses
428system.cpu.dcache.overall_accesses::cpu.data 77229032 # number of overall (read+write) accesses
429system.cpu.dcache.overall_accesses::total 77229032 # number of overall (read+write) accesses
430system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050701 # miss rate for ReadReq accesses
431system.cpu.dcache.ReadReq_miss_rate::total 0.050701 # miss rate for ReadReq accesses
|
432system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses
433system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses
| 432system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses
433system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses
|
434system.cpu.dcache.demand_miss_rate::cpu.data 0.030740 # miss rate for demand accesses
435system.cpu.dcache.demand_miss_rate::total 0.030740 # miss rate for demand accesses
436system.cpu.dcache.overall_miss_rate::cpu.data 0.030740 # miss rate for overall accesses
437system.cpu.dcache.overall_miss_rate::total 0.030740 # miss rate for overall accesses
438system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7244.088924 # average ReadReq miss latency
439system.cpu.dcache.ReadReq_avg_miss_latency::total 7244.088924 # average ReadReq miss latency
440system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549 # average WriteReq miss latency
441system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549 # average WriteReq miss latency
442system.cpu.dcache.demand_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency
443system.cpu.dcache.demand_avg_miss_latency::total 7650.338194 # average overall miss latency
444system.cpu.dcache.overall_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency
445system.cpu.dcache.overall_avg_miss_latency::total 7650.338194 # average overall miss latency
| 434system.cpu.dcache.demand_miss_rate::cpu.data 0.031129 # miss rate for demand accesses
435system.cpu.dcache.demand_miss_rate::total 0.031129 # miss rate for demand accesses
436system.cpu.dcache.overall_miss_rate::cpu.data 0.031129 # miss rate for overall accesses
437system.cpu.dcache.overall_miss_rate::total 0.031129 # miss rate for overall accesses
438system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8353.697109 # average ReadReq miss latency
439system.cpu.dcache.ReadReq_avg_miss_latency::total 8353.697109 # average ReadReq miss latency
440system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19053.332040 # average WriteReq miss latency
441system.cpu.dcache.WriteReq_avg_miss_latency::total 19053.332040 # average WriteReq miss latency
442system.cpu.dcache.demand_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency
443system.cpu.dcache.demand_avg_miss_latency::total 8720.884970 # average overall miss latency
444system.cpu.dcache.overall_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency
445system.cpu.dcache.overall_avg_miss_latency::total 8720.884970 # average overall miss latency
|
446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
452system.cpu.dcache.fast_writes 0 # number of fast writes performed
453system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
452system.cpu.dcache.fast_writes 0 # number of fast writes performed
453system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
454system.cpu.dcache.writebacks::writebacks 2065063 # number of writebacks
455system.cpu.dcache.writebacks::total 2065063 # number of writebacks
456system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320901 # number of ReadReq MSHR hits
457system.cpu.dcache.ReadReq_mshr_hits::total 320901 # number of ReadReq MSHR hits
458system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits
459system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits
460system.cpu.dcache.demand_mshr_hits::cpu.data 321370 # number of demand (read+write) MSHR hits
461system.cpu.dcache.demand_mshr_hits::total 321370 # number of demand (read+write) MSHR hits
462system.cpu.dcache.overall_mshr_hits::cpu.data 321370 # number of overall MSHR hits
463system.cpu.dcache.overall_mshr_hits::total 321370 # number of overall MSHR hits
464system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994202 # number of ReadReq MSHR misses
465system.cpu.dcache.ReadReq_mshr_misses::total 1994202 # number of ReadReq MSHR misses
466system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82019 # number of WriteReq MSHR misses
467system.cpu.dcache.WriteReq_mshr_misses::total 82019 # number of WriteReq MSHR misses
468system.cpu.dcache.demand_mshr_misses::cpu.data 2076221 # number of demand (read+write) MSHR misses
469system.cpu.dcache.demand_mshr_misses::total 2076221 # number of demand (read+write) MSHR misses
470system.cpu.dcache.overall_mshr_misses::cpu.data 2076221 # number of overall MSHR misses
471system.cpu.dcache.overall_mshr_misses::total 2076221 # number of overall MSHR misses
472system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6183631000 # number of ReadReq MSHR miss cycles
473system.cpu.dcache.ReadReq_mshr_miss_latency::total 6183631000 # number of ReadReq MSHR miss cycles
474system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313937000 # number of WriteReq MSHR miss cycles
475system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313937000 # number of WriteReq MSHR miss cycles
476system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497568000 # number of demand (read+write) MSHR miss cycles
477system.cpu.dcache.demand_mshr_miss_latency::total 7497568000 # number of demand (read+write) MSHR miss cycles
478system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497568000 # number of overall MSHR miss cycles
479system.cpu.dcache.overall_mshr_miss_latency::total 7497568000 # number of overall MSHR miss cycles
480system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042835 # mshr miss rate for ReadReq accesses
481system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042835 # mshr miss rate for ReadReq accesses
482system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses
483system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses
484system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for demand accesses
485system.cpu.dcache.demand_mshr_miss_rate::total 0.026620 # mshr miss rate for demand accesses
486system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for overall accesses
487system.cpu.dcache.overall_mshr_miss_rate::total 0.026620 # mshr miss rate for overall accesses
488system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.804733 # average ReadReq mshr miss latency
489system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.804733 # average ReadReq mshr miss latency
490system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021 # average WriteReq mshr miss latency
491system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021 # average WriteReq mshr miss latency
492system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency
493system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency
494system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency
495system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency
| 454system.cpu.dcache.writebacks::writebacks 2064775 # number of writebacks
455system.cpu.dcache.writebacks::total 2064775 # number of writebacks
456system.cpu.dcache.ReadReq_mshr_hits::cpu.data 327358 # number of ReadReq MSHR hits
457system.cpu.dcache.ReadReq_mshr_hits::total 327358 # number of ReadReq MSHR hits
458system.cpu.dcache.WriteReq_mshr_hits::cpu.data 453 # number of WriteReq MSHR hits
459system.cpu.dcache.WriteReq_mshr_hits::total 453 # number of WriteReq MSHR hits
460system.cpu.dcache.demand_mshr_hits::cpu.data 327811 # number of demand (read+write) MSHR hits
461system.cpu.dcache.demand_mshr_hits::total 327811 # number of demand (read+write) MSHR hits
462system.cpu.dcache.overall_mshr_hits::cpu.data 327811 # number of overall MSHR hits
463system.cpu.dcache.overall_mshr_hits::total 327811 # number of overall MSHR hits
464system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994199 # number of ReadReq MSHR misses
465system.cpu.dcache.ReadReq_mshr_misses::total 1994199 # number of ReadReq MSHR misses
466system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82049 # number of WriteReq MSHR misses
467system.cpu.dcache.WriteReq_mshr_misses::total 82049 # number of WriteReq MSHR misses
468system.cpu.dcache.demand_mshr_misses::cpu.data 2076248 # number of demand (read+write) MSHR misses
469system.cpu.dcache.demand_mshr_misses::total 2076248 # number of demand (read+write) MSHR misses
470system.cpu.dcache.overall_mshr_misses::cpu.data 2076248 # number of overall MSHR misses
471system.cpu.dcache.overall_mshr_misses::total 2076248 # number of overall MSHR misses
472system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8452133500 # number of ReadReq MSHR miss cycles
473system.cpu.dcache.ReadReq_mshr_miss_latency::total 8452133500 # number of ReadReq MSHR miss cycles
474system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1314555500 # number of WriteReq MSHR miss cycles
475system.cpu.dcache.WriteReq_mshr_miss_latency::total 1314555500 # number of WriteReq MSHR miss cycles
476system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9766689000 # number of demand (read+write) MSHR miss cycles
477system.cpu.dcache.demand_mshr_miss_latency::total 9766689000 # number of demand (read+write) MSHR miss cycles
478system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9766689000 # number of overall MSHR miss cycles
479system.cpu.dcache.overall_mshr_miss_latency::total 9766689000 # number of overall MSHR miss cycles
480system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043552 # mshr miss rate for ReadReq accesses
481system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043552 # mshr miss rate for ReadReq accesses
482system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses
483system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses
484system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026884 # mshr miss rate for demand accesses
485system.cpu.dcache.demand_mshr_miss_rate::total 0.026884 # mshr miss rate for demand accesses
486system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026884 # mshr miss rate for overall accesses
487system.cpu.dcache.overall_mshr_miss_rate::total 0.026884 # mshr miss rate for overall accesses
488system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4238.360114 # average ReadReq mshr miss latency
489system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4238.360114 # average ReadReq mshr miss latency
490system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16021.590757 # average WriteReq mshr miss latency
491system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16021.590757 # average WriteReq mshr miss latency
492system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency
493system.cpu.dcache.demand_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency
494system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency
495system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency
|
496system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 496system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
497system.cpu.l2cache.replacements 1458 # number of replacements
498system.cpu.l2cache.tagsinuse 20067.979072 # Cycle average of tags in use
499system.cpu.l2cache.total_refs 4027415 # Total number of references to valid blocks.
500system.cpu.l2cache.sampled_refs 30622 # Sample count of references to valid blocks.
501system.cpu.l2cache.avg_refs 131.520312 # Average number of references to valid blocks.
| 497system.cpu.l2cache.replacements 1466 # number of replacements
498system.cpu.l2cache.tagsinuse 19909.538266 # Cycle average of tags in use
499system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks.
500system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks.
501system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks.
|
502system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 502system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
503system.cpu.l2cache.occ_blocks::writebacks 19572.608886 # Average occupied blocks per requestor
504system.cpu.l2cache.occ_blocks::cpu.inst 263.032470 # Average occupied blocks per requestor
505system.cpu.l2cache.occ_blocks::cpu.data 232.337716 # Average occupied blocks per requestor
506system.cpu.l2cache.occ_percent::writebacks 0.597309 # Average percentage of cache occupancy
507system.cpu.l2cache.occ_percent::cpu.inst 0.008027 # Average percentage of cache occupancy
508system.cpu.l2cache.occ_percent::cpu.data 0.007090 # Average percentage of cache occupancy
509system.cpu.l2cache.occ_percent::total 0.612426 # Average percentage of cache occupancy
| 503system.cpu.l2cache.occ_blocks::writebacks 19409.012511 # Average occupied blocks per requestor
504system.cpu.l2cache.occ_blocks::cpu.inst 268.281429 # Average occupied blocks per requestor
505system.cpu.l2cache.occ_blocks::cpu.data 232.244325 # Average occupied blocks per requestor
506system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy
507system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy
508system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy
509system.cpu.l2cache.occ_percent::total 0.607591 # Average percentage of cache occupancy
|
510system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits
| 510system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits
|
511system.cpu.l2cache.ReadReq_hits::cpu.data 1993505 # number of ReadReq hits
512system.cpu.l2cache.ReadReq_hits::total 1993513 # number of ReadReq hits
513system.cpu.l2cache.Writeback_hits::writebacks 2065063 # number of Writeback hits
514system.cpu.l2cache.Writeback_hits::total 2065063 # number of Writeback hits
515system.cpu.l2cache.ReadExReq_hits::cpu.data 53141 # number of ReadExReq hits
516system.cpu.l2cache.ReadExReq_hits::total 53141 # number of ReadExReq hits
| 511system.cpu.l2cache.ReadReq_hits::cpu.data 1993503 # number of ReadReq hits
512system.cpu.l2cache.ReadReq_hits::total 1993511 # number of ReadReq hits
513system.cpu.l2cache.Writeback_hits::writebacks 2064775 # number of Writeback hits
514system.cpu.l2cache.Writeback_hits::total 2064775 # number of Writeback hits
515system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
516system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
517system.cpu.l2cache.ReadExReq_hits::cpu.data 53159 # number of ReadExReq hits
518system.cpu.l2cache.ReadExReq_hits::total 53159 # number of ReadExReq hits
|
517system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits
| 519system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits
|
518system.cpu.l2cache.demand_hits::cpu.data 2046646 # number of demand (read+write) hits
519system.cpu.l2cache.demand_hits::total 2046654 # number of demand (read+write) hits
| 520system.cpu.l2cache.demand_hits::cpu.data 2046662 # number of demand (read+write) hits
521system.cpu.l2cache.demand_hits::total 2046670 # number of demand (read+write) hits
|
520system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits
| 522system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits
|
521system.cpu.l2cache.overall_hits::cpu.data 2046646 # number of overall hits
522system.cpu.l2cache.overall_hits::total 2046654 # number of overall hits
| 523system.cpu.l2cache.overall_hits::cpu.data 2046662 # number of overall hits
524system.cpu.l2cache.overall_hits::total 2046670 # number of overall hits
|
523system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses
| 525system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses
|
524system.cpu.l2cache.ReadReq_misses::cpu.data 582 # number of ReadReq misses
525system.cpu.l2cache.ReadReq_misses::total 1650 # number of ReadReq misses
| 526system.cpu.l2cache.ReadReq_misses::cpu.data 588 # number of ReadReq misses
527system.cpu.l2cache.ReadReq_misses::total 1656 # number of ReadReq misses
|
526system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
527system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
| 528system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
529system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
|
528system.cpu.l2cache.ReadExReq_misses::cpu.data 28992 # number of ReadExReq misses
529system.cpu.l2cache.ReadExReq_misses::total 28992 # number of ReadExReq misses
| 530system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses
531system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses
|
530system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses
| 532system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses
|
531system.cpu.l2cache.demand_misses::cpu.data 29574 # number of demand (read+write) misses
532system.cpu.l2cache.demand_misses::total 30642 # number of demand (read+write) misses
| 533system.cpu.l2cache.demand_misses::cpu.data 29584 # number of demand (read+write) misses
534system.cpu.l2cache.demand_misses::total 30652 # number of demand (read+write) misses
|
533system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses
| 535system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses
|
534system.cpu.l2cache.overall_misses::cpu.data 29574 # number of overall misses
535system.cpu.l2cache.overall_misses::total 30642 # number of overall misses
536system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37986000 # number of ReadReq miss cycles
537system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20700500 # number of ReadReq miss cycles
538system.cpu.l2cache.ReadReq_miss_latency::total 58686500 # number of ReadReq miss cycles
539system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989313000 # number of ReadExReq miss cycles
540system.cpu.l2cache.ReadExReq_miss_latency::total 989313000 # number of ReadExReq miss cycles
541system.cpu.l2cache.demand_miss_latency::cpu.inst 37986000 # number of demand (read+write) miss cycles
542system.cpu.l2cache.demand_miss_latency::cpu.data 1010013500 # number of demand (read+write) miss cycles
543system.cpu.l2cache.demand_miss_latency::total 1047999500 # number of demand (read+write) miss cycles
544system.cpu.l2cache.overall_miss_latency::cpu.inst 37986000 # number of overall miss cycles
545system.cpu.l2cache.overall_miss_latency::cpu.data 1010013500 # number of overall miss cycles
546system.cpu.l2cache.overall_miss_latency::total 1047999500 # number of overall miss cycles
| 536system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses
537system.cpu.l2cache.overall_misses::total 30652 # number of overall misses
538system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37875000 # number of ReadReq miss cycles
539system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles
540system.cpu.l2cache.ReadReq_miss_latency::total 58841500 # number of ReadReq miss cycles
541system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles
542system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles
543system.cpu.l2cache.demand_miss_latency::cpu.inst 37875000 # number of demand (read+write) miss cycles
544system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles
545system.cpu.l2cache.demand_miss_latency::total 1047724000 # number of demand (read+write) miss cycles
546system.cpu.l2cache.overall_miss_latency::cpu.inst 37875000 # number of overall miss cycles
547system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles
548system.cpu.l2cache.overall_miss_latency::total 1047724000 # number of overall miss cycles
|
547system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses)
| 549system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses)
|
548system.cpu.l2cache.ReadReq_accesses::cpu.data 1994087 # number of ReadReq accesses(hits+misses)
549system.cpu.l2cache.ReadReq_accesses::total 1995163 # number of ReadReq accesses(hits+misses)
550system.cpu.l2cache.Writeback_accesses::writebacks 2065063 # number of Writeback accesses(hits+misses)
551system.cpu.l2cache.Writeback_accesses::total 2065063 # number of Writeback accesses(hits+misses)
552system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
553system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
554system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses)
555system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses)
| 550system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses)
551system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses)
552system.cpu.l2cache.Writeback_accesses::writebacks 2064775 # number of Writeback accesses(hits+misses)
553system.cpu.l2cache.Writeback_accesses::total 2064775 # number of Writeback accesses(hits+misses)
554system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
555system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
556system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses)
557system.cpu.l2cache.ReadExReq_accesses::total 82155 # number of ReadExReq accesses(hits+misses)
|
556system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
| 558system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
|
557system.cpu.l2cache.demand_accesses::cpu.data 2076220 # number of demand (read+write) accesses
558system.cpu.l2cache.demand_accesses::total 2077296 # number of demand (read+write) accesses
| 559system.cpu.l2cache.demand_accesses::cpu.data 2076246 # number of demand (read+write) accesses
560system.cpu.l2cache.demand_accesses::total 2077322 # number of demand (read+write) accesses
|
559system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
| 561system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
|
560system.cpu.l2cache.overall_accesses::cpu.data 2076220 # number of overall (read+write) accesses
561system.cpu.l2cache.overall_accesses::total 2077296 # number of overall (read+write) accesses
| 562system.cpu.l2cache.overall_accesses::cpu.data 2076246 # number of overall (read+write) accesses
563system.cpu.l2cache.overall_accesses::total 2077322 # number of overall (read+write) accesses
|
562system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses
| 564system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses
|
563system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000292 # miss rate for ReadReq accesses
564system.cpu.l2cache.ReadReq_miss_rate::total 0.000827 # miss rate for ReadReq accesses
565system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
566system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
567system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses
568system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses
| 565system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses
566system.cpu.l2cache.ReadReq_miss_rate::total 0.000830 # miss rate for ReadReq accesses
567system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
568system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
569system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses
570system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses
|
569system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses
| 571system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses
|
570system.cpu.l2cache.demand_miss_rate::cpu.data 0.014244 # miss rate for demand accesses
571system.cpu.l2cache.demand_miss_rate::total 0.014751 # miss rate for demand accesses
| 572system.cpu.l2cache.demand_miss_rate::cpu.data 0.014249 # miss rate for demand accesses
573system.cpu.l2cache.demand_miss_rate::total 0.014756 # miss rate for demand accesses
|
572system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses
| 574system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses
|
573system.cpu.l2cache.overall_miss_rate::cpu.data 0.014244 # miss rate for overall accesses
574system.cpu.l2cache.overall_miss_rate::total 0.014751 # miss rate for overall accesses
575system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35567.415730 # average ReadReq miss latency
576system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35567.869416 # average ReadReq miss latency
577system.cpu.l2cache.ReadReq_avg_miss_latency::total 35567.575758 # average ReadReq miss latency
578system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.654801 # average ReadExReq miss latency
579system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.654801 # average ReadExReq miss latency
580system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency
581system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency
582system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566 # average overall miss latency
583system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency
584system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency
585system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566 # average overall miss latency
| 575system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses
576system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses
577system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency
578system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency
579system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency
580system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency
581system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency
582system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency
583system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency
584system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency
585system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency
586system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency
587system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency
|
586system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
587system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
588system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
589system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
590system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
591system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
592system.cpu.l2cache.fast_writes 0 # number of fast writes performed
593system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| 588system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
589system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
591system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
592system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
593system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
594system.cpu.l2cache.fast_writes 0 # number of fast writes performed
595system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
594system.cpu.l2cache.writebacks::writebacks 318 # number of writebacks
595system.cpu.l2cache.writebacks::total 318 # number of writebacks
| 596system.cpu.l2cache.writebacks::writebacks 319 # number of writebacks
597system.cpu.l2cache.writebacks::total 319 # number of writebacks
|
596system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses
| 598system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses
|
597system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 582 # number of ReadReq MSHR misses
598system.cpu.l2cache.ReadReq_mshr_misses::total 1650 # number of ReadReq MSHR misses
| 599system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses
600system.cpu.l2cache.ReadReq_mshr_misses::total 1656 # number of ReadReq MSHR misses
|
599system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
600system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
| 601system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
602system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
|
601system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses
602system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses
| 603system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses
604system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses
|
603system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses
| 605system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses
|
604system.cpu.l2cache.demand_mshr_misses::cpu.data 29574 # number of demand (read+write) MSHR misses
605system.cpu.l2cache.demand_mshr_misses::total 30642 # number of demand (read+write) MSHR misses
| 606system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses
607system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses
|
606system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
| 608system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
|
607system.cpu.l2cache.overall_mshr_misses::cpu.data 29574 # number of overall MSHR misses
608system.cpu.l2cache.overall_mshr_misses::total 30642 # number of overall MSHR misses
609system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34610000 # number of ReadReq MSHR miss cycles
610system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18859500 # number of ReadReq MSHR miss cycles
611system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53469500 # number of ReadReq MSHR miss cycles
| 609system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses
610system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses
611system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles
612system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles
613system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles
|
612system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
613system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
| 614system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
615system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
|
614system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899045000 # number of ReadExReq MSHR miss cycles
615system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899045000 # number of ReadExReq MSHR miss cycles
616system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34610000 # number of demand (read+write) MSHR miss cycles
617system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 917904500 # number of demand (read+write) MSHR miss cycles
618system.cpu.l2cache.demand_mshr_miss_latency::total 952514500 # number of demand (read+write) MSHR miss cycles
619system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34610000 # number of overall MSHR miss cycles
620system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 917904500 # number of overall MSHR miss cycles
621system.cpu.l2cache.overall_mshr_miss_latency::total 952514500 # number of overall MSHR miss cycles
| 616system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles
617system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles
618system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles
619system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles
620system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles
621system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles
622system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles
623system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles
|
622system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses
| 624system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses
|
623system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses
624system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000827 # mshr miss rate for ReadReq accesses
625system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
626system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
627system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses
628system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses
| 625system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses
626system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses
627system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
628system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
629system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses
630system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses
|
629system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses
| 631system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses
|
630system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for demand accesses
631system.cpu.l2cache.demand_mshr_miss_rate::total 0.014751 # mshr miss rate for demand accesses
| 632system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses
633system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses
|
632system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses
| 634system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses
|
633system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for overall accesses
634system.cpu.l2cache.overall_mshr_miss_rate::total 0.014751 # mshr miss rate for overall accesses
635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041 # average ReadReq mshr miss latency
636system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175 # average ReadReq mshr miss latency
637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576 # average ReadReq mshr miss latency
| 635system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses
636system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses
637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency
638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency
639system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency
|
638system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
639system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
| 640system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
641system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
|
640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236 # average ReadExReq mshr miss latency
641system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236 # average ReadExReq mshr miss latency
642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency
643system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency
644system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency
645system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency
646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency
647system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency
| 642system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency
643system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency
644system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency
645system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency
646system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency
647system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency
648system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency
649system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency
|
648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
649
650---------- End Simulation Statistics ----------
| 650system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
651
652---------- End Simulation Statistics ----------
|