Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.070047 # Number of seconds simulated
4sim_ticks 70046988500 # Number of ticks simulated
5final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.067367 # Number of seconds simulated
4sim_ticks 67367177000 # Number of ticks simulated
5final_tick 67367177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 120922 # Simulator instruction rate (inst/s)
8host_op_rate 212925 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 53613076 # Simulator tick rate (ticks/s)
10host_mem_usage 355612 # Number of bytes of host memory used
11host_seconds 1306.53 # Real time elapsed on the host

7host_inst_rate 124120 # Simulator instruction rate (inst/s)
8host_op_rate 218555 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 52925417 # Simulator tick rate (ticks/s)
10host_mem_usage 355732 # Number of bytes of host memory used
11host_seconds 1272.87 # Real time elapsed on the host

12sim_insts 157988582 # Number of instructions simulated
13sim_ops 278192519 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read 3895936 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 892288 # Number of bytes written to this memory
17system.physmem.num_reads 60874 # Number of read requests responded to by this memory
18system.physmem.num_writes 13942 # Number of write requests responded to by this memory

14system.physmem.bytes_read 3905024 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 69056 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 895552 # Number of bytes written to this memory
17system.physmem.num_reads 61016 # Number of read requests responded to by this memory
18system.physmem.num_writes 13993 # Number of write requests responded to by this memory

19system.physmem.num_other 0 # Number of other requests responded to by this memory

20system.physmem.bw_read 55618894 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 931032 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 12738421 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 68357314 # Total bandwidth to/from this memory (bytes/s)

20system.physmem.bw_read 57966270 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1025069 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 13293595 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 71259866 # Total bandwidth to/from this memory (bytes/s)

24system.cpu.workload.num_syscalls 444 # Number of system calls

25system.cpu.numCycles 140093978 # number of cpu cycles simulated

25system.cpu.numCycles 134734355 # number of cpu cycles simulated

26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

28system.cpu.BPredUnit.lookups 37937752 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 37937752 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 1331995 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 33815417 # Number of BTB lookups
32system.cpu.BPredUnit.BTBHits 33320649 # Number of BTB hits

28system.cpu.BPredUnit.lookups 36117705 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 36117705 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 1086223 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 25647744 # Number of BTB lookups
32system.cpu.BPredUnit.BTBHits 25539011 # Number of BTB hits

33system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
34system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
35system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.

36system.cpu.fetch.icacheStallCycles 29024363 # Number of cycles fetch is stalled on an Icache miss
37system.cpu.fetch.Insts 203514307 # Number of instructions fetch has processed
38system.cpu.fetch.Branches 37937752 # Number of branches that fetch encountered
39system.cpu.fetch.predictedBranches 33320649 # Number of branches that fetch has predicted taken
40system.cpu.fetch.Cycles 63466806 # Number of cycles fetch has run and was not squashing or blocked
41system.cpu.fetch.SquashCycles 10233892 # Number of cycles fetch has spent squashing
42system.cpu.fetch.BlockedCycles 37945043 # Number of cycles fetch has spent blocked
43system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
44system.cpu.fetch.PendingTrapStallCycles 68 # Number of stall cycles due to pending traps
45system.cpu.fetch.CacheLines 28213885 # Number of cache lines fetched
46system.cpu.fetch.IcacheSquashes 212642 # Number of outstanding Icache misses that were squashed
47system.cpu.fetch.rateDist::samples 139306492 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::mean 2.579216 # Number of instructions fetched each cycle (Total)
49system.cpu.fetch.rateDist::stdev 3.290579 # Number of instructions fetched each cycle (Total)

36system.cpu.fetch.icacheStallCycles 27986454 # Number of cycles fetch is stalled on an Icache miss
37system.cpu.fetch.Insts 196428178 # Number of instructions fetch has processed
38system.cpu.fetch.Branches 36117705 # Number of branches that fetch encountered
39system.cpu.fetch.predictedBranches 25539011 # Number of branches that fetch has predicted taken
40system.cpu.fetch.Cycles 59419496 # Number of cycles fetch has run and was not squashing or blocked
41system.cpu.fetch.SquashCycles 8404854 # Number of cycles fetch has spent squashing
42system.cpu.fetch.BlockedCycles 39237097 # Number of cycles fetch has spent blocked
43system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
44system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps
45system.cpu.fetch.CacheLines 27269445 # Number of cache lines fetched
46system.cpu.fetch.IcacheSquashes 142050 # Number of outstanding Icache misses that were squashed
47system.cpu.fetch.rateDist::samples 133931620 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::mean 2.578005 # Number of instructions fetched each cycle (Total)
49system.cpu.fetch.rateDist::stdev 3.358197 # Number of instructions fetched each cycle (Total)

50system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

51system.cpu.fetch.rateDist::0 78286088 56.20% 56.20% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::1 3759512 2.70% 58.90% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::2 2809249 2.02% 60.91% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::3 4511465 3.24% 64.15% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::4 7046412 5.06% 69.21% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::5 5071327 3.64% 72.85% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::6 7671850 5.51% 78.36% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::7 4389018 3.15% 81.51% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::8 25761571 18.49% 100.00% # Number of instructions fetched each cycle (Total)

51system.cpu.fetch.rateDist::0 77253594 57.68% 57.68% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::1 2167416 1.62% 59.30% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::2 2996676 2.24% 61.54% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::3 4105343 3.07% 64.60% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::4 8023701 5.99% 70.59% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::5 5042154 3.76% 74.36% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::6 2892095 2.16% 76.52% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::7 1463696 1.09% 77.61% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::8 29986945 22.39% 100.00% # Number of instructions fetched each cycle (Total)

60system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

63system.cpu.fetch.rateDist::total 139306492 # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.branchRate 0.270802 # Number of branch fetches per cycle
65system.cpu.fetch.rate 1.452698 # Number of inst fetches per cycle
66system.cpu.decode.IdleCycles 41961886 # Number of cycles decode is idle
67system.cpu.decode.BlockedCycles 28163540 # Number of cycles decode is blocked
68system.cpu.decode.RunCycles 52299140 # Number of cycles decode is running
69system.cpu.decode.UnblockCycles 8011732 # Number of cycles decode is unblocking
70system.cpu.decode.SquashCycles 8870194 # Number of cycles decode is squashing
71system.cpu.decode.DecodedInsts 354926885 # Number of instructions handled by decode
72system.cpu.rename.SquashCycles 8870194 # Number of cycles rename is squashing
73system.cpu.rename.IdleCycles 48488899 # Number of cycles rename is idle
74system.cpu.rename.BlockCycles 4721769 # Number of cycles rename is blocking
75system.cpu.rename.serializeStallCycles 9082 # count of cycles rename stalled for serializing inst
76system.cpu.rename.RunCycles 53110553 # Number of cycles rename is running
77system.cpu.rename.UnblockCycles 24105995 # Number of cycles rename is unblocking
78system.cpu.rename.RenamedInsts 349921643 # Number of instructions processed by rename
79system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full
80system.cpu.rename.IQFullEvents 105361 # Number of times rename has blocked due to IQ full
81system.cpu.rename.LSQFullEvents 20166032 # Number of times rename has blocked due to LSQ full
82system.cpu.rename.RenamedOperands 314159745 # Number of destination operands rename has renamed
83system.cpu.rename.RenameLookups 860584858 # Number of register rename lookups that rename has made
84system.cpu.rename.int_rename_lookups 860581891 # Number of integer rename lookups
85system.cpu.rename.fp_rename_lookups 2967 # Number of floating rename lookups

63system.cpu.fetch.rateDist::total 133931620 # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.branchRate 0.268066 # Number of branch fetches per cycle
65system.cpu.fetch.rate 1.457892 # Number of inst fetches per cycle
66system.cpu.decode.IdleCycles 40456608 # Number of cycles decode is idle
67system.cpu.decode.BlockedCycles 30121503 # Number of cycles decode is blocked
68system.cpu.decode.RunCycles 46487725 # Number of cycles decode is running
69system.cpu.decode.UnblockCycles 9577404 # Number of cycles decode is unblocking
70system.cpu.decode.SquashCycles 7288380 # Number of cycles decode is squashing
71system.cpu.decode.DecodedInsts 341192383 # Number of instructions handled by decode
72system.cpu.rename.SquashCycles 7288380 # Number of cycles rename is squashing
73system.cpu.rename.IdleCycles 45850157 # Number of cycles rename is idle
74system.cpu.rename.BlockCycles 5075267 # Number of cycles rename is blocking
75system.cpu.rename.serializeStallCycles 9166 # count of cycles rename stalled for serializing inst
76system.cpu.rename.RunCycles 50344983 # Number of cycles rename is running
77system.cpu.rename.UnblockCycles 25363667 # Number of cycles rename is unblocking
78system.cpu.rename.RenamedInsts 337332641 # Number of instructions processed by rename
79system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full
80system.cpu.rename.IQFullEvents 24553 # Number of times rename has blocked due to IQ full
81system.cpu.rename.LSQFullEvents 23217040 # Number of times rename has blocked due to LSQ full
82system.cpu.rename.RenamedOperands 301814702 # Number of destination operands rename has renamed
83system.cpu.rename.RenameLookups 829797290 # Number of register rename lookups that rename has made
84system.cpu.rename.int_rename_lookups 829794179 # Number of integer rename lookups
85system.cpu.rename.fp_rename_lookups 3111 # Number of floating rename lookups

86system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed

87system.cpu.rename.UndoneMaps 65815553 # Number of HB maps that are undone due to squashing
88system.cpu.rename.serializingInsts 479 # count of serializing insts renamed
89system.cpu.rename.tempSerializingInsts 473 # count of temporary serializing insts renamed
90system.cpu.rename.skidInsts 57293063 # count of insts added to the skid buffer
91system.cpu.memDep0.insertedLoads 112603571 # Number of loads inserted to the mem dependence unit.
92system.cpu.memDep0.insertedStores 37556545 # Number of stores inserted to the mem dependence unit.
93system.cpu.memDep0.conflictingLoads 47800126 # Number of conflicting loads.
94system.cpu.memDep0.conflictingStores 8208845 # Number of conflicting stores.
95system.cpu.iq.iqInstsAdded 343290045 # Number of instructions added to the IQ (excludes non-spec)
96system.cpu.iq.iqNonSpecInstsAdded 2336 # Number of non-speculative instructions added to the IQ
97system.cpu.iq.iqInstsIssued 316029105 # Number of instructions issued
98system.cpu.iq.iqSquashedInstsIssued 76885 # Number of squashed instructions issued
99system.cpu.iq.iqSquashedInstsExamined 64917017 # Number of squashed instructions iterated over during squash; mainly for profiling
100system.cpu.iq.iqSquashedOperandsExamined 92716043 # Number of squashed operands that are examined and possibly removed from graph
101system.cpu.iq.iqSquashedNonSpecRemoved 1890 # Number of squashed non-spec instructions that were removed
102system.cpu.iq.issued_per_cycle::samples 139306492 # Number of insts issued each cycle
103system.cpu.iq.issued_per_cycle::mean 2.268588 # Number of insts issued each cycle
104system.cpu.iq.issued_per_cycle::stdev 1.744230 # Number of insts issued each cycle

87system.cpu.rename.UndoneMaps 53470510 # Number of HB maps that are undone due to squashing
88system.cpu.rename.serializingInsts 483 # count of serializing insts renamed
89system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed
90system.cpu.rename.skidInsts 56181617 # count of insts added to the skid buffer
91system.cpu.memDep0.insertedLoads 108142373 # Number of loads inserted to the mem dependence unit.
92system.cpu.memDep0.insertedStores 37171875 # Number of stores inserted to the mem dependence unit.
93system.cpu.memDep0.conflictingLoads 46300098 # Number of conflicting loads.
94system.cpu.memDep0.conflictingStores 7898843 # Number of conflicting stores.
95system.cpu.iq.iqInstsAdded 331653497 # Number of instructions added to the IQ (excludes non-spec)
96system.cpu.iq.iqNonSpecInstsAdded 2738 # Number of non-speculative instructions added to the IQ
97system.cpu.iq.iqInstsIssued 311383007 # Number of instructions issued
98system.cpu.iq.iqSquashedInstsIssued 186497 # Number of squashed instructions issued
99system.cpu.iq.iqSquashedInstsExamined 53202508 # Number of squashed instructions iterated over during squash; mainly for profiling
100system.cpu.iq.iqSquashedOperandsExamined 70962751 # Number of squashed operands that are examined and possibly removed from graph
101system.cpu.iq.iqSquashedNonSpecRemoved 2292 # Number of squashed non-spec instructions that were removed
102system.cpu.iq.issued_per_cycle::samples 133931620 # Number of insts issued each cycle
103system.cpu.iq.issued_per_cycle::mean 2.324940 # Number of insts issued each cycle
104system.cpu.iq.issued_per_cycle::stdev 1.724540 # Number of insts issued each cycle

105system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

106system.cpu.iq.issued_per_cycle::0 32068137 23.02% 23.02% # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::1 17712067 12.71% 35.73% # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::2 24423194 17.53% 53.27% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::3 32289069 23.18% 76.44% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::4 18335734 13.16% 89.61% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::5 9491103 6.81% 96.42% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::6 3154604 2.26% 98.68% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::7 1783304 1.28% 99.96% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::8 49280 0.04% 100.00% # Number of insts issued each cycle

106system.cpu.iq.issued_per_cycle::0 27909124 20.84% 20.84% # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::1 17260254 12.89% 33.73% # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::2 25571257 19.09% 52.82% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::3 31151034 23.26% 76.08% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::4 17658757 13.18% 89.26% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::5 9043417 6.75% 96.01% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::6 3762327 2.81% 98.82% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::7 1502538 1.12% 99.95% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::8 72912 0.05% 100.00% # Number of insts issued each cycle

115system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

118system.cpu.iq.issued_per_cycle::total 139306492 # Number of insts issued each cycle

118system.cpu.iq.issued_per_cycle::total 133931620 # Number of insts issued each cycle

119system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

120system.cpu.iq.fu_full::IntAlu 25569 1.30% 1.30% # attempts to use FU when none available
121system.cpu.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available
122system.cpu.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available
123system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available
124system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available
129system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available
130system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available
149system.cpu.iq.fu_full::MemRead 1859415 94.86% 96.17% # attempts to use FU when none available
150system.cpu.iq.fu_full::MemWrite 75095 3.83% 100.00% # attempts to use FU when none available

120system.cpu.iq.fu_full::IntAlu 23628 1.12% 1.12% # attempts to use FU when none available
121system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available
122system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available
123system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available
124system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
129system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available
130system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
149system.cpu.iq.fu_full::MemRead 1962682 92.75% 93.87% # attempts to use FU when none available
150system.cpu.iq.fu_full::MemWrite 129707 6.13% 100.00% # attempts to use FU when none available

151system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
152system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

153system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
154system.cpu.iq.FU_type_0::IntAlu 180131547 57.00% 57.00% # Type of FU issued
155system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.00% # Type of FU issued
156system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.00% # Type of FU issued
157system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 57.00% # Type of FU issued
158system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.00% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.00% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.00% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.00% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.00% # Type of FU issued
163system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.00% # Type of FU issued
164system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.00% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.00% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.00% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.00% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.00% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.00% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.00% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.00% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.00% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.00% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.00% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.00% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.00% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.00% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.00% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.00% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.00% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.00% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.00% # Type of FU issued
183system.cpu.iq.FU_type_0::MemRead 101432595 32.10% 89.10% # Type of FU issued
184system.cpu.iq.FU_type_0::MemWrite 34448103 10.90% 100.00% # Type of FU issued

153system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued
154system.cpu.iq.FU_type_0::IntAlu 177172854 56.90% 56.91% # Type of FU issued
155system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued
156system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued
157system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 56.91% # Type of FU issued
158system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued
163system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued
164system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued
183system.cpu.iq.FU_type_0::MemRead 99705652 32.02% 88.93% # Type of FU issued
184system.cpu.iq.FU_type_0::MemWrite 34472981 11.07% 100.00% # Type of FU issued

185system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
186system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

187system.cpu.iq.FU_type_0::total 316029105 # Type of FU issued
188system.cpu.iq.rate 2.255836 # Inst issue rate
189system.cpu.iq.fu_busy_cnt 1960079 # FU busy when requested
190system.cpu.iq.fu_busy_rate 0.006202 # FU busy rate (busy events/executed inst)
191system.cpu.iq.int_inst_queue_reads 773400844 # Number of integer instruction queue reads
192system.cpu.iq.int_inst_queue_writes 408240794 # Number of integer instruction queue writes
193system.cpu.iq.int_inst_queue_wakeup_accesses 312293905 # Number of integer instruction queue wakeup accesses
194system.cpu.iq.fp_inst_queue_reads 822 # Number of floating instruction queue reads
195system.cpu.iq.fp_inst_queue_writes 1922 # Number of floating instruction queue writes
196system.cpu.iq.fp_inst_queue_wakeup_accesses 316 # Number of floating instruction queue wakeup accesses
197system.cpu.iq.int_alu_accesses 317972066 # Number of integer alu accesses
198system.cpu.iq.fp_alu_accesses 407 # Number of floating point alu accesses
199system.cpu.iew.lsq.thread0.forwLoads 52311971 # Number of loads that had data forwarded from stores

187system.cpu.iq.FU_type_0::total 311383007 # Type of FU issued
188system.cpu.iq.rate 2.311088 # Inst issue rate
189system.cpu.iq.fu_busy_cnt 2116017 # FU busy when requested
190system.cpu.iq.fu_busy_rate 0.006796 # FU busy rate (busy events/executed inst)
191system.cpu.iq.int_inst_queue_reads 758999086 # Number of integer instruction queue reads
192system.cpu.iq.int_inst_queue_writes 384888890 # Number of integer instruction queue writes
193system.cpu.iq.int_inst_queue_wakeup_accesses 308243683 # Number of integer instruction queue wakeup accesses
194system.cpu.iq.fp_inst_queue_reads 1062 # Number of floating instruction queue reads
195system.cpu.iq.fp_inst_queue_writes 1674 # Number of floating instruction queue writes
196system.cpu.iq.fp_inst_queue_wakeup_accesses 367 # Number of floating instruction queue wakeup accesses
197system.cpu.iq.int_alu_accesses 313467157 # Number of integer alu accesses
198system.cpu.iq.fp_alu_accesses 496 # Number of floating point alu accesses
199system.cpu.iew.lsq.thread0.forwLoads 52573681 # Number of loads that had data forwarded from stores

200system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

201system.cpu.iew.lsq.thread0.squashedLoads 21824183 # Number of loads squashed
202system.cpu.iew.lsq.thread0.ignoredResponses 143830 # Number of memory responses ignored because the instruction is squashed
203system.cpu.iew.lsq.thread0.memOrderViolation 34021 # Number of memory ordering violations
204system.cpu.iew.lsq.thread0.squashedStores 6116794 # Number of stores squashed

201system.cpu.iew.lsq.thread0.squashedLoads 17362985 # Number of loads squashed
202system.cpu.iew.lsq.thread0.ignoredResponses 99732 # Number of memory responses ignored because the instruction is squashed
203system.cpu.iew.lsq.thread0.memOrderViolation 32451 # Number of memory ordering violations
204system.cpu.iew.lsq.thread0.squashedStores 5732124 # Number of stores squashed

205system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
206system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

207system.cpu.iew.lsq.thread0.rescheduledLoads 3244 # Number of loads that were rescheduled
208system.cpu.iew.lsq.thread0.cacheBlocked 3822 # Number of times an access to memory failed due to the cache being blocked

207system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled
208system.cpu.iew.lsq.thread0.cacheBlocked 3854 # Number of times an access to memory failed due to the cache being blocked

209system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

210system.cpu.iew.iewSquashCycles 8870194 # Number of cycles IEW is squashing
211system.cpu.iew.iewBlockCycles 981730 # Number of cycles IEW is blocking
212system.cpu.iew.iewUnblockCycles 88786 # Number of cycles IEW is unblocking
213system.cpu.iew.iewDispatchedInsts 343292381 # Number of instructions dispatched to IQ
214system.cpu.iew.iewDispSquashedInsts 39929 # Number of squashed instructions skipped by dispatch
215system.cpu.iew.iewDispLoadInsts 112603571 # Number of dispatched load instructions
216system.cpu.iew.iewDispStoreInsts 37556545 # Number of dispatched store instructions
217system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions
218system.cpu.iew.iewIQFullEvents 1316 # Number of times the IQ has become full, causing a stall
219system.cpu.iew.iewLSQFullEvents 42406 # Number of times the LSQ has become full, causing a stall
220system.cpu.iew.memOrderViolationEvents 34021 # Number of memory order violations
221system.cpu.iew.predictedTakenIncorrect 1234482 # Number of branches that were predicted taken incorrectly
222system.cpu.iew.predictedNotTakenIncorrect 211725 # Number of branches that were predicted not taken incorrectly
223system.cpu.iew.branchMispredicts 1446207 # Number of branch mispredicts detected at execute
224system.cpu.iew.iewExecutedInsts 313835720 # Number of executed instructions
225system.cpu.iew.iewExecLoadInsts 100810143 # Number of load instructions executed
226system.cpu.iew.iewExecSquashedInsts 2193385 # Number of squashed instructions skipped in execute

210system.cpu.iew.iewSquashCycles 7288380 # Number of cycles IEW is squashing
211system.cpu.iew.iewBlockCycles 913145 # Number of cycles IEW is blocking
212system.cpu.iew.iewUnblockCycles 89980 # Number of cycles IEW is unblocking
213system.cpu.iew.iewDispatchedInsts 331656235 # Number of instructions dispatched to IQ
214system.cpu.iew.iewDispSquashedInsts 45880 # Number of squashed instructions skipped by dispatch
215system.cpu.iew.iewDispLoadInsts 108142373 # Number of dispatched load instructions
216system.cpu.iew.iewDispStoreInsts 37171875 # Number of dispatched store instructions
217system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions
218system.cpu.iew.iewIQFullEvents 1173 # Number of times the IQ has become full, causing a stall
219system.cpu.iew.iewLSQFullEvents 43472 # Number of times the LSQ has become full, causing a stall
220system.cpu.iew.memOrderViolationEvents 32451 # Number of memory order violations
221system.cpu.iew.predictedTakenIncorrect 613492 # Number of branches that were predicted taken incorrectly
222system.cpu.iew.predictedNotTakenIncorrect 579011 # Number of branches that were predicted not taken incorrectly
223system.cpu.iew.branchMispredicts 1192503 # Number of branch mispredicts detected at execute
224system.cpu.iew.iewExecutedInsts 309419383 # Number of executed instructions
225system.cpu.iew.iewExecLoadInsts 99171010 # Number of load instructions executed
226system.cpu.iew.iewExecSquashedInsts 1963624 # Number of squashed instructions skipped in execute

227system.cpu.iew.exec_swp 0 # number of swp insts executed
228system.cpu.iew.exec_nop 0 # number of nop insts executed

229system.cpu.iew.exec_refs 134854161 # number of memory reference insts executed
230system.cpu.iew.exec_branches 31726163 # Number of branches executed
231system.cpu.iew.exec_stores 34044018 # Number of stores executed
232system.cpu.iew.exec_rate 2.240180 # Inst execution rate
233system.cpu.iew.wb_sent 313006075 # cumulative count of insts sent to commit
234system.cpu.iew.wb_count 312294221 # cumulative count of insts written-back
235system.cpu.iew.wb_producers 231754622 # num instructions producing a value
236system.cpu.iew.wb_consumers 317218208 # num instructions consuming a value

229system.cpu.iew.exec_refs 133254790 # number of memory reference insts executed
230system.cpu.iew.exec_branches 31526578 # Number of branches executed
231system.cpu.iew.exec_stores 34083780 # Number of stores executed
232system.cpu.iew.exec_rate 2.296514 # Inst execution rate
233system.cpu.iew.wb_sent 308790761 # cumulative count of insts sent to commit
234system.cpu.iew.wb_count 308244050 # cumulative count of insts written-back
235system.cpu.iew.wb_producers 227493444 # num instructions producing a value
236system.cpu.iew.wb_consumers 314310835 # num instructions consuming a value

237system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

238system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle
239system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back

238system.cpu.iew.wb_rate 2.287791 # insts written-back per cycle
239system.cpu.iew.wb_fanout 0.723785 # average fanout of values written-back

240system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
241system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
242system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions

243system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit

243system.cpu.commit.commitSquashedInsts 53467881 # The number of squashed insts skipped by commit

244system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards

245system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted
246system.cpu.commit.committed_per_cycle::samples 130436298 # Number of insts commited each cycle
247system.cpu.commit.committed_per_cycle::mean 2.132785 # Number of insts commited each cycle
248system.cpu.commit.committed_per_cycle::stdev 2.651894 # Number of insts commited each cycle

245system.cpu.commit.branchMispredicts 1086244 # The number of times a branch was mispredicted
246system.cpu.commit.committed_per_cycle::samples 126643240 # Number of insts commited each cycle
247system.cpu.commit.committed_per_cycle::mean 2.196663 # Number of insts commited each cycle
248system.cpu.commit.committed_per_cycle::stdev 2.674492 # Number of insts commited each cycle

249system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

250system.cpu.commit.committed_per_cycle::0 49351461 37.84% 37.84% # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::1 24978168 19.15% 56.99% # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::2 17073618 13.09% 70.08% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::3 12436945 9.53% 79.61% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::4 3526211 2.70% 82.31% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::5 3453253 2.65% 84.96% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::6 2711146 2.08% 87.04% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::7 1125673 0.86% 87.90% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::8 15779823 12.10% 100.00% # Number of insts commited each cycle

250system.cpu.commit.committed_per_cycle::0 46336828 36.59% 36.59% # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::1 24193827 19.10% 55.69% # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::2 16853923 13.31% 69.00% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::3 12623187 9.97% 78.97% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::4 3354078 2.65% 81.62% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::5 3557907 2.81% 84.43% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::6 2707686 2.14% 86.56% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::7 1157110 0.91% 87.48% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::8 15858694 12.52% 100.00% # Number of insts commited each cycle

259system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

262system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle

262system.cpu.commit.committed_per_cycle::total 126643240 # Number of insts commited each cycle

263system.cpu.commit.committedInsts 157988582 # Number of instructions committed
264system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
265system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
266system.cpu.commit.refs 122219139 # Number of memory references committed
267system.cpu.commit.loads 90779388 # Number of loads committed
268system.cpu.commit.membars 0 # Number of memory barriers committed
269system.cpu.commit.branches 29309710 # Number of branches committed
270system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
271system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
272system.cpu.commit.function_calls 0 # Number of function calls committed.

273system.cpu.commit.bw_lim_events 15779823 # number cycles where commit BW limit reached

273system.cpu.commit.bw_lim_events 15858694 # number cycles where commit BW limit reached

274system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

275system.cpu.rob.rob_reads 457952368 # The number of ROB reads
276system.cpu.rob.rob_writes 695479183 # The number of ROB writes
277system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself
278system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling

275system.cpu.rob.rob_reads 442444946 # The number of ROB reads
276system.cpu.rob.rob_writes 670617818 # The number of ROB writes
277system.cpu.timesIdled 23939 # Number of times that the entire CPU went into an idle state and unscheduled itself
278system.cpu.idleCycles 802735 # Total number of cycles that the CPU has spent unscheduled due to idling

279system.cpu.committedInsts 157988582 # Number of Instructions Simulated
280system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
281system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated

282system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction
283system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads
284system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle
285system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads
286system.cpu.int_regfile_reads 554395898 # number of integer regfile reads
287system.cpu.int_regfile_writes 279799467 # number of integer regfile writes
288system.cpu.fp_regfile_reads 352 # number of floating regfile reads
289system.cpu.fp_regfile_writes 262 # number of floating regfile writes
290system.cpu.misc_regfile_reads 200946158 # number of misc regfile reads
291system.cpu.icache.replacements 64 # number of replacements
292system.cpu.icache.tagsinuse 822.534021 # Cycle average of tags in use
293system.cpu.icache.total_refs 28212585 # Total number of references to valid blocks.
294system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks.
295system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks.

282system.cpu.cpi 0.852811 # CPI: Cycles Per Instruction
283system.cpu.cpi_total 0.852811 # CPI: Total CPI of All Threads
284system.cpu.ipc 1.172593 # IPC: Instructions Per Cycle
285system.cpu.ipc_total 1.172593 # IPC: Total IPC of All Threads
286system.cpu.int_regfile_reads 549500021 # number of integer regfile reads
287system.cpu.int_regfile_writes 275642637 # number of integer regfile writes
288system.cpu.fp_regfile_reads 429 # number of floating regfile reads
289system.cpu.fp_regfile_writes 242 # number of floating regfile writes
290system.cpu.misc_regfile_reads 197910962 # number of misc regfile reads
291system.cpu.icache.replacements 103 # number of replacements
292system.cpu.icache.tagsinuse 848.450455 # Cycle average of tags in use
293system.cpu.icache.total_refs 27268036 # Total number of references to valid blocks.
294system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks.
295system.cpu.icache.avg_refs 24947.882891 # Average number of references to valid blocks.

296system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

297system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor
298system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy
299system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy
300system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits
301system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits
302system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits
303system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits
304system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits
305system.cpu.icache.overall_hits::total 28212585 # number of overall hits
306system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses
307system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses
308system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses
309system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses
310system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses
311system.cpu.icache.overall_misses::total 1300 # number of overall misses
312system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles
313system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles
314system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles
315system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles
316system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles
317system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles
318system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses)
319system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses
321system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses
322system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses
323system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses
324system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses
325system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses
326system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses
327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency
328system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency
329system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency

297system.cpu.icache.occ_blocks::cpu.inst 848.450455 # Average occupied blocks per requestor
298system.cpu.icache.occ_percent::cpu.inst 0.414282 # Average percentage of cache occupancy
299system.cpu.icache.occ_percent::total 0.414282 # Average percentage of cache occupancy
300system.cpu.icache.ReadReq_hits::cpu.inst 27268036 # number of ReadReq hits
301system.cpu.icache.ReadReq_hits::total 27268036 # number of ReadReq hits
302system.cpu.icache.demand_hits::cpu.inst 27268036 # number of demand (read+write) hits
303system.cpu.icache.demand_hits::total 27268036 # number of demand (read+write) hits
304system.cpu.icache.overall_hits::cpu.inst 27268036 # number of overall hits
305system.cpu.icache.overall_hits::total 27268036 # number of overall hits
306system.cpu.icache.ReadReq_misses::cpu.inst 1409 # number of ReadReq misses
307system.cpu.icache.ReadReq_misses::total 1409 # number of ReadReq misses
308system.cpu.icache.demand_misses::cpu.inst 1409 # number of demand (read+write) misses
309system.cpu.icache.demand_misses::total 1409 # number of demand (read+write) misses
310system.cpu.icache.overall_misses::cpu.inst 1409 # number of overall misses
311system.cpu.icache.overall_misses::total 1409 # number of overall misses
312system.cpu.icache.ReadReq_miss_latency::cpu.inst 50108000 # number of ReadReq miss cycles
313system.cpu.icache.ReadReq_miss_latency::total 50108000 # number of ReadReq miss cycles
314system.cpu.icache.demand_miss_latency::cpu.inst 50108000 # number of demand (read+write) miss cycles
315system.cpu.icache.demand_miss_latency::total 50108000 # number of demand (read+write) miss cycles
316system.cpu.icache.overall_miss_latency::cpu.inst 50108000 # number of overall miss cycles
317system.cpu.icache.overall_miss_latency::total 50108000 # number of overall miss cycles
318system.cpu.icache.ReadReq_accesses::cpu.inst 27269445 # number of ReadReq accesses(hits+misses)
319system.cpu.icache.ReadReq_accesses::total 27269445 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.demand_accesses::cpu.inst 27269445 # number of demand (read+write) accesses
321system.cpu.icache.demand_accesses::total 27269445 # number of demand (read+write) accesses
322system.cpu.icache.overall_accesses::cpu.inst 27269445 # number of overall (read+write) accesses
323system.cpu.icache.overall_accesses::total 27269445 # number of overall (read+write) accesses
324system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
325system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
326system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35562.810504 # average ReadReq miss latency
328system.cpu.icache.demand_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency
329system.cpu.icache.overall_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency

330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
334system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
335system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
336system.cpu.icache.fast_writes 0 # number of fast writes performed
337system.cpu.icache.cache_copies 0 # number of cache copies performed

338system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits
339system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits
340system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits
341system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
342system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits
343system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits
344system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses
345system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
346system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses
347system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses
348system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses
349system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses
350system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles
351system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles
352system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles
353system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles
354system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles
355system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles
356system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses
357system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses
358system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for overall accesses
359system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317 # average ReadReq mshr miss latency
360system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency
361system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency

338system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits
339system.cpu.icache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits
340system.cpu.icache.demand_mshr_hits::cpu.inst 315 # number of demand (read+write) MSHR hits
341system.cpu.icache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits
342system.cpu.icache.overall_mshr_hits::cpu.inst 315 # number of overall MSHR hits
343system.cpu.icache.overall_mshr_hits::total 315 # number of overall MSHR hits
344system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1094 # number of ReadReq MSHR misses
345system.cpu.icache.ReadReq_mshr_misses::total 1094 # number of ReadReq MSHR misses
346system.cpu.icache.demand_mshr_misses::cpu.inst 1094 # number of demand (read+write) MSHR misses
347system.cpu.icache.demand_mshr_misses::total 1094 # number of demand (read+write) MSHR misses
348system.cpu.icache.overall_mshr_misses::cpu.inst 1094 # number of overall MSHR misses
349system.cpu.icache.overall_mshr_misses::total 1094 # number of overall MSHR misses
350system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38230000 # number of ReadReq MSHR miss cycles
351system.cpu.icache.ReadReq_mshr_miss_latency::total 38230000 # number of ReadReq MSHR miss cycles
352system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38230000 # number of demand (read+write) MSHR miss cycles
353system.cpu.icache.demand_mshr_miss_latency::total 38230000 # number of demand (read+write) MSHR miss cycles
354system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38230000 # number of overall MSHR miss cycles
355system.cpu.icache.overall_mshr_miss_latency::total 38230000 # number of overall MSHR miss cycles
356system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
357system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
358system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
359system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34945.155393 # average ReadReq mshr miss latency
360system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency
361system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency

362system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

363system.cpu.dcache.replacements 2072906 # number of replacements
364system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use
365system.cpu.dcache.total_refs 77489413 # Total number of references to valid blocks.
366system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks.
367system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks.
368system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit.
369system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor
370system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy
371system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy
372system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits
373system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits
374system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits
375system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits
376system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits
377system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits
378system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits
379system.cpu.dcache.overall_hits::total 77489404 # number of overall hits
380system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses
381system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses
382system.cpu.dcache.WriteReq_misses::cpu.data 86000 # number of WriteReq misses
383system.cpu.dcache.WriteReq_misses::total 86000 # number of WriteReq misses
384system.cpu.dcache.demand_misses::cpu.data 2375012 # number of demand (read+write) misses
385system.cpu.dcache.demand_misses::total 2375012 # number of demand (read+write) misses
386system.cpu.dcache.overall_misses::cpu.data 2375012 # number of overall misses
387system.cpu.dcache.overall_misses::total 2375012 # number of overall misses
388system.cpu.dcache.ReadReq_miss_latency::cpu.data 13766771000 # number of ReadReq miss cycles
389system.cpu.dcache.ReadReq_miss_latency::total 13766771000 # number of ReadReq miss cycles
390system.cpu.dcache.WriteReq_miss_latency::cpu.data 1501245288 # number of WriteReq miss cycles
391system.cpu.dcache.WriteReq_miss_latency::total 1501245288 # number of WriteReq miss cycles
392system.cpu.dcache.demand_miss_latency::cpu.data 15268016288 # number of demand (read+write) miss cycles
393system.cpu.dcache.demand_miss_latency::total 15268016288 # number of demand (read+write) miss cycles
394system.cpu.dcache.overall_miss_latency::cpu.data 15268016288 # number of overall miss cycles
395system.cpu.dcache.overall_miss_latency::total 15268016288 # number of overall miss cycles
396system.cpu.dcache.ReadReq_accesses::cpu.data 48424665 # number of ReadReq accesses(hits+misses)
397system.cpu.dcache.ReadReq_accesses::total 48424665 # number of ReadReq accesses(hits+misses)

363system.cpu.dcache.replacements 2072116 # number of replacements
364system.cpu.dcache.tagsinuse 4072.716490 # Cycle average of tags in use
365system.cpu.dcache.total_refs 75611002 # Total number of references to valid blocks.
366system.cpu.dcache.sampled_refs 2076212 # Sample count of references to valid blocks.
367system.cpu.dcache.avg_refs 36.417766 # Average number of references to valid blocks.
368system.cpu.dcache.warmup_cycle 22583642000 # Cycle when the warmup percentage was hit.
369system.cpu.dcache.occ_blocks::cpu.data 4072.716490 # Average occupied blocks per requestor
370system.cpu.dcache.occ_percent::cpu.data 0.994316 # Average percentage of cache occupancy
371system.cpu.dcache.occ_percent::total 0.994316 # Average percentage of cache occupancy
372system.cpu.dcache.ReadReq_hits::cpu.data 44257159 # number of ReadReq hits
373system.cpu.dcache.ReadReq_hits::total 44257159 # number of ReadReq hits
374system.cpu.dcache.WriteReq_hits::cpu.data 31353834 # number of WriteReq hits
375system.cpu.dcache.WriteReq_hits::total 31353834 # number of WriteReq hits
376system.cpu.dcache.demand_hits::cpu.data 75610993 # number of demand (read+write) hits
377system.cpu.dcache.demand_hits::total 75610993 # number of demand (read+write) hits
378system.cpu.dcache.overall_hits::cpu.data 75610993 # number of overall hits
379system.cpu.dcache.overall_hits::total 75610993 # number of overall hits
380system.cpu.dcache.ReadReq_misses::cpu.data 2289224 # number of ReadReq misses
381system.cpu.dcache.ReadReq_misses::total 2289224 # number of ReadReq misses
382system.cpu.dcache.WriteReq_misses::cpu.data 85917 # number of WriteReq misses
383system.cpu.dcache.WriteReq_misses::total 85917 # number of WriteReq misses
384system.cpu.dcache.demand_misses::cpu.data 2375141 # number of demand (read+write) misses
385system.cpu.dcache.demand_misses::total 2375141 # number of demand (read+write) misses
386system.cpu.dcache.overall_misses::cpu.data 2375141 # number of overall misses
387system.cpu.dcache.overall_misses::total 2375141 # number of overall misses
388system.cpu.dcache.ReadReq_miss_latency::cpu.data 13801326000 # number of ReadReq miss cycles
389system.cpu.dcache.ReadReq_miss_latency::total 13801326000 # number of ReadReq miss cycles
390system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502330294 # number of WriteReq miss cycles
391system.cpu.dcache.WriteReq_miss_latency::total 1502330294 # number of WriteReq miss cycles
392system.cpu.dcache.demand_miss_latency::cpu.data 15303656294 # number of demand (read+write) miss cycles
393system.cpu.dcache.demand_miss_latency::total 15303656294 # number of demand (read+write) miss cycles
394system.cpu.dcache.overall_miss_latency::cpu.data 15303656294 # number of overall miss cycles
395system.cpu.dcache.overall_miss_latency::total 15303656294 # number of overall miss cycles
396system.cpu.dcache.ReadReq_accesses::cpu.data 46546383 # number of ReadReq accesses(hits+misses)
397system.cpu.dcache.ReadReq_accesses::total 46546383 # number of ReadReq accesses(hits+misses)

398system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
399system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)

400system.cpu.dcache.demand_accesses::cpu.data 79864416 # number of demand (read+write) accesses
401system.cpu.dcache.demand_accesses::total 79864416 # number of demand (read+write) accesses
402system.cpu.dcache.overall_accesses::cpu.data 79864416 # number of overall (read+write) accesses
403system.cpu.dcache.overall_accesses::total 79864416 # number of overall (read+write) accesses
404system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047270 # miss rate for ReadReq accesses
405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002735 # miss rate for WriteReq accesses
406system.cpu.dcache.demand_miss_rate::cpu.data 0.029738 # miss rate for demand accesses
407system.cpu.dcache.overall_miss_rate::cpu.data 0.029738 # miss rate for overall accesses
408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6014.285203 # average ReadReq miss latency
409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558 # average WriteReq miss latency
410system.cpu.dcache.demand_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency
411system.cpu.dcache.overall_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency

400system.cpu.dcache.demand_accesses::cpu.data 77986134 # number of demand (read+write) accesses
401system.cpu.dcache.demand_accesses::total 77986134 # number of demand (read+write) accesses
402system.cpu.dcache.overall_accesses::cpu.data 77986134 # number of overall (read+write) accesses
403system.cpu.dcache.overall_accesses::total 77986134 # number of overall (read+write) accesses
404system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049182 # miss rate for ReadReq accesses
405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002733 # miss rate for WriteReq accesses
406system.cpu.dcache.demand_miss_rate::cpu.data 0.030456 # miss rate for demand accesses
407system.cpu.dcache.overall_miss_rate::cpu.data 0.030456 # miss rate for overall accesses
408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6028.822867 # average ReadReq miss latency
409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17485.832769 # average WriteReq miss latency
410system.cpu.dcache.demand_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency
411system.cpu.dcache.overall_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency

412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
416system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
417system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
418system.cpu.dcache.fast_writes 0 # number of fast writes performed
419system.cpu.dcache.cache_copies 0 # number of cache copies performed

420system.cpu.dcache.writebacks::writebacks 1880780 # number of writebacks
421system.cpu.dcache.writebacks::total 1880780 # number of writebacks
422system.cpu.dcache.ReadReq_mshr_hits::cpu.data 294089 # number of ReadReq MSHR hits
423system.cpu.dcache.ReadReq_mshr_hits::total 294089 # number of ReadReq MSHR hits
424system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3918 # number of WriteReq MSHR hits
425system.cpu.dcache.WriteReq_mshr_hits::total 3918 # number of WriteReq MSHR hits
426system.cpu.dcache.demand_mshr_hits::cpu.data 298007 # number of demand (read+write) MSHR hits
427system.cpu.dcache.demand_mshr_hits::total 298007 # number of demand (read+write) MSHR hits
428system.cpu.dcache.overall_mshr_hits::cpu.data 298007 # number of overall MSHR hits
429system.cpu.dcache.overall_mshr_hits::total 298007 # number of overall MSHR hits
430system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994923 # number of ReadReq MSHR misses
431system.cpu.dcache.ReadReq_mshr_misses::total 1994923 # number of ReadReq MSHR misses
432system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses
433system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses
434system.cpu.dcache.demand_mshr_misses::cpu.data 2077005 # number of demand (read+write) MSHR misses
435system.cpu.dcache.demand_mshr_misses::total 2077005 # number of demand (read+write) MSHR misses
436system.cpu.dcache.overall_mshr_misses::cpu.data 2077005 # number of overall MSHR misses
437system.cpu.dcache.overall_mshr_misses::total 2077005 # number of overall MSHR misses
438system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5565133500 # number of ReadReq MSHR miss cycles
439system.cpu.dcache.ReadReq_mshr_miss_latency::total 5565133500 # number of ReadReq MSHR miss cycles
440system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1157645788 # number of WriteReq MSHR miss cycles
441system.cpu.dcache.WriteReq_mshr_miss_latency::total 1157645788 # number of WriteReq MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6722779288 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.demand_mshr_miss_latency::total 6722779288 # number of demand (read+write) MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6722779288 # number of overall MSHR miss cycles
445system.cpu.dcache.overall_mshr_miss_latency::total 6722779288 # number of overall MSHR miss cycles
446system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041196 # mshr miss rate for ReadReq accesses

420system.cpu.dcache.writebacks::writebacks 1879081 # number of writebacks
421system.cpu.dcache.writebacks::total 1879081 # number of writebacks
422system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295092 # number of ReadReq MSHR hits
423system.cpu.dcache.ReadReq_mshr_hits::total 295092 # number of ReadReq MSHR hits
424system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3834 # number of WriteReq MSHR hits
425system.cpu.dcache.WriteReq_mshr_hits::total 3834 # number of WriteReq MSHR hits
426system.cpu.dcache.demand_mshr_hits::cpu.data 298926 # number of demand (read+write) MSHR hits
427system.cpu.dcache.demand_mshr_hits::total 298926 # number of demand (read+write) MSHR hits
428system.cpu.dcache.overall_mshr_hits::cpu.data 298926 # number of overall MSHR hits
429system.cpu.dcache.overall_mshr_hits::total 298926 # number of overall MSHR hits
430system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994132 # number of ReadReq MSHR misses
431system.cpu.dcache.ReadReq_mshr_misses::total 1994132 # number of ReadReq MSHR misses
432system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82083 # number of WriteReq MSHR misses
433system.cpu.dcache.WriteReq_mshr_misses::total 82083 # number of WriteReq MSHR misses
434system.cpu.dcache.demand_mshr_misses::cpu.data 2076215 # number of demand (read+write) MSHR misses
435system.cpu.dcache.demand_mshr_misses::total 2076215 # number of demand (read+write) MSHR misses
436system.cpu.dcache.overall_mshr_misses::cpu.data 2076215 # number of overall MSHR misses
437system.cpu.dcache.overall_mshr_misses::total 2076215 # number of overall MSHR misses
438system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5588966000 # number of ReadReq MSHR miss cycles
439system.cpu.dcache.ReadReq_mshr_miss_latency::total 5588966000 # number of ReadReq MSHR miss cycles
440system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158785294 # number of WriteReq MSHR miss cycles
441system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158785294 # number of WriteReq MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6747751294 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.demand_mshr_miss_latency::total 6747751294 # number of demand (read+write) MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6747751294 # number of overall MSHR miss cycles
445system.cpu.dcache.overall_mshr_miss_latency::total 6747751294 # number of overall MSHR miss cycles
446system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042842 # mshr miss rate for ReadReq accesses

447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses

448system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses
449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses
450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2789.648272 # average ReadReq mshr miss latency
451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033 # average WriteReq mshr miss latency
452system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency
453system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency

448system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for demand accesses
449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for overall accesses
450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2802.706140 # average ReadReq mshr miss latency
451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14117.238576 # average WriteReq mshr miss latency
452system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency
453system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency

454system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

455system.cpu.l2cache.replacements 33246 # number of replacements
456system.cpu.l2cache.tagsinuse 18964.988080 # Cycle average of tags in use
457system.cpu.l2cache.total_refs 3764517 # Total number of references to valid blocks.
458system.cpu.l2cache.sampled_refs 61253 # Sample count of references to valid blocks.
459system.cpu.l2cache.avg_refs 61.458492 # Average number of references to valid blocks.

455system.cpu.l2cache.replacements 33385 # number of replacements
456system.cpu.l2cache.tagsinuse 18998.818974 # Cycle average of tags in use
457system.cpu.l2cache.total_refs 3761978 # Total number of references to valid blocks.
458system.cpu.l2cache.sampled_refs 61393 # Sample count of references to valid blocks.
459system.cpu.l2cache.avg_refs 61.276986 # Average number of references to valid blocks.

460system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

461system.cpu.l2cache.occ_blocks::writebacks 12927.949414 # Average occupied blocks per requestor
462system.cpu.l2cache.occ_blocks::cpu.inst 243.086422 # Average occupied blocks per requestor
463system.cpu.l2cache.occ_blocks::cpu.data 5793.952244 # Average occupied blocks per requestor
464system.cpu.l2cache.occ_percent::writebacks 0.394530 # Average percentage of cache occupancy
465system.cpu.l2cache.occ_percent::cpu.inst 0.007418 # Average percentage of cache occupancy
466system.cpu.l2cache.occ_percent::cpu.data 0.176817 # Average percentage of cache occupancy
467system.cpu.l2cache.occ_percent::total 0.578766 # Average percentage of cache occupancy
468system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
469system.cpu.l2cache.ReadReq_hits::cpu.data 1964440 # number of ReadReq hits
470system.cpu.l2cache.ReadReq_hits::total 1964445 # number of ReadReq hits
471system.cpu.l2cache.Writeback_hits::writebacks 1880780 # number of Writeback hits
472system.cpu.l2cache.Writeback_hits::total 1880780 # number of Writeback hits
473system.cpu.l2cache.ReadExReq_hits::cpu.data 52709 # number of ReadExReq hits
474system.cpu.l2cache.ReadExReq_hits::total 52709 # number of ReadExReq hits
475system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::cpu.data 2017149 # number of demand (read+write) hits
477system.cpu.l2cache.demand_hits::total 2017154 # number of demand (read+write) hits
478system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
479system.cpu.l2cache.overall_hits::cpu.data 2017149 # number of overall hits
480system.cpu.l2cache.overall_hits::total 2017154 # number of overall hits
481system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses
482system.cpu.l2cache.ReadReq_misses::cpu.data 30342 # number of ReadReq misses
483system.cpu.l2cache.ReadReq_misses::total 31361 # number of ReadReq misses

461system.cpu.l2cache.occ_blocks::writebacks 12949.193091 # Average occupied blocks per requestor
462system.cpu.l2cache.occ_blocks::cpu.inst 250.074892 # Average occupied blocks per requestor
463system.cpu.l2cache.occ_blocks::cpu.data 5799.550991 # Average occupied blocks per requestor
464system.cpu.l2cache.occ_percent::writebacks 0.395178 # Average percentage of cache occupancy
465system.cpu.l2cache.occ_percent::cpu.inst 0.007632 # Average percentage of cache occupancy
466system.cpu.l2cache.occ_percent::cpu.data 0.176988 # Average percentage of cache occupancy
467system.cpu.l2cache.occ_percent::total 0.579798 # Average percentage of cache occupancy
468system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
469system.cpu.l2cache.ReadReq_hits::cpu.data 1963577 # number of ReadReq hits
470system.cpu.l2cache.ReadReq_hits::total 1963591 # number of ReadReq hits
471system.cpu.l2cache.Writeback_hits::writebacks 1879081 # number of Writeback hits
472system.cpu.l2cache.Writeback_hits::total 1879081 # number of Writeback hits
473system.cpu.l2cache.ReadExReq_hits::cpu.data 52700 # number of ReadExReq hits
474system.cpu.l2cache.ReadExReq_hits::total 52700 # number of ReadExReq hits
475system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::cpu.data 2016277 # number of demand (read+write) hits
477system.cpu.l2cache.demand_hits::total 2016291 # number of demand (read+write) hits
478system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
479system.cpu.l2cache.overall_hits::cpu.data 2016277 # number of overall hits
480system.cpu.l2cache.overall_hits::total 2016291 # number of overall hits
481system.cpu.l2cache.ReadReq_misses::cpu.inst 1079 # number of ReadReq misses
482system.cpu.l2cache.ReadReq_misses::cpu.data 30422 # number of ReadReq misses
483system.cpu.l2cache.ReadReq_misses::total 31501 # number of ReadReq misses

484system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
485system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses

486system.cpu.l2cache.ReadExReq_misses::cpu.data 29513 # number of ReadExReq misses
487system.cpu.l2cache.ReadExReq_misses::total 29513 # number of ReadExReq misses
488system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses
489system.cpu.l2cache.demand_misses::cpu.data 59855 # number of demand (read+write) misses
490system.cpu.l2cache.demand_misses::total 60874 # number of demand (read+write) misses
491system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses
492system.cpu.l2cache.overall_misses::cpu.data 59855 # number of overall misses
493system.cpu.l2cache.overall_misses::total 60874 # number of overall misses
494system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34913500 # number of ReadReq miss cycles
495system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1036289000 # number of ReadReq miss cycles
496system.cpu.l2cache.ReadReq_miss_latency::total 1071202500 # number of ReadReq miss cycles
497system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006190000 # number of ReadExReq miss cycles
498system.cpu.l2cache.ReadExReq_miss_latency::total 1006190000 # number of ReadExReq miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.inst 34913500 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::cpu.data 2042479000 # number of demand (read+write) miss cycles
501system.cpu.l2cache.demand_miss_latency::total 2077392500 # number of demand (read+write) miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.inst 34913500 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::cpu.data 2042479000 # number of overall miss cycles
504system.cpu.l2cache.overall_miss_latency::total 2077392500 # number of overall miss cycles
505system.cpu.l2cache.ReadReq_accesses::cpu.inst 1024 # number of ReadReq accesses(hits+misses)
506system.cpu.l2cache.ReadReq_accesses::cpu.data 1994782 # number of ReadReq accesses(hits+misses)
507system.cpu.l2cache.ReadReq_accesses::total 1995806 # number of ReadReq accesses(hits+misses)
508system.cpu.l2cache.Writeback_accesses::writebacks 1880780 # number of Writeback accesses(hits+misses)
509system.cpu.l2cache.Writeback_accesses::total 1880780 # number of Writeback accesses(hits+misses)

486system.cpu.l2cache.ReadExReq_misses::cpu.data 29515 # number of ReadExReq misses
487system.cpu.l2cache.ReadExReq_misses::total 29515 # number of ReadExReq misses
488system.cpu.l2cache.demand_misses::cpu.inst 1079 # number of demand (read+write) misses
489system.cpu.l2cache.demand_misses::cpu.data 59937 # number of demand (read+write) misses
490system.cpu.l2cache.demand_misses::total 61016 # number of demand (read+write) misses
491system.cpu.l2cache.overall_misses::cpu.inst 1079 # number of overall misses
492system.cpu.l2cache.overall_misses::cpu.data 59937 # number of overall misses
493system.cpu.l2cache.overall_misses::total 61016 # number of overall misses
494system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36980000 # number of ReadReq miss cycles
495system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1039210000 # number of ReadReq miss cycles
496system.cpu.l2cache.ReadReq_miss_latency::total 1076190000 # number of ReadReq miss cycles
497system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006243500 # number of ReadExReq miss cycles
498system.cpu.l2cache.ReadExReq_miss_latency::total 1006243500 # number of ReadExReq miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.inst 36980000 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::cpu.data 2045453500 # number of demand (read+write) miss cycles
501system.cpu.l2cache.demand_miss_latency::total 2082433500 # number of demand (read+write) miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.inst 36980000 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::cpu.data 2045453500 # number of overall miss cycles
504system.cpu.l2cache.overall_miss_latency::total 2082433500 # number of overall miss cycles
505system.cpu.l2cache.ReadReq_accesses::cpu.inst 1093 # number of ReadReq accesses(hits+misses)
506system.cpu.l2cache.ReadReq_accesses::cpu.data 1993999 # number of ReadReq accesses(hits+misses)
507system.cpu.l2cache.ReadReq_accesses::total 1995092 # number of ReadReq accesses(hits+misses)
508system.cpu.l2cache.Writeback_accesses::writebacks 1879081 # number of Writeback accesses(hits+misses)
509system.cpu.l2cache.Writeback_accesses::total 1879081 # number of Writeback accesses(hits+misses)

510system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
511system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)

512system.cpu.l2cache.ReadExReq_accesses::cpu.data 82222 # number of ReadExReq accesses(hits+misses)
513system.cpu.l2cache.ReadExReq_accesses::total 82222 # number of ReadExReq accesses(hits+misses)
514system.cpu.l2cache.demand_accesses::cpu.inst 1024 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 2077004 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 2078028 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 1024 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 2077004 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 2078028 # number of overall (read+write) accesses
520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995117 # miss rate for ReadReq accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015211 # miss rate for ReadReq accesses

512system.cpu.l2cache.ReadExReq_accesses::cpu.data 82215 # number of ReadExReq accesses(hits+misses)
513system.cpu.l2cache.ReadExReq_accesses::total 82215 # number of ReadExReq accesses(hits+misses)
514system.cpu.l2cache.demand_accesses::cpu.inst 1093 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 2076214 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 2077307 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 1093 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 2076214 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 2077307 # number of overall (read+write) accesses
520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.987191 # miss rate for ReadReq accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015257 # miss rate for ReadReq accesses

522system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses

523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358943 # miss rate for ReadExReq accesses
524system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995117 # miss rate for demand accesses
525system.cpu.l2cache.demand_miss_rate::cpu.data 0.028818 # miss rate for demand accesses
526system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995117 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::cpu.data 0.028818 # miss rate for overall accesses
528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267 # average ReadReq miss latency
529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451 # average ReadReq miss latency
530system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510 # average ReadExReq miss latency
531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency
532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency
534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency

523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358998 # miss rate for ReadExReq accesses
524system.cpu.l2cache.demand_miss_rate::cpu.inst 0.987191 # miss rate for demand accesses
525system.cpu.l2cache.demand_miss_rate::cpu.data 0.028868 # miss rate for demand accesses
526system.cpu.l2cache.overall_miss_rate::cpu.inst 0.987191 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::cpu.data 0.028868 # miss rate for overall accesses
528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.474513 # average ReadReq miss latency
529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34159.818552 # average ReadReq miss latency
530system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34092.613925 # average ReadExReq miss latency
531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency
532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency
534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency

535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
539system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
540system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
541system.cpu.l2cache.fast_writes 0 # number of fast writes performed
542system.cpu.l2cache.cache_copies 0 # number of cache copies performed

543system.cpu.l2cache.writebacks::writebacks 13942 # number of writebacks
544system.cpu.l2cache.writebacks::total 13942 # number of writebacks
545system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
546system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30342 # number of ReadReq MSHR misses
547system.cpu.l2cache.ReadReq_mshr_misses::total 31361 # number of ReadReq MSHR misses

543system.cpu.l2cache.writebacks::writebacks 13993 # number of writebacks
544system.cpu.l2cache.writebacks::total 13993 # number of writebacks
545system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses
546system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30422 # number of ReadReq MSHR misses
547system.cpu.l2cache.ReadReq_mshr_misses::total 31501 # number of ReadReq MSHR misses

548system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
549system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses

550system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29513 # number of ReadExReq MSHR misses
551system.cpu.l2cache.ReadExReq_mshr_misses::total 29513 # number of ReadExReq MSHR misses
552system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
553system.cpu.l2cache.demand_mshr_misses::cpu.data 59855 # number of demand (read+write) MSHR misses
554system.cpu.l2cache.demand_mshr_misses::total 60874 # number of demand (read+write) MSHR misses
555system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
556system.cpu.l2cache.overall_mshr_misses::cpu.data 59855 # number of overall MSHR misses
557system.cpu.l2cache.overall_mshr_misses::total 60874 # number of overall MSHR misses
558system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31643000 # number of ReadReq MSHR miss cycles
559system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941211000 # number of ReadReq MSHR miss cycles
560system.cpu.l2cache.ReadReq_mshr_miss_latency::total 972854000 # number of ReadReq MSHR miss cycles

550system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29515 # number of ReadExReq MSHR misses
551system.cpu.l2cache.ReadExReq_mshr_misses::total 29515 # number of ReadExReq MSHR misses
552system.cpu.l2cache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses
553system.cpu.l2cache.demand_mshr_misses::cpu.data 59937 # number of demand (read+write) MSHR misses
554system.cpu.l2cache.demand_mshr_misses::total 61016 # number of demand (read+write) MSHR misses
555system.cpu.l2cache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses
556system.cpu.l2cache.overall_mshr_misses::cpu.data 59937 # number of overall MSHR misses
557system.cpu.l2cache.overall_mshr_misses::total 61016 # number of overall MSHR misses
558system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33519500 # number of ReadReq MSHR miss cycles
559system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 943737500 # number of ReadReq MSHR miss cycles
560system.cpu.l2cache.ReadReq_mshr_miss_latency::total 977257000 # number of ReadReq MSHR miss cycles

561system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
562system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles

563system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 914925500 # number of ReadExReq MSHR miss cycles
564system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 914925500 # number of ReadExReq MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31643000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856136500 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.demand_mshr_miss_latency::total 1887779500 # number of demand (read+write) MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles
569system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles
570system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles
571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses
572system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses

563system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915036000 # number of ReadExReq MSHR miss cycles
564system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915036000 # number of ReadExReq MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33519500 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1858773500 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.demand_mshr_miss_latency::total 1892293000 # number of demand (read+write) MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33519500 # number of overall MSHR miss cycles
569system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1858773500 # number of overall MSHR miss cycles
570system.cpu.l2cache.overall_mshr_miss_latency::total 1892293000 # number of overall MSHR miss cycles
571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for ReadReq accesses
572system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015257 # mshr miss rate for ReadReq accesses

573system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses

574system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses
575system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses
576system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses
577system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses
578system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses
579system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency
580system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency

574system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358998 # mshr miss rate for ReadExReq accesses
575system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for demand accesses
576system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for demand accesses
577system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for overall accesses
578system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for overall accesses
579system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.338276 # average ReadReq mshr miss latency
580system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31021.546907 # average ReadReq mshr miss latency

581system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency

582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency
583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency
584system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency
586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency

582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.405556 # average ReadExReq mshr miss latency
583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency
584system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency
586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency