| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.065987 # Number of seconds simulated 4sim_ticks 65986743500 # Number of ticks simulated 5final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.065554 # Number of seconds simulated 4sim_ticks 65553895500 # Number of ticks simulated 5final_tick 65553895500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 86207 # Simulator instruction rate (inst/s) 8host_op_rate 151797 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36005878 # Simulator tick rate (ticks/s) 10host_mem_usage 411344 # Number of bytes of host memory used 11host_seconds 1832.67 # Real time elapsed on the host | 7host_inst_rate 122580 # Simulator instruction rate (inst/s) 8host_op_rate 215844 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50862026 # Simulator tick rate (ticks/s) 10host_mem_usage 417260 # Number of bytes of host memory used 11host_seconds 1288.86 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 69632 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1890944 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1960576 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 69632 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 69632 # Number of instructions bytes read from this memory |
| 22system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory 23system.physmem.bytes_written::total 17920 # Number of bytes written to this memory | 22system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory 23system.physmem.bytes_written::total 17920 # Number of bytes written to this memory |
| 24system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.inst 1088 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 29546 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 30634 # Number of read requests responded to by this memory |
| 27system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 280 # Number of write requests responded to by this memory | 27system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 280 # Number of write requests responded to by this memory |
| 29system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 30622 # Number of read requests accepted | 29system.physmem.bw_read::cpu.inst 1062210 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 28845639 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 29907849 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1062210 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1062210 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 273363 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 273363 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 273363 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1062210 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 28845639 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 30181212 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 30634 # Number of read requests accepted |
| 41system.physmem.writeReqs 280 # Number of write requests accepted | 41system.physmem.writeReqs 280 # Number of write requests accepted |
| 42system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue | 42system.physmem.readBursts 30634 # Number of DRAM read bursts, including those serviced by the write queue |
| 43system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue | 43system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue |
| 44system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue 46system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side | 44system.physmem.bytesReadDRAM 1951616 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue 46system.physmem.bytesWritten 16000 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 1960576 # Total read bytes from the system interface side |
| 48system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side | 48system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side |
| 49system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue | 49system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 52system.physmem.perBankRdBursts::0 1932 # Per bank write bursts 53system.physmem.perBankRdBursts::1 2084 # Per bank write bursts 54system.physmem.perBankRdBursts::2 2041 # Per bank write bursts 55system.physmem.perBankRdBursts::3 1935 # Per bank write bursts 56system.physmem.perBankRdBursts::4 2086 # Per bank write bursts 57system.physmem.perBankRdBursts::5 1909 # Per bank write bursts 58system.physmem.perBankRdBursts::6 1974 # Per bank write bursts 59system.physmem.perBankRdBursts::7 1865 # Per bank write bursts 60system.physmem.perBankRdBursts::8 1948 # Per bank write bursts | 52system.physmem.perBankRdBursts::0 1938 # Per bank write bursts 53system.physmem.perBankRdBursts::1 2083 # Per bank write bursts 54system.physmem.perBankRdBursts::2 2040 # Per bank write bursts 55system.physmem.perBankRdBursts::3 1941 # Per bank write bursts 56system.physmem.perBankRdBursts::4 2041 # Per bank write bursts 57system.physmem.perBankRdBursts::5 1918 # Per bank write bursts 58system.physmem.perBankRdBursts::6 1976 # Per bank write bursts 59system.physmem.perBankRdBursts::7 1870 # Per bank write bursts 60system.physmem.perBankRdBursts::8 1951 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::9 1940 # Per bank write bursts | 61system.physmem.perBankRdBursts::9 1940 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::10 1806 # Per bank write bursts | 62system.physmem.perBankRdBursts::10 1805 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::11 1794 # Per bank write bursts 64system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 65system.physmem.perBankRdBursts::13 1799 # Per bank write bursts | 63system.physmem.perBankRdBursts::11 1794 # Per bank write bursts 64system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 65system.physmem.perBankRdBursts::13 1799 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::14 1828 # Per bank write bursts | 66system.physmem.perBankRdBursts::14 1827 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::15 1779 # Per bank write bursts 68system.physmem.perBankWrBursts::0 10 # Per bank write bursts 69system.physmem.perBankWrBursts::1 107 # Per bank write bursts | 67system.physmem.perBankRdBursts::15 1779 # Per bank write bursts 68system.physmem.perBankWrBursts::0 10 # Per bank write bursts 69system.physmem.perBankWrBursts::1 107 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::2 30 # Per bank write bursts 71system.physmem.perBankWrBursts::3 12 # Per bank write bursts 72system.physmem.perBankWrBursts::4 60 # Per bank write bursts 73system.physmem.perBankWrBursts::5 8 # Per bank write bursts | 70system.physmem.perBankWrBursts::2 31 # Per bank write bursts 71system.physmem.perBankWrBursts::3 25 # Per bank write bursts 72system.physmem.perBankWrBursts::4 39 # Per bank write bursts 73system.physmem.perBankWrBursts::5 13 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::6 16 # Per bank write bursts | 74system.physmem.perBankWrBursts::6 16 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::7 0 # Per bank write bursts | 75system.physmem.perBankWrBursts::7 1 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::8 0 # Per bank write bursts 77system.physmem.perBankWrBursts::9 5 # Per bank write bursts 78system.physmem.perBankWrBursts::10 3 # Per bank write bursts 79system.physmem.perBankWrBursts::11 0 # Per bank write bursts 80system.physmem.perBankWrBursts::12 0 # Per bank write bursts 81system.physmem.perBankWrBursts::13 0 # Per bank write bursts 82system.physmem.perBankWrBursts::14 0 # Per bank write bursts 83system.physmem.perBankWrBursts::15 0 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 76system.physmem.perBankWrBursts::8 0 # Per bank write bursts 77system.physmem.perBankWrBursts::9 5 # Per bank write bursts 78system.physmem.perBankWrBursts::10 3 # Per bank write bursts 79system.physmem.perBankWrBursts::11 0 # Per bank write bursts 80system.physmem.perBankWrBursts::12 0 # Per bank write bursts 81system.physmem.perBankWrBursts::13 0 # Per bank write bursts 82system.physmem.perBankWrBursts::14 0 # Per bank write bursts 83system.physmem.perBankWrBursts::15 0 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 65986546500 # Total gap between requests | 86system.physmem.totGap 65553697500 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 93system.physmem.readPktSize::6 30622 # Read request sizes (log2) | 93system.physmem.readPktSize::6 30634 # Read request sizes (log2) |
| 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 280 # Write request sizes (log2) | 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 280 # Write request sizes (log2) |
| 101system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 29978 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see | 104system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see |
| 105system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 105system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 15 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::21 15 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see | 161system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see --- 19 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see --- 19 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation | 197system.physmem.bytesPerActivate::samples 2859 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 687.860091 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 477.665686 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 399.129385 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 441 15.42% 15.42% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 263 9.20% 24.62% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 134 4.69% 29.31% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 136 4.76% 34.07% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 118 4.13% 38.20% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 116 4.06% 42.25% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 85 2.97% 45.23% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 96 3.36% 48.58% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 1470 51.42% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 2859 # Bytes accessed per row activation |
| 211system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes | 211system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes |
| 212system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes | 212system.physmem.rdPerTurnAround::mean 2173.928571 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 21.222071 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 8074.812153 # Reads before turning the bus around for writes |
| 215system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads | 215system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads |
| 219system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads | 219system.physmem.wrPerTurnAround::mean 17.857143 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 17.849200 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.534522 # Writes before turning the bus around for reads |
| 222system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads | 222system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads |
| 223system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads | 223system.physmem.wrPerTurnAround::18 13 92.86% 100.00% # Writes before turning the bus around for reads |
| 225system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads | 224system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads |
| 226system.physmem.totQLat 136557750 # Total ticks spent queuing 227system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM 228system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers 229system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst | 225system.physmem.totQLat 136299000 # Total ticks spent queuing 226system.physmem.totMemAccLat 708061500 # Total ticks spent from burst creation until serviced by the DRAM 227system.physmem.totBusLat 152470000 # Total ticks spent in databus transfers 228system.physmem.avgQLat 4469.70 # Average queueing delay per DRAM burst |
| 230system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 231system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst 232system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s | 230system.physmem.avgMemAccLat 23219.70 # Average memory access latency per DRAM burst 231system.physmem.avgRdBW 29.77 # Average DRAM read bandwidth in MiByte/s |
| 233system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s | 232system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s |
| 234system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s | 233system.physmem.avgRdBWSys 29.91 # Average system read bandwidth in MiByte/s |
| 235system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s 236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 237system.physmem.busUtil 0.23 # Data bus utilization in percentage 238system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads 239system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 234system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.23 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 240system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 241system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing 242system.physmem.readRowHits 27745 # Number of row buffer hits during reads 243system.physmem.writeRowHits 178 # Number of row buffer hits during writes 244system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads 245system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes 246system.physmem.avgGap 2135348.73 # Average gap between requests 247system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined 248system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) 249system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) 250system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) 251system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) 252system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) 253system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) 254system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) 255system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) 256system.physmem_0.averagePower 673.125124 # Core power per rank (mW) 257system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states 258system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states | 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 11.62 # Average write queue length when enqueuing 241system.physmem.readRowHits 27721 # Number of row buffer hits during reads 242system.physmem.writeRowHits 161 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 90.91 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 57.50 # Row buffer hit rate for writes 245system.physmem.avgGap 2120518.13 # Average gap between requests 246system.physmem.pageHitRate 90.60 # Row buffer hit rate, read and write combined 247system.physmem_0.actEnergy 11740680 # Energy for activate commands per rank (pJ) 248system.physmem_0.preEnergy 6406125 # Energy for precharge commands per rank (pJ) 249system.physmem_0.readEnergy 123169800 # Energy for read commands per rank (pJ) 250system.physmem_0.writeEnergy 1568160 # Energy for write commands per rank (pJ) 251system.physmem_0.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) 252system.physmem_0.actBackEnergy 3052855305 # Energy for active background per rank (pJ) 253system.physmem_0.preBackEnergy 36653676000 # Energy for precharge background per rank (pJ) 254system.physmem_0.totalEnergy 44130982710 # Total energy per rank (pJ) 255system.physmem_0.averagePower 673.213820 # Core power per rank (mW) 256system.physmem_0.memoryStateTime::IDLE 60959756000 # Time in different power states 257system.physmem_0.memoryStateTime::REF 2188940000 # Time in different power states |
| 259system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 258system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 260system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states | 259system.physmem_0.memoryStateTime::ACT 2404016500 # Time in different power states |
| 261system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 260system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 262system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) 263system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) 264system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) | 261system.physmem_1.actEnergy 9873360 # Energy for activate commands per rank (pJ) 262system.physmem_1.preEnergy 5387250 # Energy for precharge commands per rank (pJ) 263system.physmem_1.readEnergy 114558600 # Energy for read commands per rank (pJ) |
| 265system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) | 264system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) |
| 266system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) 267system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) 268system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) 269system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) 270system.physmem_1.averagePower 673.182663 # Core power per rank (mW) 271system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states 272system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states | 265system.physmem_1.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) 266system.physmem_1.actBackEnergy 3230070300 # Energy for active background per rank (pJ) 267system.physmem_1.preBackEnergy 36498224250 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 44139732240 # Total energy per rank (pJ) 269system.physmem_1.averagePower 673.347293 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 60700713000 # Time in different power states 271system.physmem_1.memoryStateTime::REF 2188940000 # Time in different power states |
| 273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 274system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states | 273system.physmem_1.memoryStateTime::ACT 2663059500 # Time in different power states |
| 275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 276system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 277system.cpu.branchPred.lookups 40828848 # Number of BP lookups 278system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted 279system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect 280system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups | 275system.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 276system.cpu.branchPred.lookups 40360668 # Number of BP lookups 277system.cpu.branchPred.condPredicted 40360668 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 1392637 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 26664097 # Number of BTB lookups |
| 281system.cpu.branchPred.BTBHits 0 # Number of BTB hits 282system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 283system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage | 280system.cpu.branchPred.BTBHits 0 # Number of BTB hits 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 282system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage |
| 284system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. 285system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. 286system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. 287system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. 288system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. 289system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. | 283system.cpu.branchPred.usedRAS 5988252 # Number of times the RAS was used to get a target. 284system.cpu.branchPred.RASInCorrect 86625 # Number of incorrect RAS predictions. 285system.cpu.branchPred.indirectLookups 26664097 # Number of indirect predictor lookups. 286system.cpu.branchPred.indirectHits 21157452 # Number of indirect target hits. 287system.cpu.branchPred.indirectMisses 5506645 # Number of indirect misses. 288system.cpu.branchPredindirectMispredicted 511906 # Number of mispredicted indirect branches. |
| 290system.cpu_clk_domain.clock 500 # Clock period in ticks | 289system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 291system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states | 290system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states |
| 292system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 291system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 293system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 294system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states | 292system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 293system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states |
| 295system.cpu.workload.num_syscalls 444 # Number of system calls | 294system.cpu.workload.num_syscalls 444 # Number of system calls |
| 296system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states 297system.cpu.numCycles 131973488 # number of cpu cycles simulated | 295system.cpu.pwrStateResidencyTicks::ON 65553895500 # Cumulative time (in ticks) in various power states 296system.cpu.numCycles 131107792 # number of cpu cycles simulated |
| 298system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 299system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 297system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 298system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 300system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss 301system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed 302system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered 303system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken 304system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked 305system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing 306system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb 307system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 308system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps 309system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions 310system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR 311system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched 312system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed 313system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed 314system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) | 299system.cpu.fetch.icacheStallCycles 30523578 # Number of cycles fetch is stalled on an Icache miss 300system.cpu.fetch.Insts 219647427 # Number of instructions fetch has processed 301system.cpu.fetch.Branches 40360668 # Number of branches that fetch encountered 302system.cpu.fetch.predictedBranches 27145704 # Number of branches that fetch has predicted taken 303system.cpu.fetch.Cycles 98945290 # Number of cycles fetch has run and was not squashing or blocked 304system.cpu.fetch.SquashCycles 2900833 # Number of cycles fetch has spent squashing 305system.cpu.fetch.TlbCycles 518 # Number of cycles fetch has spent waiting for tlb 306system.cpu.fetch.MiscStallCycles 6239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 307system.cpu.fetch.PendingTrapStallCycles 114030 # Number of stall cycles due to pending traps 308system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions 309system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR 310system.cpu.fetch.CacheLines 29742559 # Number of cache lines fetched 311system.cpu.fetch.IcacheSquashes 352958 # Number of outstanding Icache misses that were squashed 312system.cpu.fetch.ItlbSquashes 20 # Number of outstanding ITLB misses that were squashed 313system.cpu.fetch.rateDist::samples 131040277 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::mean 2.949675 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::stdev 3.407509 # Number of instructions fetched each cycle (Total) |
| 317system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 316system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 318system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) | 317system.cpu.fetch.rateDist::0 65532629 50.01% 50.01% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::1 4015050 3.06% 53.07% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::2 3611452 2.76% 55.83% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::3 6110552 4.66% 60.49% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::4 7743592 5.91% 66.40% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::5 5553299 4.24% 70.64% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::6 3377797 2.58% 73.22% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::7 2818268 2.15% 75.37% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::8 32277638 24.63% 100.00% # Number of instructions fetched each cycle (Total) |
| 327system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 330system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle 332system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle 333system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle 334system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked 335system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running 336system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking 337system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing 338system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode 339system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing 340system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle 341system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking 342system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst 343system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running 344system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking 345system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename 346system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full 347system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full 348system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full 349system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full 350system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed 351system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made 352system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups 353system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups | 329system.cpu.fetch.rateDist::total 131040277 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.branchRate 0.307843 # Number of branch fetches per cycle 331system.cpu.fetch.rate 1.675319 # Number of inst fetches per cycle 332system.cpu.decode.IdleCycles 15257836 # Number of cycles decode is idle 333system.cpu.decode.BlockedCycles 64260169 # Number of cycles decode is blocked 334system.cpu.decode.RunCycles 40205069 # Number of cycles decode is running 335system.cpu.decode.UnblockCycles 9866787 # Number of cycles decode is unblocking 336system.cpu.decode.SquashCycles 1450416 # Number of cycles decode is squashing 337system.cpu.decode.DecodedInsts 361840570 # Number of instructions handled by decode 338system.cpu.rename.SquashCycles 1450416 # Number of cycles rename is squashing 339system.cpu.rename.IdleCycles 20789312 # Number of cycles rename is idle 340system.cpu.rename.BlockCycles 11161609 # Number of cycles rename is blocking 341system.cpu.rename.serializeStallCycles 17754 # count of cycles rename stalled for serializing inst 342system.cpu.rename.RunCycles 44252475 # Number of cycles rename is running 343system.cpu.rename.UnblockCycles 53368711 # Number of cycles rename is unblocking 344system.cpu.rename.RenamedInsts 352352816 # Number of instructions processed by rename 345system.cpu.rename.ROBFullEvents 16475 # Number of times rename has blocked due to ROB full 346system.cpu.rename.IQFullEvents 802883 # Number of times rename has blocked due to IQ full 347system.cpu.rename.LQFullEvents 46797603 # Number of times rename has blocked due to LQ full 348system.cpu.rename.SQFullEvents 4838735 # Number of times rename has blocked due to SQ full 349system.cpu.rename.RenamedOperands 354809982 # Number of destination operands rename has renamed 350system.cpu.rename.RenameLookups 933969547 # Number of register rename lookups that rename has made 351system.cpu.rename.int_rename_lookups 575070468 # Number of integer rename lookups 352system.cpu.rename.fp_rename_lookups 25233 # Number of floating rename lookups |
| 354system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed | 353system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed |
| 355system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing 356system.cpu.rename.serializingInsts 501 # count of serializing insts renamed 357system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed 358system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer 359system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. 360system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. 361system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. 362system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. 363system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) 364system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ 365system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued 366system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued 367system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph 369system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed 370system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle | 354system.cpu.rename.UndoneMaps 75597235 # Number of HB maps that are undone due to squashing 355system.cpu.rename.serializingInsts 487 # count of serializing insts renamed 356system.cpu.rename.tempSerializingInsts 488 # count of temporary serializing insts renamed 357system.cpu.rename.skidInsts 64661942 # count of insts added to the skid buffer 358system.cpu.memDep0.insertedLoads 112312024 # Number of loads inserted to the mem dependence unit. 359system.cpu.memDep0.insertedStores 38476139 # Number of stores inserted to the mem dependence unit. 360system.cpu.memDep0.conflictingLoads 51587404 # Number of conflicting loads. 361system.cpu.memDep0.conflictingStores 9144280 # Number of conflicting stores. 362system.cpu.iq.iqInstsAdded 343861767 # Number of instructions added to the IQ (excludes non-spec) 363system.cpu.iq.iqNonSpecInstsAdded 4715 # Number of non-speculative instructions added to the IQ 364system.cpu.iq.iqInstsIssued 317818488 # Number of instructions issued 365system.cpu.iq.iqSquashedInstsIssued 169830 # Number of squashed instructions issued 366system.cpu.iq.iqSquashedInstsExamined 65674018 # Number of squashed instructions iterated over during squash; mainly for profiling 367system.cpu.iq.iqSquashedOperandsExamined 101673382 # Number of squashed operands that are examined and possibly removed from graph 368system.cpu.iq.iqSquashedNonSpecRemoved 4270 # Number of squashed non-spec instructions that were removed 369system.cpu.iq.issued_per_cycle::samples 131040277 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::mean 2.425350 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::stdev 2.164581 # Number of insts issued each cycle |
| 373system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 372system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 374system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle | 373system.cpu.iq.issued_per_cycle::0 35194225 26.86% 26.86% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::1 20112862 15.35% 42.21% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::2 17093441 13.04% 55.25% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::3 17641161 13.46% 68.71% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::4 15328111 11.70% 80.41% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::5 12869587 9.82% 90.23% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::6 6689257 5.10% 95.34% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::7 4093724 3.12% 98.46% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::8 2017909 1.54% 100.00% # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 386system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle | 385system.cpu.iq.issued_per_cycle::total 131040277 # Number of insts issued each cycle |
| 387system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 386system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 388system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 417system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available 418system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available | 387system.cpu.iq.fu_full::IntAlu 366862 8.95% 8.95% # attempts to use FU when none available 388system.cpu.iq.fu_full::IntMult 0 0.00% 8.95% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available 416system.cpu.iq.fu_full::MemRead 3538662 86.29% 95.24% # attempts to use FU when none available 417system.cpu.iq.fu_full::MemWrite 195200 4.76% 100.00% # attempts to use FU when none available |
| 419system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 421system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued | 418system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 419system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 420system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued |
| 422system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued 423system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued 424system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued 451system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued 452system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued | 421system.cpu.iq.FU_type_0::IntAlu 181791277 57.20% 57.21% # Type of FU issued 422system.cpu.iq.FU_type_0::IntMult 11724 0.00% 57.21% # Type of FU issued 423system.cpu.iq.FU_type_0::IntDiv 408 0.00% 57.21% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatAdd 305 0.00% 57.21% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued 450system.cpu.iq.FU_type_0::MemRead 101272470 31.86% 89.08% # Type of FU issued 451system.cpu.iq.FU_type_0::MemWrite 34708964 10.92% 100.00% # Type of FU issued |
| 453system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 452system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 453system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 455system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued 456system.cpu.iq.rate 2.417343 # Inst issue rate 457system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested 458system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) 459system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads 460system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes 461system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses 462system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads 463system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes 464system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses 465system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses 466system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses 467system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores | 454system.cpu.iq.FU_type_0::total 317818488 # Type of FU issued 455system.cpu.iq.rate 2.424101 # Inst issue rate 456system.cpu.iq.fu_busy_cnt 4100724 # FU busy when requested 457system.cpu.iq.fu_busy_rate 0.012903 # FU busy rate (busy events/executed inst) 458system.cpu.iq.int_inst_queue_reads 770927721 # Number of integer instruction queue reads 459system.cpu.iq.int_inst_queue_writes 409562927 # Number of integer instruction queue writes 460system.cpu.iq.int_inst_queue_wakeup_accesses 313648272 # Number of integer instruction queue wakeup accesses 461system.cpu.iq.fp_inst_queue_reads 20086 # Number of floating instruction queue reads 462system.cpu.iq.fp_inst_queue_writes 38326 # Number of floating instruction queue writes 463system.cpu.iq.fp_inst_queue_wakeup_accesses 4607 # Number of floating instruction queue wakeup accesses 464system.cpu.iq.int_alu_accesses 321877132 # Number of integer alu accesses 465system.cpu.iq.fp_alu_accesses 8740 # Number of floating point alu accesses 466system.cpu.iew.lsq.thread0.forwLoads 57541030 # Number of loads that had data forwarded from stores |
| 468system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 467system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 469system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed 470system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed 471system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations 472system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed | 468system.cpu.iew.lsq.thread0.squashedLoads 21532639 # Number of loads squashed 469system.cpu.iew.lsq.thread0.ignoredResponses 67356 # Number of memory responses ignored because the instruction is squashed 470system.cpu.iew.lsq.thread0.memOrderViolation 63407 # Number of memory ordering violations 471system.cpu.iew.lsq.thread0.squashedStores 7036387 # Number of stores squashed |
| 473system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 474system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 472system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 473system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 475system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled 476system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked | 474system.cpu.iew.lsq.thread0.rescheduledLoads 3908 # Number of loads that were rescheduled 475system.cpu.iew.lsq.thread0.cacheBlocked 141249 # Number of times an access to memory failed due to the cache being blocked |
| 477system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 476system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 478system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing 479system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking 480system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking 481system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ 482system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch 483system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions 484system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions 485system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions 486system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall 487system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall 488system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations 489system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly 490system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly 491system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute 492system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions 493system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed 494system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute | 477system.cpu.iew.iewSquashCycles 1450416 # Number of cycles IEW is squashing 478system.cpu.iew.iewBlockCycles 8045146 # Number of cycles IEW is blocking 479system.cpu.iew.iewUnblockCycles 3020269 # Number of cycles IEW is unblocking 480system.cpu.iew.iewDispatchedInsts 343866482 # Number of instructions dispatched to IQ 481system.cpu.iew.iewDispSquashedInsts 122594 # Number of squashed instructions skipped by dispatch 482system.cpu.iew.iewDispLoadInsts 112312024 # Number of dispatched load instructions 483system.cpu.iew.iewDispStoreInsts 38476139 # Number of dispatched store instructions 484system.cpu.iew.iewDispNonSpecInsts 1910 # Number of dispatched non-speculative instructions 485system.cpu.iew.iewIQFullEvents 3213 # Number of times the IQ has become full, causing a stall 486system.cpu.iew.iewLSQFullEvents 3025719 # Number of times the LSQ has become full, causing a stall 487system.cpu.iew.memOrderViolationEvents 63407 # Number of memory order violations 488system.cpu.iew.predictedTakenIncorrect 529775 # Number of branches that were predicted taken incorrectly 489system.cpu.iew.predictedNotTakenIncorrect 1033204 # Number of branches that were predicted not taken incorrectly 490system.cpu.iew.branchMispredicts 1562979 # Number of branch mispredicts detected at execute 491system.cpu.iew.iewExecutedInsts 315414153 # Number of executed instructions 492system.cpu.iew.iewExecLoadInsts 100518036 # Number of load instructions executed 493system.cpu.iew.iewExecSquashedInsts 2404335 # Number of squashed instructions skipped in execute |
| 495system.cpu.iew.exec_swp 0 # number of swp insts executed 496system.cpu.iew.exec_nop 0 # number of nop insts executed | 494system.cpu.iew.exec_swp 0 # number of swp insts executed 495system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 497system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed 498system.cpu.iew.exec_branches 32185799 # Number of branches executed 499system.cpu.iew.exec_stores 34371814 # Number of stores executed 500system.cpu.iew.exec_rate 2.398114 # Inst execution rate 501system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit 502system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back 503system.cpu.iew.wb_producers 238446717 # num instructions producing a value 504system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value 505system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle 506system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back 507system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit | 496system.cpu.iew.exec_refs 134824639 # number of memory reference insts executed 497system.cpu.iew.exec_branches 32104448 # Number of branches executed 498system.cpu.iew.exec_stores 34306603 # Number of stores executed 499system.cpu.iew.exec_rate 2.405762 # Inst execution rate 500system.cpu.iew.wb_sent 314286106 # cumulative count of insts sent to commit 501system.cpu.iew.wb_count 313652879 # cumulative count of insts written-back 502system.cpu.iew.wb_producers 237682188 # num instructions producing a value 503system.cpu.iew.wb_consumers 343423954 # num instructions consuming a value 504system.cpu.iew.wb_rate 2.392328 # insts written-back per cycle 505system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back 506system.cpu.commit.commitSquashedInsts 65797430 # The number of squashed insts skipped by commit |
| 508system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards | 507system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards |
| 509system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted 510system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle | 508system.cpu.commit.branchMispredicts 1399141 # The number of times a branch was mispredicted 509system.cpu.commit.committed_per_cycle::samples 121633848 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::mean 2.287130 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::stdev 3.051606 # Number of insts commited each cycle |
| 513system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 512system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 514system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::0 56556051 46.50% 46.50% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::1 16464352 13.54% 60.03% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::2 11233282 9.24% 69.27% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::3 8748892 7.19% 76.46% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::4 2045691 1.68% 78.14% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::5 1756798 1.44% 79.59% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::6 927336 0.76% 80.35% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::7 727466 0.60% 80.95% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::8 23173980 19.05% 100.00% # Number of insts commited each cycle |
| 523system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 526system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle | 525system.cpu.commit.committed_per_cycle::total 121633848 # Number of insts commited each cycle |
| 527system.cpu.commit.committedInsts 157988547 # Number of instructions committed 528system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 529system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 530system.cpu.commit.refs 122219137 # Number of memory references committed 531system.cpu.commit.loads 90779385 # Number of loads committed 532system.cpu.commit.membars 0 # Number of memory barriers committed 533system.cpu.commit.branches 29309705 # Number of branches committed 534system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 567system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 568system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction | 526system.cpu.commit.committedInsts 157988547 # Number of instructions committed 527system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 528system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 529system.cpu.commit.refs 122219137 # Number of memory references committed 530system.cpu.commit.loads 90779385 # Number of loads committed 531system.cpu.commit.membars 0 # Number of memory barriers committed 532system.cpu.commit.branches 29309705 # Number of branches committed 533system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 563system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 566system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 567system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 568system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction |
| 572system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached 573system.cpu.rob.rob_reads 445462066 # The number of ROB reads 574system.cpu.rob.rob_writes 702797421 # The number of ROB writes 575system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself 576system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling | 571system.cpu.commit.bw_lim_events 23173980 # number cycles where commit BW limit reached 572system.cpu.rob.rob_reads 442449762 # The number of ROB reads 573system.cpu.rob.rob_writes 697455131 # The number of ROB writes 574system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself 575system.cpu.idleCycles 67515 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 577system.cpu.committedInsts 157988547 # Number of Instructions Simulated 578system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated | 576system.cpu.committedInsts 157988547 # Number of Instructions Simulated 577system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated |
| 579system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads 581system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle 582system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads 583system.cpu.int_regfile_reads 504041942 # number of integer regfile reads 584system.cpu.int_regfile_writes 248656420 # number of integer regfile writes 585system.cpu.fp_regfile_reads 4180 # number of floating regfile reads 586system.cpu.fp_regfile_writes 782 # number of floating regfile writes 587system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads 588system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes 589system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads | 578system.cpu.cpi 0.829856 # CPI: Cycles Per Instruction 579system.cpu.cpi_total 0.829856 # CPI: Total CPI of All Threads 580system.cpu.ipc 1.205028 # IPC: Instructions Per Cycle 581system.cpu.ipc_total 1.205028 # IPC: Total IPC of All Threads 582system.cpu.int_regfile_reads 502814986 # number of integer regfile reads 583system.cpu.int_regfile_writes 247784196 # number of integer regfile writes 584system.cpu.fp_regfile_reads 4396 # number of floating regfile reads 585system.cpu.fp_regfile_writes 732 # number of floating regfile writes 586system.cpu.cc_regfile_reads 109093589 # number of cc regfile reads 587system.cpu.cc_regfile_writes 65488596 # number of cc regfile writes 588system.cpu.misc_regfile_reads 201890594 # number of misc regfile reads |
| 590system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 589system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.tags.replacements 2073508 # number of replacements 593system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use 594system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. 595system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. 596system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. 597system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor 599system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy 600system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy | 590system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 591system.cpu.dcache.tags.replacements 2073601 # number of replacements 592system.cpu.dcache.tags.tagsinuse 4068.108072 # Cycle average of tags in use 593system.cpu.dcache.tags.total_refs 71473739 # Total number of references to valid blocks. 594system.cpu.dcache.tags.sampled_refs 2077697 # Sample count of references to valid blocks. 595system.cpu.dcache.tags.avg_refs 34.400463 # Average number of references to valid blocks. 596system.cpu.dcache.tags.warmup_cycle 21041764500 # Cycle when the warmup percentage was hit. 597system.cpu.dcache.tags.occ_blocks::cpu.data 4068.108072 # Average occupied blocks per requestor 598system.cpu.dcache.tags.occ_percent::cpu.data 0.993190 # Average percentage of cache occupancy 599system.cpu.dcache.tags.occ_percent::total 0.993190 # Average percentage of cache occupancy |
| 601system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 600system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 602system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id 603system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id 604system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id | 601system.cpu.dcache.tags.age_task_id_blocks_1024::0 507 # Occupied blocks per task id 602system.cpu.dcache.tags.age_task_id_blocks_1024::1 3433 # Occupied blocks per task id 603system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id |
| 605system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 604system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 606system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses 607system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses 608system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 609system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits 610system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits 611system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits 612system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits 613system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits 614system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits 615system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits 616system.cpu.dcache.overall_hits::total 71894591 # number of overall hits 617system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses 618system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses 619system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses 620system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses 621system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses 622system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses 623system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses 624system.cpu.dcache.overall_misses::total 2787704 # number of overall misses 625system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles 626system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles 627system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles 628system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles 629system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles 630system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles 631system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles 632system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles 633system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) | 605system.cpu.dcache.tags.tag_accesses 150601371 # Number of tag accesses 606system.cpu.dcache.tags.data_accesses 150601371 # Number of data accesses 607system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 608system.cpu.dcache.ReadReq_hits::cpu.data 40127755 # number of ReadReq hits 609system.cpu.dcache.ReadReq_hits::total 40127755 # number of ReadReq hits 610system.cpu.dcache.WriteReq_hits::cpu.data 31345984 # number of WriteReq hits 611system.cpu.dcache.WriteReq_hits::total 31345984 # number of WriteReq hits 612system.cpu.dcache.demand_hits::cpu.data 71473739 # number of demand (read+write) hits 613system.cpu.dcache.demand_hits::total 71473739 # number of demand (read+write) hits 614system.cpu.dcache.overall_hits::cpu.data 71473739 # number of overall hits 615system.cpu.dcache.overall_hits::total 71473739 # number of overall hits 616system.cpu.dcache.ReadReq_misses::cpu.data 2694330 # number of ReadReq misses 617system.cpu.dcache.ReadReq_misses::total 2694330 # number of ReadReq misses 618system.cpu.dcache.WriteReq_misses::cpu.data 93768 # number of WriteReq misses 619system.cpu.dcache.WriteReq_misses::total 93768 # number of WriteReq misses 620system.cpu.dcache.demand_misses::cpu.data 2788098 # number of demand (read+write) misses 621system.cpu.dcache.demand_misses::total 2788098 # number of demand (read+write) misses 622system.cpu.dcache.overall_misses::cpu.data 2788098 # number of overall misses 623system.cpu.dcache.overall_misses::total 2788098 # number of overall misses 624system.cpu.dcache.ReadReq_miss_latency::cpu.data 32345718500 # number of ReadReq miss cycles 625system.cpu.dcache.ReadReq_miss_latency::total 32345718500 # number of ReadReq miss cycles 626system.cpu.dcache.WriteReq_miss_latency::cpu.data 2982305493 # number of WriteReq miss cycles 627system.cpu.dcache.WriteReq_miss_latency::total 2982305493 # number of WriteReq miss cycles 628system.cpu.dcache.demand_miss_latency::cpu.data 35328023993 # number of demand (read+write) miss cycles 629system.cpu.dcache.demand_miss_latency::total 35328023993 # number of demand (read+write) miss cycles 630system.cpu.dcache.overall_miss_latency::cpu.data 35328023993 # number of overall miss cycles 631system.cpu.dcache.overall_miss_latency::total 35328023993 # number of overall miss cycles 632system.cpu.dcache.ReadReq_accesses::cpu.data 42822085 # number of ReadReq accesses(hits+misses) 633system.cpu.dcache.ReadReq_accesses::total 42822085 # number of ReadReq accesses(hits+misses) |
| 635system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 634system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 637system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses 638system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses 639system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses 640system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses 641system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses 642system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses 643system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses 644system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses 645system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses 646system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses 647system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses 648system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses 649system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency 650system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency 651system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency 652system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency 653system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency 654system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency 655system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency 656system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency 657system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked 658system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked 659system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked | 636system.cpu.dcache.demand_accesses::cpu.data 74261837 # number of demand (read+write) accesses 637system.cpu.dcache.demand_accesses::total 74261837 # number of demand (read+write) accesses 638system.cpu.dcache.overall_accesses::cpu.data 74261837 # number of overall (read+write) accesses 639system.cpu.dcache.overall_accesses::total 74261837 # number of overall (read+write) accesses 640system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062919 # miss rate for ReadReq accesses 641system.cpu.dcache.ReadReq_miss_rate::total 0.062919 # miss rate for ReadReq accesses 642system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002982 # miss rate for WriteReq accesses 643system.cpu.dcache.WriteReq_miss_rate::total 0.002982 # miss rate for WriteReq accesses 644system.cpu.dcache.demand_miss_rate::cpu.data 0.037544 # miss rate for demand accesses 645system.cpu.dcache.demand_miss_rate::total 0.037544 # miss rate for demand accesses 646system.cpu.dcache.overall_miss_rate::cpu.data 0.037544 # miss rate for overall accesses 647system.cpu.dcache.overall_miss_rate::total 0.037544 # miss rate for overall accesses 648system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464 # average ReadReq miss latency 649system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464 # average ReadReq miss latency 650system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003 # average WriteReq miss latency 651system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003 # average WriteReq miss latency 652system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency 653system.cpu.dcache.demand_avg_miss_latency::total 12671.012279 # average overall miss latency 654system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency 655system.cpu.dcache.overall_avg_miss_latency::total 12671.012279 # average overall miss latency 656system.cpu.dcache.blocked_cycles::no_mshrs 218790 # number of cycles access was blocked 657system.cpu.dcache.blocked_cycles::no_targets 393 # number of cycles access was blocked 658system.cpu.dcache.blocked::no_mshrs 43059 # number of cycles access was blocked |
| 660system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked | 659system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked |
| 661system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked 662system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked 663system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks 664system.cpu.dcache.writebacks::total 2066969 # number of writebacks 665system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits 666system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits 667system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 668system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 669system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits 670system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits 671system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits 672system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits 673system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses 674system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses 675system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses 676system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses 677system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses 678system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses 679system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses 680system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses 681system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles 682system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles 683system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles 684system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles 688system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles 689system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses 690system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses 691system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses 692system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses 693system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses 694system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses 695system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses 696system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses 697system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency 698system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency 699system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency 700system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency 701system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 702system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency 703system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 704system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency 705system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 706system.cpu.icache.tags.replacements 93 # number of replacements 707system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use 708system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. 709system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. 710system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. | 660system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.081168 # average number of cycles each access was blocked 661system.cpu.dcache.avg_blocked_cycles::no_targets 98.250000 # average number of cycles each access was blocked 662system.cpu.dcache.writebacks::writebacks 2067196 # number of writebacks 663system.cpu.dcache.writebacks::total 2067196 # number of writebacks 664system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698496 # number of ReadReq MSHR hits 665system.cpu.dcache.ReadReq_mshr_hits::total 698496 # number of ReadReq MSHR hits 666system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11905 # number of WriteReq MSHR hits 667system.cpu.dcache.WriteReq_mshr_hits::total 11905 # number of WriteReq MSHR hits 668system.cpu.dcache.demand_mshr_hits::cpu.data 710401 # number of demand (read+write) MSHR hits 669system.cpu.dcache.demand_mshr_hits::total 710401 # number of demand (read+write) MSHR hits 670system.cpu.dcache.overall_mshr_hits::cpu.data 710401 # number of overall MSHR hits 671system.cpu.dcache.overall_mshr_hits::total 710401 # number of overall MSHR hits 672system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995834 # number of ReadReq MSHR misses 673system.cpu.dcache.ReadReq_mshr_misses::total 1995834 # number of ReadReq MSHR misses 674system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81863 # number of WriteReq MSHR misses 675system.cpu.dcache.WriteReq_mshr_misses::total 81863 # number of WriteReq MSHR misses 676system.cpu.dcache.demand_mshr_misses::cpu.data 2077697 # number of demand (read+write) MSHR misses 677system.cpu.dcache.demand_mshr_misses::total 2077697 # number of demand (read+write) MSHR misses 678system.cpu.dcache.overall_mshr_misses::cpu.data 2077697 # number of overall MSHR misses 679system.cpu.dcache.overall_mshr_misses::total 2077697 # number of overall MSHR misses 680system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24223051500 # number of ReadReq MSHR miss cycles 681system.cpu.dcache.ReadReq_mshr_miss_latency::total 24223051500 # number of ReadReq MSHR miss cycles 682system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2825101993 # number of WriteReq MSHR miss cycles 683system.cpu.dcache.WriteReq_mshr_miss_latency::total 2825101993 # number of WriteReq MSHR miss cycles 684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27048153493 # number of demand (read+write) MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::total 27048153493 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27048153493 # number of overall MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::total 27048153493 # number of overall MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046608 # mshr miss rate for ReadReq accesses 689system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046608 # mshr miss rate for ReadReq accesses 690system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses 691system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses 692system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for demand accesses 693system.cpu.dcache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses 694system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for overall accesses 695system.cpu.dcache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses 696system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718 # average ReadReq mshr miss latency 697system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718 # average ReadReq mshr miss latency 698system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482 # average WriteReq mshr miss latency 699system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482 # average WriteReq mshr miss latency 700system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency 701system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency 702system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency 703system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency 704system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 705system.cpu.icache.tags.replacements 91 # number of replacements 706system.cpu.icache.tags.tagsinuse 875.979350 # Cycle average of tags in use 707system.cpu.icache.tags.total_refs 29741086 # Total number of references to valid blocks. 708system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. 709system.cpu.icache.tags.avg_refs 26625.860340 # Average number of references to valid blocks. |
| 711system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 710system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 712system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor 713system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy 714system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy 715system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id 716system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 717system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 718system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 719system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id 720system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id 721system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id 722system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses 723system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses 724system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 725system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits 726system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits 727system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits 728system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits 729system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits 730system.cpu.icache.overall_hits::total 29996478 # number of overall hits 731system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses 732system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses 733system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses 734system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses 735system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses 736system.cpu.icache.overall_misses::total 1445 # number of overall misses 737system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles 738system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles 739system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles 740system.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles 741system.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles 742system.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles 743system.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) 744system.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) 745system.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses 746system.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses 747system.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses 748system.cpu.icache.overall_accesses::total 29997923 # number of overall (read+write) accesses 749system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 750system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 751system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 752system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 753system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 754system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses 755system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388 # average ReadReq miss latency 756system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388 # average ReadReq miss latency 757system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency 758system.cpu.icache.demand_avg_miss_latency::total 73417.992388 # average overall miss latency 759system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency 760system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency 761system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked | 711system.cpu.icache.tags.occ_blocks::cpu.inst 875.979350 # Average occupied blocks per requestor 712system.cpu.icache.tags.occ_percent::cpu.inst 0.427724 # Average percentage of cache occupancy 713system.cpu.icache.tags.occ_percent::total 0.427724 # Average percentage of cache occupancy 714system.cpu.icache.tags.occ_task_id_blocks::1024 1026 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 716system.cpu.icache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 717system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 718system.cpu.icache.tags.age_task_id_blocks_1024::4 914 # Occupied blocks per task id 719system.cpu.icache.tags.occ_task_id_percent::1024 0.500977 # Percentage of cache occupancy per task id 720system.cpu.icache.tags.tag_accesses 59486235 # Number of tag accesses 721system.cpu.icache.tags.data_accesses 59486235 # Number of data accesses 722system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 723system.cpu.icache.ReadReq_hits::cpu.inst 29741086 # number of ReadReq hits 724system.cpu.icache.ReadReq_hits::total 29741086 # number of ReadReq hits 725system.cpu.icache.demand_hits::cpu.inst 29741086 # number of demand (read+write) hits 726system.cpu.icache.demand_hits::total 29741086 # number of demand (read+write) hits 727system.cpu.icache.overall_hits::cpu.inst 29741086 # number of overall hits 728system.cpu.icache.overall_hits::total 29741086 # number of overall hits 729system.cpu.icache.ReadReq_misses::cpu.inst 1473 # number of ReadReq misses 730system.cpu.icache.ReadReq_misses::total 1473 # number of ReadReq misses 731system.cpu.icache.demand_misses::cpu.inst 1473 # number of demand (read+write) misses 732system.cpu.icache.demand_misses::total 1473 # number of demand (read+write) misses 733system.cpu.icache.overall_misses::cpu.inst 1473 # number of overall misses 734system.cpu.icache.overall_misses::total 1473 # number of overall misses 735system.cpu.icache.ReadReq_miss_latency::cpu.inst 110309999 # number of ReadReq miss cycles 736system.cpu.icache.ReadReq_miss_latency::total 110309999 # number of ReadReq miss cycles 737system.cpu.icache.demand_miss_latency::cpu.inst 110309999 # number of demand (read+write) miss cycles 738system.cpu.icache.demand_miss_latency::total 110309999 # number of demand (read+write) miss cycles 739system.cpu.icache.overall_miss_latency::cpu.inst 110309999 # number of overall miss cycles 740system.cpu.icache.overall_miss_latency::total 110309999 # number of overall miss cycles 741system.cpu.icache.ReadReq_accesses::cpu.inst 29742559 # number of ReadReq accesses(hits+misses) 742system.cpu.icache.ReadReq_accesses::total 29742559 # number of ReadReq accesses(hits+misses) 743system.cpu.icache.demand_accesses::cpu.inst 29742559 # number of demand (read+write) accesses 744system.cpu.icache.demand_accesses::total 29742559 # number of demand (read+write) accesses 745system.cpu.icache.overall_accesses::cpu.inst 29742559 # number of overall (read+write) accesses 746system.cpu.icache.overall_accesses::total 29742559 # number of overall (read+write) accesses 747system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses 748system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses 749system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses 750system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses 751system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses 752system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses 753system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74887.983028 # average ReadReq miss latency 754system.cpu.icache.ReadReq_avg_miss_latency::total 74887.983028 # average ReadReq miss latency 755system.cpu.icache.demand_avg_miss_latency::cpu.inst 74887.983028 # average overall miss latency 756system.cpu.icache.demand_avg_miss_latency::total 74887.983028 # average overall miss latency 757system.cpu.icache.overall_avg_miss_latency::cpu.inst 74887.983028 # average overall miss latency 758system.cpu.icache.overall_avg_miss_latency::total 74887.983028 # average overall miss latency 759system.cpu.icache.blocked_cycles::no_mshrs 1013 # number of cycles access was blocked |
| 762system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 760system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 763system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked | 761system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked |
| 764system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 762system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 765system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked | 763system.cpu.icache.avg_blocked_cycles::no_mshrs 77.923077 # average number of cycles each access was blocked |
| 766system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 764system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 767system.cpu.icache.writebacks::writebacks 93 # number of writebacks 768system.cpu.icache.writebacks::total 93 # number of writebacks 769system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits 770system.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits 771system.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits 772system.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits 773system.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits 774system.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits 775system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1113 # number of ReadReq MSHR misses 776system.cpu.icache.ReadReq_mshr_misses::total 1113 # number of ReadReq MSHR misses 777system.cpu.icache.demand_mshr_misses::cpu.inst 1113 # number of demand (read+write) MSHR misses 778system.cpu.icache.demand_mshr_misses::total 1113 # number of demand (read+write) MSHR misses 779system.cpu.icache.overall_mshr_misses::cpu.inst 1113 # number of overall MSHR misses 780system.cpu.icache.overall_mshr_misses::total 1113 # number of overall MSHR misses 781system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 84684499 # number of ReadReq MSHR miss cycles 782system.cpu.icache.ReadReq_mshr_miss_latency::total 84684499 # number of ReadReq MSHR miss cycles 783system.cpu.icache.demand_mshr_miss_latency::cpu.inst 84684499 # number of demand (read+write) MSHR miss cycles 784system.cpu.icache.demand_mshr_miss_latency::total 84684499 # number of demand (read+write) MSHR miss cycles 785system.cpu.icache.overall_mshr_miss_latency::cpu.inst 84684499 # number of overall MSHR miss cycles 786system.cpu.icache.overall_mshr_miss_latency::total 84684499 # number of overall MSHR miss cycles 787system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 788system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 789system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 790system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 791system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 792system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 793system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency 794system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency 795system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 796system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency 797system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 798system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency 799system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 800system.cpu.l2cache.tags.replacements 650 # number of replacements 801system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use 802system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. 803system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. 804system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. | 765system.cpu.icache.writebacks::writebacks 91 # number of writebacks 766system.cpu.icache.writebacks::total 91 # number of writebacks 767system.cpu.icache.ReadReq_mshr_hits::cpu.inst 356 # number of ReadReq MSHR hits 768system.cpu.icache.ReadReq_mshr_hits::total 356 # number of ReadReq MSHR hits 769system.cpu.icache.demand_mshr_hits::cpu.inst 356 # number of demand (read+write) MSHR hits 770system.cpu.icache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits 771system.cpu.icache.overall_mshr_hits::cpu.inst 356 # number of overall MSHR hits 772system.cpu.icache.overall_mshr_hits::total 356 # number of overall MSHR hits 773system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1117 # number of ReadReq MSHR misses 774system.cpu.icache.ReadReq_mshr_misses::total 1117 # number of ReadReq MSHR misses 775system.cpu.icache.demand_mshr_misses::cpu.inst 1117 # number of demand (read+write) MSHR misses 776system.cpu.icache.demand_mshr_misses::total 1117 # number of demand (read+write) MSHR misses 777system.cpu.icache.overall_mshr_misses::cpu.inst 1117 # number of overall MSHR misses 778system.cpu.icache.overall_mshr_misses::total 1117 # number of overall MSHR misses 779system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86959999 # number of ReadReq MSHR miss cycles 780system.cpu.icache.ReadReq_mshr_miss_latency::total 86959999 # number of ReadReq MSHR miss cycles 781system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86959999 # number of demand (read+write) MSHR miss cycles 782system.cpu.icache.demand_mshr_miss_latency::total 86959999 # number of demand (read+write) MSHR miss cycles 783system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86959999 # number of overall MSHR miss cycles 784system.cpu.icache.overall_mshr_miss_latency::total 86959999 # number of overall MSHR miss cycles 785system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for ReadReq accesses 786system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000038 # mshr miss rate for ReadReq accesses 787system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for demand accesses 788system.cpu.icache.demand_mshr_miss_rate::total 0.000038 # mshr miss rate for demand accesses 789system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for overall accesses 790system.cpu.icache.overall_mshr_miss_rate::total 0.000038 # mshr miss rate for overall accesses 791system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77851.386750 # average ReadReq mshr miss latency 792system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77851.386750 # average ReadReq mshr miss latency 793system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77851.386750 # average overall mshr miss latency 794system.cpu.icache.demand_avg_mshr_miss_latency::total 77851.386750 # average overall mshr miss latency 795system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77851.386750 # average overall mshr miss latency 796system.cpu.icache.overall_avg_mshr_miss_latency::total 77851.386750 # average overall mshr miss latency 797system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 798system.cpu.l2cache.tags.replacements 663 # number of replacements 799system.cpu.l2cache.tags.tagsinuse 21665.639104 # Cycle average of tags in use 800system.cpu.l2cache.tags.total_refs 4121840 # Total number of references to valid blocks. 801system.cpu.l2cache.tags.sampled_refs 30651 # Sample count of references to valid blocks. 802system.cpu.l2cache.tags.avg_refs 134.476526 # Average number of references to valid blocks. |
| 805system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 803system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 806system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor 807system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor 808system.cpu.l2cache.tags.occ_blocks::cpu.data 275.118635 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_percent::writebacks 0.598769 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021693 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::cpu.data 0.008396 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::total 0.628858 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_task_id_blocks::1024 29972 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id 819system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id 820system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses 821system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses 822system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 823system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits 824system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits 825system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits 826system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits 827system.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits 828system.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits 829system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits 830system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits 831system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995161 # number of ReadSharedReq hits 832system.cpu.l2cache.ReadSharedReq_hits::total 1995161 # number of ReadSharedReq hits 833system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 834system.cpu.l2cache.demand_hits::cpu.data 2048067 # number of demand (read+write) hits 835system.cpu.l2cache.demand_hits::total 2048095 # number of demand (read+write) hits 836system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 837system.cpu.l2cache.overall_hits::cpu.data 2048067 # number of overall hits 838system.cpu.l2cache.overall_hits::total 2048095 # number of overall hits 839system.cpu.l2cache.ReadExReq_misses::cpu.data 28982 # number of ReadExReq misses 840system.cpu.l2cache.ReadExReq_misses::total 28982 # number of ReadExReq misses 841system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1085 # number of ReadCleanReq misses 842system.cpu.l2cache.ReadCleanReq_misses::total 1085 # number of ReadCleanReq misses 843system.cpu.l2cache.ReadSharedReq_misses::cpu.data 555 # number of ReadSharedReq misses 844system.cpu.l2cache.ReadSharedReq_misses::total 555 # number of ReadSharedReq misses 845system.cpu.l2cache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses 846system.cpu.l2cache.demand_misses::cpu.data 29537 # number of demand (read+write) misses 847system.cpu.l2cache.demand_misses::total 30622 # number of demand (read+write) misses 848system.cpu.l2cache.overall_misses::cpu.inst 1085 # number of overall misses 849system.cpu.l2cache.overall_misses::cpu.data 29537 # number of overall misses 850system.cpu.l2cache.overall_misses::total 30622 # number of overall misses 851system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2117059500 # number of ReadExReq miss cycles 852system.cpu.l2cache.ReadExReq_miss_latency::total 2117059500 # number of ReadExReq miss cycles 853system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 82707500 # number of ReadCleanReq miss cycles 854system.cpu.l2cache.ReadCleanReq_miss_latency::total 82707500 # number of ReadCleanReq miss cycles 855system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43407000 # number of ReadSharedReq miss cycles 856system.cpu.l2cache.ReadSharedReq_miss_latency::total 43407000 # number of ReadSharedReq miss cycles 857system.cpu.l2cache.demand_miss_latency::cpu.inst 82707500 # number of demand (read+write) miss cycles 858system.cpu.l2cache.demand_miss_latency::cpu.data 2160466500 # number of demand (read+write) miss cycles 859system.cpu.l2cache.demand_miss_latency::total 2243174000 # number of demand (read+write) miss cycles 860system.cpu.l2cache.overall_miss_latency::cpu.inst 82707500 # number of overall miss cycles 861system.cpu.l2cache.overall_miss_latency::cpu.data 2160466500 # number of overall miss cycles 862system.cpu.l2cache.overall_miss_latency::total 2243174000 # number of overall miss cycles 863system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066969 # number of WritebackDirty accesses(hits+misses) 864system.cpu.l2cache.WritebackDirty_accesses::total 2066969 # number of WritebackDirty accesses(hits+misses) 865system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) 866system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) 867system.cpu.l2cache.ReadExReq_accesses::cpu.data 81888 # number of ReadExReq accesses(hits+misses) 868system.cpu.l2cache.ReadExReq_accesses::total 81888 # number of ReadExReq accesses(hits+misses) 869system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1113 # number of ReadCleanReq accesses(hits+misses) 870system.cpu.l2cache.ReadCleanReq_accesses::total 1113 # number of ReadCleanReq accesses(hits+misses) 871system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995716 # number of ReadSharedReq accesses(hits+misses) 872system.cpu.l2cache.ReadSharedReq_accesses::total 1995716 # number of ReadSharedReq accesses(hits+misses) 873system.cpu.l2cache.demand_accesses::cpu.inst 1113 # number of demand (read+write) accesses 874system.cpu.l2cache.demand_accesses::cpu.data 2077604 # number of demand (read+write) accesses 875system.cpu.l2cache.demand_accesses::total 2078717 # number of demand (read+write) accesses 876system.cpu.l2cache.overall_accesses::cpu.inst 1113 # number of overall (read+write) accesses 877system.cpu.l2cache.overall_accesses::cpu.data 2077604 # number of overall (read+write) accesses 878system.cpu.l2cache.overall_accesses::total 2078717 # number of overall (read+write) accesses 879system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353922 # miss rate for ReadExReq accesses 880system.cpu.l2cache.ReadExReq_miss_rate::total 0.353922 # miss rate for ReadExReq accesses 881system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974843 # miss rate for ReadCleanReq accesses 882system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974843 # miss rate for ReadCleanReq accesses 883system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000278 # miss rate for ReadSharedReq accesses 884system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000278 # miss rate for ReadSharedReq accesses 885system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974843 # miss rate for demand accesses 886system.cpu.l2cache.demand_miss_rate::cpu.data 0.014217 # miss rate for demand accesses 887system.cpu.l2cache.demand_miss_rate::total 0.014731 # miss rate for demand accesses 888system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974843 # miss rate for overall accesses 889system.cpu.l2cache.overall_miss_rate::cpu.data 0.014217 # miss rate for overall accesses 890system.cpu.l2cache.overall_miss_rate::total 0.014731 # miss rate for overall accesses 891system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73047.391484 # average ReadExReq miss latency 892system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73047.391484 # average ReadExReq miss latency 893system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76228.110599 # average ReadCleanReq miss latency 894system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599 # average ReadCleanReq miss latency 895system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811 # average ReadSharedReq miss latency 896system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811 # average ReadSharedReq miss latency 897system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency 898system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency 899system.cpu.l2cache.demand_avg_miss_latency::total 73253.673829 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency 901system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency 902system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency | 804system.cpu.l2cache.tags.occ_blocks::writebacks 2.943755 # Average occupied blocks per requestor 805system.cpu.l2cache.tags.occ_blocks::cpu.inst 711.855926 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_blocks::cpu.data 20950.839423 # Average occupied blocks per requestor 807system.cpu.l2cache.tags.occ_percent::writebacks 0.000090 # Average percentage of cache occupancy 808system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021724 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::cpu.data 0.639369 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::total 0.661183 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_task_id_blocks::1024 29988 # Occupied blocks per task id 812system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 813system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29650 # Occupied blocks per task id 817system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915161 # Percentage of cache occupancy per task id 818system.cpu.l2cache.tags.tag_accesses 33250579 # Number of tag accesses 819system.cpu.l2cache.tags.data_accesses 33250579 # Number of data accesses 820system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 821system.cpu.l2cache.WritebackDirty_hits::writebacks 2067196 # number of WritebackDirty hits 822system.cpu.l2cache.WritebackDirty_hits::total 2067196 # number of WritebackDirty hits 823system.cpu.l2cache.WritebackClean_hits::writebacks 91 # number of WritebackClean hits 824system.cpu.l2cache.WritebackClean_hits::total 91 # number of WritebackClean hits 825system.cpu.l2cache.ReadExReq_hits::cpu.data 52900 # number of ReadExReq hits 826system.cpu.l2cache.ReadExReq_hits::total 52900 # number of ReadExReq hits 827system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 29 # number of ReadCleanReq hits 828system.cpu.l2cache.ReadCleanReq_hits::total 29 # number of ReadCleanReq hits 829system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995251 # number of ReadSharedReq hits 830system.cpu.l2cache.ReadSharedReq_hits::total 1995251 # number of ReadSharedReq hits 831system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits 832system.cpu.l2cache.demand_hits::cpu.data 2048151 # number of demand (read+write) hits 833system.cpu.l2cache.demand_hits::total 2048180 # number of demand (read+write) hits 834system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits 835system.cpu.l2cache.overall_hits::cpu.data 2048151 # number of overall hits 836system.cpu.l2cache.overall_hits::total 2048180 # number of overall hits 837system.cpu.l2cache.ReadExReq_misses::cpu.data 28989 # number of ReadExReq misses 838system.cpu.l2cache.ReadExReq_misses::total 28989 # number of ReadExReq misses 839system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1088 # number of ReadCleanReq misses 840system.cpu.l2cache.ReadCleanReq_misses::total 1088 # number of ReadCleanReq misses 841system.cpu.l2cache.ReadSharedReq_misses::cpu.data 557 # number of ReadSharedReq misses 842system.cpu.l2cache.ReadSharedReq_misses::total 557 # number of ReadSharedReq misses 843system.cpu.l2cache.demand_misses::cpu.inst 1088 # number of demand (read+write) misses 844system.cpu.l2cache.demand_misses::cpu.data 29546 # number of demand (read+write) misses 845system.cpu.l2cache.demand_misses::total 30634 # number of demand (read+write) misses 846system.cpu.l2cache.overall_misses::cpu.inst 1088 # number of overall misses 847system.cpu.l2cache.overall_misses::cpu.data 29546 # number of overall misses 848system.cpu.l2cache.overall_misses::total 30634 # number of overall misses 849system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2146396500 # number of ReadExReq miss cycles 850system.cpu.l2cache.ReadExReq_miss_latency::total 2146396500 # number of ReadExReq miss cycles 851system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84962000 # number of ReadCleanReq miss cycles 852system.cpu.l2cache.ReadCleanReq_miss_latency::total 84962000 # number of ReadCleanReq miss cycles 853system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42143000 # number of ReadSharedReq miss cycles 854system.cpu.l2cache.ReadSharedReq_miss_latency::total 42143000 # number of ReadSharedReq miss cycles 855system.cpu.l2cache.demand_miss_latency::cpu.inst 84962000 # number of demand (read+write) miss cycles 856system.cpu.l2cache.demand_miss_latency::cpu.data 2188539500 # number of demand (read+write) miss cycles 857system.cpu.l2cache.demand_miss_latency::total 2273501500 # number of demand (read+write) miss cycles 858system.cpu.l2cache.overall_miss_latency::cpu.inst 84962000 # number of overall miss cycles 859system.cpu.l2cache.overall_miss_latency::cpu.data 2188539500 # number of overall miss cycles 860system.cpu.l2cache.overall_miss_latency::total 2273501500 # number of overall miss cycles 861system.cpu.l2cache.WritebackDirty_accesses::writebacks 2067196 # number of WritebackDirty accesses(hits+misses) 862system.cpu.l2cache.WritebackDirty_accesses::total 2067196 # number of WritebackDirty accesses(hits+misses) 863system.cpu.l2cache.WritebackClean_accesses::writebacks 91 # number of WritebackClean accesses(hits+misses) 864system.cpu.l2cache.WritebackClean_accesses::total 91 # number of WritebackClean accesses(hits+misses) 865system.cpu.l2cache.ReadExReq_accesses::cpu.data 81889 # number of ReadExReq accesses(hits+misses) 866system.cpu.l2cache.ReadExReq_accesses::total 81889 # number of ReadExReq accesses(hits+misses) 867system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1117 # number of ReadCleanReq accesses(hits+misses) 868system.cpu.l2cache.ReadCleanReq_accesses::total 1117 # number of ReadCleanReq accesses(hits+misses) 869system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995808 # number of ReadSharedReq accesses(hits+misses) 870system.cpu.l2cache.ReadSharedReq_accesses::total 1995808 # number of ReadSharedReq accesses(hits+misses) 871system.cpu.l2cache.demand_accesses::cpu.inst 1117 # number of demand (read+write) accesses 872system.cpu.l2cache.demand_accesses::cpu.data 2077697 # number of demand (read+write) accesses 873system.cpu.l2cache.demand_accesses::total 2078814 # number of demand (read+write) accesses 874system.cpu.l2cache.overall_accesses::cpu.inst 1117 # number of overall (read+write) accesses 875system.cpu.l2cache.overall_accesses::cpu.data 2077697 # number of overall (read+write) accesses 876system.cpu.l2cache.overall_accesses::total 2078814 # number of overall (read+write) accesses 877system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.354004 # miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_miss_rate::total 0.354004 # miss rate for ReadExReq accesses 879system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974038 # miss rate for ReadCleanReq accesses 880system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974038 # miss rate for ReadCleanReq accesses 881system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000279 # miss rate for ReadSharedReq accesses 882system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000279 # miss rate for ReadSharedReq accesses 883system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974038 # miss rate for demand accesses 884system.cpu.l2cache.demand_miss_rate::cpu.data 0.014221 # miss rate for demand accesses 885system.cpu.l2cache.demand_miss_rate::total 0.014736 # miss rate for demand accesses 886system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974038 # miss rate for overall accesses 887system.cpu.l2cache.overall_miss_rate::cpu.data 0.014221 # miss rate for overall accesses 888system.cpu.l2cache.overall_miss_rate::total 0.014736 # miss rate for overall accesses 889system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74041.757218 # average ReadExReq miss latency 890system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74041.757218 # average ReadExReq miss latency 891system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78090.073529 # average ReadCleanReq miss latency 892system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529 # average ReadCleanReq miss latency 893system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226 # average ReadSharedReq miss latency 894system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226 # average ReadSharedReq miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559 # average overall miss latency |
| 903system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 906system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 907system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 908system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 909system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks 910system.cpu.l2cache.writebacks::total 280 # number of writebacks | 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks 908system.cpu.l2cache.writebacks::total 280 # number of writebacks |
| 911system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses 912system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses 913system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses 914system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses 915system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses 916system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses 917system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # number of demand (read+write) MSHR misses 918system.cpu.l2cache.demand_mshr_misses::cpu.data 29537 # number of demand (read+write) MSHR misses 919system.cpu.l2cache.demand_mshr_misses::total 30622 # number of demand (read+write) MSHR misses 920system.cpu.l2cache.overall_mshr_misses::cpu.inst 1085 # number of overall MSHR misses 921system.cpu.l2cache.overall_mshr_misses::cpu.data 29537 # number of overall MSHR misses 922system.cpu.l2cache.overall_mshr_misses::total 30622 # number of overall MSHR misses 923system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827239500 # number of ReadExReq MSHR miss cycles 924system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827239500 # number of ReadExReq MSHR miss cycles 925system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71857500 # number of ReadCleanReq MSHR miss cycles 926system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71857500 # number of ReadCleanReq MSHR miss cycles 927system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 37857000 # number of ReadSharedReq MSHR miss cycles 928system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 37857000 # number of ReadSharedReq MSHR miss cycles 929system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71857500 # number of demand (read+write) MSHR miss cycles 930system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1865096500 # number of demand (read+write) MSHR miss cycles 931system.cpu.l2cache.demand_mshr_miss_latency::total 1936954000 # number of demand (read+write) MSHR miss cycles 932system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71857500 # number of overall MSHR miss cycles 933system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1865096500 # number of overall MSHR miss cycles 934system.cpu.l2cache.overall_mshr_miss_latency::total 1936954000 # number of overall MSHR miss cycles 935system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353922 # mshr miss rate for ReadExReq accesses 936system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353922 # mshr miss rate for ReadExReq accesses 937system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for ReadCleanReq accesses 938system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses 939system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses 940system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses 941system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses 942system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses 943system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses 944system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses 945system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses 946system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses 947system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency 948system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency 949system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency 950system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency 951system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency 952system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency 953system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 954system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency 956system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 957system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency 959system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. 960system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. 961system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 962system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. 963system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 909system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28989 # number of ReadExReq MSHR misses 910system.cpu.l2cache.ReadExReq_mshr_misses::total 28989 # number of ReadExReq MSHR misses 911system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1088 # number of ReadCleanReq MSHR misses 912system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1088 # number of ReadCleanReq MSHR misses 913system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 557 # number of ReadSharedReq MSHR misses 914system.cpu.l2cache.ReadSharedReq_mshr_misses::total 557 # number of ReadSharedReq MSHR misses 915system.cpu.l2cache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.demand_mshr_misses::cpu.data 29546 # number of demand (read+write) MSHR misses 917system.cpu.l2cache.demand_mshr_misses::total 30634 # number of demand (read+write) MSHR misses 918system.cpu.l2cache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses 919system.cpu.l2cache.overall_mshr_misses::cpu.data 29546 # number of overall MSHR misses 920system.cpu.l2cache.overall_mshr_misses::total 30634 # number of overall MSHR misses 921system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1856506500 # number of ReadExReq MSHR miss cycles 922system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1856506500 # number of ReadExReq MSHR miss cycles 923system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74082000 # number of ReadCleanReq MSHR miss cycles 924system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74082000 # number of ReadCleanReq MSHR miss cycles 925system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36573000 # number of ReadSharedReq MSHR miss cycles 926system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36573000 # number of ReadSharedReq MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74082000 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1893079500 # number of demand (read+write) MSHR miss cycles 929system.cpu.l2cache.demand_mshr_miss_latency::total 1967161500 # number of demand (read+write) MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74082000 # number of overall MSHR miss cycles 931system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1893079500 # number of overall MSHR miss cycles 932system.cpu.l2cache.overall_mshr_miss_latency::total 1967161500 # number of overall MSHR miss cycles 933system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354004 # mshr miss rate for ReadExReq accesses 934system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354004 # mshr miss rate for ReadExReq accesses 935system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for ReadCleanReq accesses 936system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974038 # mshr miss rate for ReadCleanReq accesses 937system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000279 # mshr miss rate for ReadSharedReq accesses 938system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadSharedReq accesses 939system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for demand accesses 940system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses 941system.cpu.l2cache.demand_mshr_miss_rate::total 0.014736 # mshr miss rate for demand accesses 942system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for overall accesses 943system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses 944system.cpu.l2cache.overall_mshr_miss_rate::total 0.014736 # mshr miss rate for overall accesses 945system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218 # average ReadExReq mshr miss latency 946system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218 # average ReadExReq mshr miss latency 947system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529 # average ReadCleanReq mshr miss latency 948system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529 # average ReadCleanReq mshr miss latency 949system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226 # average ReadSharedReq mshr miss latency 950system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226 # average ReadSharedReq mshr miss latency 951system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency 952system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency 953system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency 954system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency 955system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency 956system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency 957system.cpu.toL2Bus.snoop_filter.tot_requests 4152506 # Total number of requests made to the snoop filter. 958system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073696 # Number of requests hitting in the snoop filter with a single holder of the requested data. 959system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 960system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. 961system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 964system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 962system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 965system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 966system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution 967system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution 968system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution 969system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution 970system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution 971system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution 972system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution 973system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution 974system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) 975system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) 976system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) 977system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) 978system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) 979system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) 980system.cpu.toL2Bus.snoops 650 # Total snoops (count) | 963system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 964system.cpu.toL2Bus.trans_dist::ReadResp 1996925 # Transaction distribution 965system.cpu.toL2Bus.trans_dist::WritebackDirty 2067476 # Transaction distribution 966system.cpu.toL2Bus.trans_dist::WritebackClean 91 # Transaction distribution 967system.cpu.toL2Bus.trans_dist::CleanEvict 6788 # Transaction distribution 968system.cpu.toL2Bus.trans_dist::ReadExReq 81889 # Transaction distribution 969system.cpu.toL2Bus.trans_dist::ReadExResp 81889 # Transaction distribution 970system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution 971system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995808 # Transaction distribution 972system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2325 # Packet count per connected master and slave (bytes) 973system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228995 # Packet count per connected master and slave (bytes) 974system.cpu.toL2Bus.pkt_count::total 6231320 # Packet count per connected master and slave (bytes) 975system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77312 # Cumulative packet size per connected master and slave (bytes) 976system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265273152 # Cumulative packet size per connected master and slave (bytes) 977system.cpu.toL2Bus.pkt_size::total 265350464 # Cumulative packet size per connected master and slave (bytes) 978system.cpu.toL2Bus.snoops 663 # Total snoops (count) |
| 981system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) | 979system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) |
| 982system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram 984system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram | 980system.cpu.toL2Bus.snoop_fanout::samples 2079477 # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::mean 0.000168 # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::stdev 0.012972 # Request fanout histogram |
| 985system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 983system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 986system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram 987system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram | 984system.cpu.toL2Bus.snoop_fanout::0 2079127 99.98% 99.98% # Request fanout histogram 985system.cpu.toL2Bus.snoop_fanout::1 350 0.02% 100.00% # Request fanout histogram |
| 988system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 989system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 990system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 991system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 986system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 987system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 988system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 989system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 992system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram 993system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) | 990system.cpu.toL2Bus.snoop_fanout::total 2079477 # Request fanout histogram 991system.cpu.toL2Bus.reqLayer0.occupancy 4143540000 # Layer occupancy (ticks) |
| 994system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) | 992system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) |
| 995system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) | 993system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) |
| 996system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 994system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 997system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) 998system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) 999system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states 1000system.membus.trans_dist::ReadResp 1640 # Transaction distribution | 995system.cpu.toL2Bus.respLayer1.occupancy 3116545500 # Layer occupancy (ticks) 996system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) 997system.membus.snoop_filter.tot_requests 30966 # Total number of requests made to the snoop filter. 998system.membus.snoop_filter.hit_single_requests 332 # Number of requests hitting in the snoop filter with a single holder of the requested data. 999system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1000system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1001system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1002system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1003system.membus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states 1004system.membus.trans_dist::ReadResp 1645 # Transaction distribution |
| 1001system.membus.trans_dist::WritebackDirty 280 # Transaction distribution | 1005system.membus.trans_dist::WritebackDirty 280 # Transaction distribution |
| 1002system.membus.trans_dist::CleanEvict 45 # Transaction distribution 1003system.membus.trans_dist::ReadExReq 28982 # Transaction distribution 1004system.membus.trans_dist::ReadExResp 28982 # Transaction distribution 1005system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution 1006system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) 1007system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) 1008system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) 1009system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) 1010system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) 1011system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) | 1006system.membus.trans_dist::CleanEvict 52 # Transaction distribution 1007system.membus.trans_dist::ReadExReq 28989 # Transaction distribution 1008system.membus.trans_dist::ReadExResp 28989 # Transaction distribution 1009system.membus.trans_dist::ReadSharedReq 1645 # Transaction distribution 1010system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61600 # Packet count per connected master and slave (bytes) 1011system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61600 # Packet count per connected master and slave (bytes) 1012system.membus.pkt_count::total 61600 # Packet count per connected master and slave (bytes) 1013system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1978496 # Cumulative packet size per connected master and slave (bytes) 1014system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1978496 # Cumulative packet size per connected master and slave (bytes) 1015system.membus.pkt_size::total 1978496 # Cumulative packet size per connected master and slave (bytes) |
| 1012system.membus.snoops 0 # Total snoops (count) 1013system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1016system.membus.snoops 0 # Total snoops (count) 1017system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1014system.membus.snoop_fanout::samples 30947 # Request fanout histogram | 1018system.membus.snoop_fanout::samples 30634 # Request fanout histogram |
| 1015system.membus.snoop_fanout::mean 0 # Request fanout histogram 1016system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1017system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1019system.membus.snoop_fanout::mean 0 # Request fanout histogram 1020system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1021system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1018system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram | 1022system.membus.snoop_fanout::0 30634 100.00% 100.00% # Request fanout histogram |
| 1019system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1020system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1021system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1022system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1023system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1024system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1025system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1026system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1023system.membus.snoop_fanout::total 30947 # Request fanout histogram 1024system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) | 1027system.membus.snoop_fanout::total 30634 # Request fanout histogram 1028system.membus.reqLayer0.occupancy 43502500 # Layer occupancy (ticks) |
| 1025system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1029system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1026system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) | 1030system.membus.respLayer1.occupancy 161439750 # Layer occupancy (ticks) |
| 1027system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1028 1029---------- End Simulation Statistics ---------- | 1031system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1032 1033---------- End Simulation Statistics ---------- |