| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.065987 # Number of seconds simulated 4sim_ticks 65986743500 # Number of ticks simulated 5final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.065987 # Number of seconds simulated 4sim_ticks 65986743500 # Number of ticks simulated 5final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 126294 # Simulator instruction rate (inst/s) 8host_op_rate 222383 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52748930 # Simulator tick rate (ticks/s) | 7host_inst_rate 126228 # Simulator instruction rate (inst/s) 8host_op_rate 222267 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52721316 # Simulator tick rate (ticks/s) |
| 10host_mem_usage 414760 # Number of bytes of host memory used | 10host_mem_usage 414760 # Number of bytes of host memory used |
| 11host_seconds 1250.96 # Real time elapsed on the host | 11host_seconds 1251.61 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory --- 627 unchanged lines hidden (view full) --- 647system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency 648system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency 649system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked 650system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked 652system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked 654system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory --- 627 unchanged lines hidden (view full) --- 647system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency 648system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency 649system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked 650system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked 652system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked 654system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked |
| 655system.cpu.dcache.fast_writes 0 # number of fast writes performed 656system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 657system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks 658system.cpu.dcache.writebacks::total 2066969 # number of writebacks 659system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits 660system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits 661system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 662system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 663system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits 664system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 691system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency 692system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency 693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency | 655system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks 656system.cpu.dcache.writebacks::total 2066969 # number of writebacks 657system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits 658system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits 659system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 661system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits 662system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency |
| 699system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 700system.cpu.icache.tags.replacements 93 # number of replacements 701system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use 702system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. 703system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. 704system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. 705system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 706system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor 707system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 752system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency 753system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency 754system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked 755system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 756system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked 757system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 758system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked 759system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 697system.cpu.icache.tags.replacements 93 # number of replacements 698system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use 699system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. 700system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. 701system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. 702system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 703system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor 704system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 749system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency 750system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency 751system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked 752system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked 754system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked 756system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 760system.cpu.icache.fast_writes 0 # number of fast writes performed 761system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 762system.cpu.icache.writebacks::writebacks 93 # number of writebacks 763system.cpu.icache.writebacks::total 93 # number of writebacks 764system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits 765system.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits 766system.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits 767system.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits 768system.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits 769system.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 786system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 787system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 788system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency 789system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency 790system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 791system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency 792system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 793system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency | 757system.cpu.icache.writebacks::writebacks 93 # number of writebacks 758system.cpu.icache.writebacks::total 93 # number of writebacks 759system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits 760system.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits 761system.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits 762system.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits 763system.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits 764system.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 782system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency |
| 794system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 795system.cpu.l2cache.tags.replacements 650 # number of replacements 796system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use 797system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. 798system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. 799system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. 800system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 801system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 895system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency 896system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency 897system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 898system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 899system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 900system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 901system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 902system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 789system.cpu.l2cache.tags.replacements 650 # number of replacements 790system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use 791system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. 792system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. 793system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. 794system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 795system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 889system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency 891system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 896system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 903system.cpu.l2cache.fast_writes 0 # number of fast writes performed 904system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 905system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks 906system.cpu.l2cache.writebacks::total 280 # number of writebacks 907system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses 909system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses 910system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses 911system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses 912system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses --- 34 unchanged lines hidden (view full) --- 947system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency 948system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 950system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 951system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 953system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 954system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency | 897system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks 898system.cpu.l2cache.writebacks::total 280 # number of writebacks 899system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses 900system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses 901system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses 902system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses 903system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses 904system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses --- 34 unchanged lines hidden (view full) --- 939system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency 940system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency 941system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 942system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 943system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency 944system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 945system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 946system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency |
| 955system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 956system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. 957system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. 958system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 959system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. 960system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 961system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 962system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution --- 59 unchanged lines hidden --- | 947system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. 948system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. 949system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 950system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. 951system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 952system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 953system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution --- 59 unchanged lines hidden --- |