| stats.txt (11384:e3cbd2823210) | stats.txt (11388:bd4125134e77) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061602 # Number of seconds simulated 4sim_ticks 61602281500 # Number of ticks simulated 5final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061602 # Number of seconds simulated 4sim_ticks 61602281500 # Number of ticks simulated 5final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 59652 # Simulator instruction rate (inst/s) 8host_op_rate 105038 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23259273 # Simulator tick rate (ticks/s) 10host_mem_usage 445096 # Number of bytes of host memory used 11host_seconds 2648.50 # Real time elapsed on the host | 7host_inst_rate 60207 # Simulator instruction rate (inst/s) 8host_op_rate 106015 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23475786 # Simulator tick rate (ticks/s) 10host_mem_usage 445092 # Number of bytes of host memory used 11host_seconds 2624.08 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory |
| 19system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory 22system.physmem.bytes_written::total 12160 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory | 19system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory 22system.physmem.bytes_written::total 12160 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory |
| 26system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 190 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) | 26system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 190 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) |
| 29system.physmem.bw_read::cpu.data 30569257 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 31606102 # Total read bandwidth from this memory (bytes/s) | 29system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) | 31system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.bw_total::cpu.data 30569257 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 31803497 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30422 # Number of read requests accepted | 37system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30421 # Number of read requests accepted |
| 40system.physmem.writeReqs 190 # Number of write requests accepted | 40system.physmem.writeReqs 190 # Number of write requests accepted |
| 41system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue | 41system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue |
| 42system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue | 42system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue |
| 43system.physmem.bytesReadDRAM 1941504 # Total number of bytes read from DRAM | 43system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM |
| 44system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue 45system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM | 44system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue 45system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM |
| 46system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side | 46system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side |
| 47system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1928 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2059 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2023 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1928 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2025 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1901 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1952 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1864 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1938 # Per bank write bursts | 47system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1928 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2059 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2023 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1928 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2025 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1901 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1952 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1864 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1938 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::9 1932 # Per bank write bursts | 60system.physmem.perBankRdBursts::9 1931 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::10 1804 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1794 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 67system.physmem.perBankWrBursts::0 10 # Per bank write bursts 68system.physmem.perBankWrBursts::1 78 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 61602096500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 61system.physmem.perBankRdBursts::10 1804 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1794 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 67system.physmem.perBankWrBursts::0 10 # Per bank write bursts 68system.physmem.perBankWrBursts::1 78 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 61602096500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 30422 # Read request sizes (log2) | 92system.physmem.readPktSize::6 30421 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 190 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 190 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation | 102system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation |
| 197system.physmem.bytesPerActivate::mean 716.489526 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 515.486965 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 387.954881 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 364 13.38% 13.38% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 231 8.49% 21.87% # Bytes accessed per row activation | 197system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation |
| 202system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes | 202system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes |
| 211system.physmem.rdPerTurnAround::mean 3363.777778 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 10055.709980 # Reads before turning the bus around for writes | 211system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes |
| 213system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes 216system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads 223system.physmem.totQLat 133021500 # Total ticks spent queuing | 213system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes 216system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads 223system.physmem.totQLat 133021500 # Total ticks spent queuing |
| 224system.physmem.totMemAccLat 701821500 # Total ticks spent from burst creation until serviced by the DRAM 225system.physmem.totBusLat 151680000 # Total ticks spent in databus transfers 226system.physmem.avgQLat 4384.94 # Average queueing delay per DRAM burst | 224system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM 225system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers 226system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst |
| 227system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 227system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 228system.physmem.avgMemAccLat 23134.94 # Average memory access latency per DRAM burst | 228system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst |
| 229system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s 230system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s 231system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s 232system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s 233system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 234system.physmem.busUtil 0.25 # Data bus utilization in percentage 235system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 236system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 237system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 238system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing | 229system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s 230system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s 231system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s 232system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s 233system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 234system.physmem.busUtil 0.25 # Data bus utilization in percentage 235system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 236system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 237system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 238system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing |
| 239system.physmem.readRowHits 27659 # Number of row buffer hits during reads | 239system.physmem.readRowHits 27658 # Number of row buffer hits during reads |
| 240system.physmem.writeRowHits 106 # Number of row buffer hits during writes 241system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads 242system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes | 240system.physmem.writeRowHits 106 # Number of row buffer hits during writes 241system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads 242system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes |
| 243system.physmem.avgGap 2012351.25 # Average gap between requests | 243system.physmem.avgGap 2012416.99 # Average gap between requests |
| 244system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined 245system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) 246system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) 247system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ) 248system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ) 249system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) 250system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ) 251system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ) 252system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ) 253system.physmem_0.averagePower 673.239327 # Core power per rank (mW) 254system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states 255system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states 256system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 257system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states 258system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 259system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) 260system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) | 244system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined 245system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) 246system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) 247system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ) 248system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ) 249system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) 250system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ) 251system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ) 252system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ) 253system.physmem_0.averagePower 673.239327 # Core power per rank (mW) 254system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states 255system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states 256system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 257system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states 258system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 259system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) 260system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) |
| 261system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) | 261system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ) |
| 262system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 263system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) 264system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) 265system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) | 262system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 263system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) 264system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) 265system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) |
| 266system.physmem_1.totalEnergy 41481574230 # Total energy per rank (pJ) 267system.physmem_1.averagePower 673.432024 # Core power per rank (mW) | 266system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ) 267system.physmem_1.averagePower 673.431898 # Core power per rank (mW) |
| 268system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states 269system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states 270system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states 272system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.cpu.branchPred.lookups 36908905 # Number of BP lookups 274system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted 275system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect --- 69 unchanged lines hidden (view full) --- 345system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. 346system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads. 347system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. 348system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ 350system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued 351system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued 352system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling | 268system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states 269system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states 270system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states 272system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.cpu.branchPred.lookups 36908905 # Number of BP lookups 274system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted 275system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect --- 69 unchanged lines hidden (view full) --- 345system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. 346system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads. 347system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. 348system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ 350system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued 351system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued 352system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 353system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph | 353system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph |
| 354system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed 355system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle --- 76 unchanged lines hidden (view full) --- 438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued 441system.cpu.iq.rate 2.484510 # Inst issue rate 442system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested 443system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) 444system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads 445system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes | 354system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed 355system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle --- 76 unchanged lines hidden (view full) --- 438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued 441system.cpu.iq.rate 2.484510 # Inst issue rate 442system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested 443system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) 444system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads 445system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes |
| 446system.cpu.iq.int_inst_queue_wakeup_accesses 304282659 # Number of integer instruction queue wakeup accesses | 446system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses |
| 447system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads 448system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes 449system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses 450system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses 451system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses 452system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores 453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed --- 23 unchanged lines hidden (view full) --- 478system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed 479system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute 480system.cpu.iew.exec_swp 0 # number of swp insts executed 481system.cpu.iew.exec_nop 0 # number of nop insts executed 482system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed 483system.cpu.iew.exec_branches 31401849 # Number of branches executed 484system.cpu.iew.exec_stores 33679798 # Number of stores executed 485system.cpu.iew.exec_rate 2.476830 # Inst execution rate | 447system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads 448system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes 449system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses 450system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses 451system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses 452system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores 453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed --- 23 unchanged lines hidden (view full) --- 478system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed 479system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute 480system.cpu.iew.exec_swp 0 # number of swp insts executed 481system.cpu.iew.exec_nop 0 # number of nop insts executed 482system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed 483system.cpu.iew.exec_branches 31401849 # Number of branches executed 484system.cpu.iew.exec_stores 33679798 # Number of stores executed 485system.cpu.iew.exec_rate 2.476830 # Inst execution rate |
| 486system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit 487system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back | 486system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit 487system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back |
| 488system.cpu.iew.wb_producers 230213909 # num instructions producing a value 489system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value 490system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back 492system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit 493system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 494system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle --- 72 unchanged lines hidden (view full) --- 568system.cpu.int_regfile_reads 491477136 # number of integer regfile reads 569system.cpu.int_regfile_writes 239432261 # number of integer regfile writes 570system.cpu.fp_regfile_reads 110 # number of floating regfile reads 571system.cpu.fp_regfile_writes 84 # number of floating regfile writes 572system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads 573system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes 574system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads 575system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 488system.cpu.iew.wb_producers 230213909 # num instructions producing a value 489system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value 490system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back 492system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit 493system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 494system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle --- 72 unchanged lines hidden (view full) --- 568system.cpu.int_regfile_reads 491477136 # number of integer regfile reads 569system.cpu.int_regfile_writes 239432261 # number of integer regfile writes 570system.cpu.fp_regfile_reads 110 # number of floating regfile reads 571system.cpu.fp_regfile_writes 84 # number of floating regfile writes 572system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads 573system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes 574system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads 575system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 576system.cpu.dcache.tags.replacements 2072313 # number of replacements 577system.cpu.dcache.tags.tagsinuse 4068.012890 # Cycle average of tags in use | 576system.cpu.dcache.tags.replacements 2072312 # number of replacements 577system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use |
| 578system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. | 578system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. |
| 579system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks. 580system.cpu.dcache.tags.avg_refs 32.783059 # Average number of references to valid blocks. | 579system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks. 580system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks. |
| 581system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. | 581system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. |
| 582system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012890 # Average occupied blocks per requestor 583system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy | 582system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor 583system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy |
| 585system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 589system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 585system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 589system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 590system.cpu.dcache.tags.tag_accesses 143788645 # Number of tag accesses 591system.cpu.dcache.tags.data_accesses 143788645 # Number of data accesses | 590system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses 591system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses |
| 592system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits 593system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits 594system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits 595system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits 596system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits 597system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits 598system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits 599system.cpu.dcache.overall_hits::total 68071037 # number of overall hits | 592system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits 593system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits 594system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits 595system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits 596system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits 597system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits 598system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits 599system.cpu.dcache.overall_hits::total 68071037 # number of overall hits |
| 600system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses 601system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses | 600system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses 601system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses |
| 602system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses 603system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses | 602system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses 603system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses |
| 604system.cpu.dcache.demand_misses::cpu.data 2785081 # number of demand (read+write) misses 605system.cpu.dcache.demand_misses::total 2785081 # number of demand (read+write) misses 606system.cpu.dcache.overall_misses::cpu.data 2785081 # number of overall misses 607system.cpu.dcache.overall_misses::total 2785081 # number of overall misses 608system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304267000 # number of ReadReq miss cycles 609system.cpu.dcache.ReadReq_miss_latency::total 32304267000 # number of ReadReq miss cycles | 604system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses 605system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses 606system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses 607system.cpu.dcache.overall_misses::total 2785080 # number of overall misses 608system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles 609system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles |
| 610system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles 611system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles | 610system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles 611system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles |
| 612system.cpu.dcache.demand_miss_latency::cpu.data 35260881994 # number of demand (read+write) miss cycles 613system.cpu.dcache.demand_miss_latency::total 35260881994 # number of demand (read+write) miss cycles 614system.cpu.dcache.overall_miss_latency::cpu.data 35260881994 # number of overall miss cycles 615system.cpu.dcache.overall_miss_latency::total 35260881994 # number of overall miss cycles 616system.cpu.dcache.ReadReq_accesses::cpu.data 39416366 # number of ReadReq accesses(hits+misses) 617system.cpu.dcache.ReadReq_accesses::total 39416366 # number of ReadReq accesses(hits+misses) | 612system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles 613system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles 614system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles 615system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles 616system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses) 617system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses) |
| 618system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 619system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 618system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 619system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 620system.cpu.dcache.demand_accesses::cpu.data 70856118 # number of demand (read+write) accesses 621system.cpu.dcache.demand_accesses::total 70856118 # number of demand (read+write) accesses 622system.cpu.dcache.overall_accesses::cpu.data 70856118 # number of overall (read+write) accesses 623system.cpu.dcache.overall_accesses::total 70856118 # number of overall (read+write) accesses | 620system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses 621system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses 622system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses 623system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses |
| 624system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses 625system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses 626system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses 627system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses 628system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses 629system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses 630system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses 631system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses | 624system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses 625system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses 626system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses 627system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses 628system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses 629system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses 630system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses 631system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses |
| 632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573 # average ReadReq miss latency 633system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573 # average ReadReq miss latency | 632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency 633system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency |
| 634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency | 634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency |
| 636system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency 637system.cpu.dcache.demand_avg_miss_latency::total 12660.630694 # average overall miss latency 638system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency 639system.cpu.dcache.overall_avg_miss_latency::total 12660.630694 # average overall miss latency | 636system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency 637system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency 638system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency 639system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency |
| 640system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked 641system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked 643system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked 645system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu.dcache.fast_writes 0 # number of fast writes performed 647system.cpu.dcache.cache_copies 0 # number of cache copies performed 648system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks 649system.cpu.dcache.writebacks::total 2066601 # number of writebacks 650system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits 651system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits 652system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 653system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 654system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits 655system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits 656system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits 657system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits | 640system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked 641system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked 643system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked 645system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu.dcache.fast_writes 0 # number of fast writes performed 647system.cpu.dcache.cache_copies 0 # number of cache copies performed 648system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks 649system.cpu.dcache.writebacks::total 2066601 # number of writebacks 650system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits 651system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits 652system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 653system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 654system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits 655system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits 656system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits 657system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits |
| 658system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses 659system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses | 658system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994365 # number of ReadReq MSHR misses 659system.cpu.dcache.ReadReq_mshr_misses::total 1994365 # number of ReadReq MSHR misses |
| 660system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses 661system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses | 660system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses 661system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses |
| 662system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 # number of demand (read+write) MSHR misses 663system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses 664system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses 665system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses 666system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195993500 # number of ReadReq MSHR miss cycles 667system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195993500 # number of ReadReq MSHR miss cycles | 662system.cpu.dcache.demand_mshr_misses::cpu.data 2076409 # number of demand (read+write) MSHR misses 663system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses 664system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses 665system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses 666system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles 667system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles |
| 668system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles 669system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles | 668system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles 669system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles |
| 670system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995390495 # number of demand (read+write) MSHR miss cycles 671system.cpu.dcache.demand_mshr_miss_latency::total 26995390495 # number of demand (read+write) MSHR miss cycles 672system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995390495 # number of overall MSHR miss cycles 673system.cpu.dcache.overall_mshr_miss_latency::total 26995390495 # number of overall MSHR miss cycles | 670system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles 671system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles 672system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles 673system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles |
| 674system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses 675system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses 676system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 677system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses | 674system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses 675system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses 676system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 677system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses |
| 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.173082 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.173082 # average ReadReq mshr miss latency | 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency |
| 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency | 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency |
| 686system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency 687system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency 688system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency 689system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency | 686system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency 687system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency 688system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency 689system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency |
| 690system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 691system.cpu.icache.tags.replacements 53 # number of replacements 692system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use 693system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks. 694system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. 695system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks. 696system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 697system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor --- 80 unchanged lines hidden (view full) --- 778system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency 779system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency 780system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency 781system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency 782system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency 783system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency 784system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cpu.l2cache.tags.replacements 493 # number of replacements | 690system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 691system.cpu.icache.tags.replacements 53 # number of replacements 692system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use 693system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks. 694system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. 695system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks. 696system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 697system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor --- 80 unchanged lines hidden (view full) --- 778system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency 779system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency 780system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency 781system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency 782system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency 783system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency 784system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cpu.l2cache.tags.replacements 493 # number of replacements |
| 786system.cpu.l2cache.tags.tagsinuse 20712.318868 # Cycle average of tags in use 787system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. 788system.cpu.l2cache.tags.sampled_refs 30411 # Sample count of references to valid blocks. 789system.cpu.l2cache.tags.avg_refs 132.685640 # Average number of references to valid blocks. | 786system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use 787system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks. 788system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks. 789system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks. |
| 790system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 791system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor | 790system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 791system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor |
| 793system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917380 # Average occupied blocks per requestor | 793system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor |
| 794system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy | 794system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy |
| 796system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id | 796system.cpu.l2cache.tags.occ_percent::cpu.data 0.007474 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::total 0.632059 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_task_id_blocks::1024 29917 # Occupied blocks per task id |
| 799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id | 799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id |
| 803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27623 # Occupied blocks per task id 804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913025 # Percentage of cache occupancy per task id 805system.cpu.l2cache.tags.tag_accesses 33310473 # Number of tag accesses 806system.cpu.l2cache.tags.data_accesses 33310473 # Number of data accesses | 803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27622 # Occupied blocks per task id 804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912994 # Percentage of cache occupancy per task id 805system.cpu.l2cache.tags.tag_accesses 33310456 # Number of tag accesses 806system.cpu.l2cache.tags.data_accesses 33310456 # Number of data accesses |
| 807system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits 808system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits 809system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits 810system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits 811system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 812system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 813system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits 814system.cpu.l2cache.ReadExReq_hits::total 53071 # number of ReadExReq hits --- 6 unchanged lines hidden (view full) --- 821system.cpu.l2cache.demand_hits::total 2047001 # number of demand (read+write) hits 822system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 823system.cpu.l2cache.overall_hits::cpu.data 2046985 # number of overall hits 824system.cpu.l2cache.overall_hits::total 2047001 # number of overall hits 825system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses 826system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses 827system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 998 # number of ReadCleanReq misses 828system.cpu.l2cache.ReadCleanReq_misses::total 998 # number of ReadCleanReq misses | 807system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits 808system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits 809system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits 810system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits 811system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 812system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 813system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits 814system.cpu.l2cache.ReadExReq_hits::total 53071 # number of ReadExReq hits --- 6 unchanged lines hidden (view full) --- 821system.cpu.l2cache.demand_hits::total 2047001 # number of demand (read+write) hits 822system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 823system.cpu.l2cache.overall_hits::cpu.data 2046985 # number of overall hits 824system.cpu.l2cache.overall_hits::total 2047001 # number of overall hits 825system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses 826system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses 827system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 998 # number of ReadCleanReq misses 828system.cpu.l2cache.ReadCleanReq_misses::total 998 # number of ReadCleanReq misses |
| 829system.cpu.l2cache.ReadSharedReq_misses::cpu.data 426 # number of ReadSharedReq misses 830system.cpu.l2cache.ReadSharedReq_misses::total 426 # number of ReadSharedReq misses | 829system.cpu.l2cache.ReadSharedReq_misses::cpu.data 425 # number of ReadSharedReq misses 830system.cpu.l2cache.ReadSharedReq_misses::total 425 # number of ReadSharedReq misses |
| 831system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses | 831system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses |
| 832system.cpu.l2cache.demand_misses::cpu.data 29424 # number of demand (read+write) misses 833system.cpu.l2cache.demand_misses::total 30422 # number of demand (read+write) misses | 832system.cpu.l2cache.demand_misses::cpu.data 29423 # number of demand (read+write) misses 833system.cpu.l2cache.demand_misses::total 30421 # number of demand (read+write) misses |
| 834system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses | 834system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses |
| 835system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses 836system.cpu.l2cache.overall_misses::total 30422 # number of overall misses | 835system.cpu.l2cache.overall_misses::cpu.data 29423 # number of overall misses 836system.cpu.l2cache.overall_misses::total 30421 # number of overall misses |
| 837system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles 839system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles 840system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles | 837system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles 839system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles 840system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles |
| 841system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32704000 # number of ReadSharedReq miss cycles 842system.cpu.l2cache.ReadSharedReq_miss_latency::total 32704000 # number of ReadSharedReq miss cycles | 841system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32635000 # number of ReadSharedReq miss cycles 842system.cpu.l2cache.ReadSharedReq_miss_latency::total 32635000 # number of ReadSharedReq miss cycles |
| 843system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles | 843system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles |
| 844system.cpu.l2cache.demand_miss_latency::cpu.data 2150842000 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::total 2226559000 # number of demand (read+write) miss cycles | 844system.cpu.l2cache.demand_miss_latency::cpu.data 2150773000 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::total 2226490000 # number of demand (read+write) miss cycles |
| 846system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles | 846system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles |
| 847system.cpu.l2cache.overall_miss_latency::cpu.data 2150842000 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::total 2226559000 # number of overall miss cycles | 847system.cpu.l2cache.overall_miss_latency::cpu.data 2150773000 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::total 2226490000 # number of overall miss cycles |
| 849system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses) 850system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses) 851system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses) 852system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses) 853system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 854system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses) 858system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses) | 849system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses) 850system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses) 851system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses) 852system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses) 853system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 854system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses) 858system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses) |
| 859system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994340 # number of ReadSharedReq accesses(hits+misses) 860system.cpu.l2cache.ReadSharedReq_accesses::total 1994340 # number of ReadSharedReq accesses(hits+misses) | 859system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994339 # number of ReadSharedReq accesses(hits+misses) 860system.cpu.l2cache.ReadSharedReq_accesses::total 1994339 # number of ReadSharedReq accesses(hits+misses) |
| 861system.cpu.l2cache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses | 861system.cpu.l2cache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses |
| 862system.cpu.l2cache.demand_accesses::cpu.data 2076409 # number of demand (read+write) accesses 863system.cpu.l2cache.demand_accesses::total 2077423 # number of demand (read+write) accesses | 862system.cpu.l2cache.demand_accesses::cpu.data 2076408 # number of demand (read+write) accesses 863system.cpu.l2cache.demand_accesses::total 2077422 # number of demand (read+write) accesses |
| 864system.cpu.l2cache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses | 864system.cpu.l2cache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses |
| 865system.cpu.l2cache.overall_accesses::cpu.data 2076409 # number of overall (read+write) accesses 866system.cpu.l2cache.overall_accesses::total 2077423 # number of overall (read+write) accesses | 865system.cpu.l2cache.overall_accesses::cpu.data 2076408 # number of overall (read+write) accesses 866system.cpu.l2cache.overall_accesses::total 2077422 # number of overall (read+write) accesses |
| 867system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353337 # miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadExReq_miss_rate::total 0.353337 # miss rate for ReadExReq accesses 869system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.984221 # miss rate for ReadCleanReq accesses 870system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.984221 # miss rate for ReadCleanReq accesses | 867system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353337 # miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadExReq_miss_rate::total 0.353337 # miss rate for ReadExReq accesses 869system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.984221 # miss rate for ReadCleanReq accesses 870system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.984221 # miss rate for ReadCleanReq accesses |
| 871system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000214 # miss rate for ReadSharedReq accesses 872system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000214 # miss rate for ReadSharedReq accesses | 871system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000213 # miss rate for ReadSharedReq accesses 872system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000213 # miss rate for ReadSharedReq accesses |
| 873system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses | 873system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses |
| 874system.cpu.l2cache.demand_miss_rate::cpu.data 0.014171 # miss rate for demand accesses | 874system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses |
| 875system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses 876system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses | 875system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses 876system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses |
| 877system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses | 877system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses |
| 878system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses 879system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency 881system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency 882system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency | 878system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses 879system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency 881system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency 882system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency |
| 883system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76769.953052 # average ReadSharedReq miss latency 884system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76769.953052 # average ReadSharedReq miss latency | 883system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294 # average ReadSharedReq miss latency 884system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294 # average ReadSharedReq miss latency |
| 885system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency | 885system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency |
| 886system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency 887system.cpu.l2cache.demand_avg_miss_latency::total 73189.106568 # average overall miss latency | 886system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency 887system.cpu.l2cache.demand_avg_miss_latency::total 73189.244272 # average overall miss latency |
| 888system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency | 888system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency |
| 889system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::total 73189.106568 # average overall miss latency | 889system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::total 73189.244272 # average overall miss latency |
| 891system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 896system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 897system.cpu.l2cache.fast_writes 0 # number of fast writes performed 898system.cpu.l2cache.cache_copies 0 # number of cache copies performed 899system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks 900system.cpu.l2cache.writebacks::total 190 # number of writebacks 901system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses 902system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses 903system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses 904system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses | 891system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 896system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 897system.cpu.l2cache.fast_writes 0 # number of fast writes performed 898system.cpu.l2cache.cache_copies 0 # number of cache copies performed 899system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks 900system.cpu.l2cache.writebacks::total 190 # number of writebacks 901system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses 902system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses 903system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses 904system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses |
| 905system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 426 # number of ReadSharedReq MSHR misses 906system.cpu.l2cache.ReadSharedReq_mshr_misses::total 426 # number of ReadSharedReq MSHR misses | 905system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 425 # number of ReadSharedReq MSHR misses 906system.cpu.l2cache.ReadSharedReq_mshr_misses::total 425 # number of ReadSharedReq MSHR misses |
| 907system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses | 907system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses |
| 908system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::total 30422 # number of demand (read+write) MSHR misses | 908system.cpu.l2cache.demand_mshr_misses::cpu.data 29423 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::total 30421 # number of demand (read+write) MSHR misses |
| 910system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses | 910system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses |
| 911system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses | 911system.cpu.l2cache.overall_mshr_misses::cpu.data 29423 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::total 30421 # number of overall MSHR misses |
| 913system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles 916system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles | 913system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles 916system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles |
| 917system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28444000 # number of ReadSharedReq MSHR miss cycles 918system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28444000 # number of ReadSharedReq MSHR miss cycles | 917system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28385000 # number of ReadSharedReq MSHR miss cycles 918system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28385000 # number of ReadSharedReq MSHR miss cycles |
| 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles | 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles |
| 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856602000 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::total 1922339000 # number of demand (read+write) MSHR miss cycles | 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856543000 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::total 1922280000 # number of demand (read+write) MSHR miss cycles |
| 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles | 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles |
| 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856602000 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::total 1922339000 # number of overall MSHR miss cycles | 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles |
| 925system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses 926system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses 927system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses 928system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses | 925system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses 926system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses 927system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses 928system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses |
| 929system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses 930system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses | 929system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses 930system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses |
| 931system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses | 931system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses |
| 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses | 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses |
| 933system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses 934system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses | 933system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses 934system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses |
| 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses | 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses |
| 936system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses 937system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency 938system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency 939system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency 940system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency | 936system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses 937system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency 938system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency 939system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency 940system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency |
| 941system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052 # average ReadSharedReq mshr miss latency 942system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052 # average ReadSharedReq mshr miss latency | 941system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency 942system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency |
| 943system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency | 943system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency |
| 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency | 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency |
| 946system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency | 946system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency |
| 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency | 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency |
| 949system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 949system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 950system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. 951system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 950system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter. 951system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 952system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 953system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. 954system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 955system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 952system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 953system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. 954system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 955system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 956system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution | 956system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution |
| 957system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution | 957system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution |
| 959system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution | 959system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution |
| 960system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution | 960system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution |
| 965system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution | 965system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution |
| 966system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) | 966system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) |
| 967system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes) | 967system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes) |
| 969system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) | 969system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) |
| 970system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) 971system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes) | 970system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes) 971system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes) |
| 972system.cpu.toL2Bus.snoops 493 # Total snoops (count) | 972system.cpu.toL2Bus.snoops 493 # Total snoops (count) |
| 973system.cpu.toL2Bus.snoop_fanout::samples 2077917 # Request fanout histogram | 973system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram |
| 974system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 974system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 977system.cpu.toL2Bus.snoop_fanout::0 2077592 99.98% 99.98% # Request fanout histogram | 977system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram |
| 978system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 980system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 978system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 980system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 983system.cpu.toL2Bus.snoop_fanout::total 2077917 # Request fanout histogram 984system.cpu.toL2Bus.reqLayer0.occupancy 4141549000 # Layer occupancy (ticks) | 983system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram 984system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks) |
| 985system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 986system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) 987system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 985system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 986system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) 987system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 988system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) | 988system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks) |
| 989system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) | 989system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) |
| 990system.membus.trans_dist::ReadResp 1424 # Transaction distribution | 990system.membus.trans_dist::ReadResp 1423 # Transaction distribution |
| 991system.membus.trans_dist::WritebackDirty 190 # Transaction distribution 992system.membus.trans_dist::CleanEvict 24 # Transaction distribution 993system.membus.trans_dist::ReadExReq 28998 # Transaction distribution 994system.membus.trans_dist::ReadExResp 28998 # Transaction distribution | 991system.membus.trans_dist::WritebackDirty 190 # Transaction distribution 992system.membus.trans_dist::CleanEvict 24 # Transaction distribution 993system.membus.trans_dist::ReadExReq 28998 # Transaction distribution 994system.membus.trans_dist::ReadExResp 28998 # Transaction distribution |
| 995system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution 996system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes) 997system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes) 998system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes) 999system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959168 # Cumulative packet size per connected master and slave (bytes) 1000system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959168 # Cumulative packet size per connected master and slave (bytes) 1001system.membus.pkt_size::total 1959168 # Cumulative packet size per connected master and slave (bytes) | 995system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution 996system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes) 997system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes) 998system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes) 999system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes) 1000system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes) 1001system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes) |
| 1002system.membus.snoops 0 # Total snoops (count) | 1002system.membus.snoops 0 # Total snoops (count) |
| 1003system.membus.snoop_fanout::samples 30636 # Request fanout histogram | 1003system.membus.snoop_fanout::samples 30635 # Request fanout histogram |
| 1004system.membus.snoop_fanout::mean 0 # Request fanout histogram 1005system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1006system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1004system.membus.snoop_fanout::mean 0 # Request fanout histogram 1005system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1006system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1007system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram | 1007system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram |
| 1008system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1009system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1010system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1011system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1008system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1009system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1010system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1011system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1012system.membus.snoop_fanout::total 30636 # Request fanout histogram 1013system.membus.reqLayer0.occupancy 42770500 # Layer occupancy (ticks) | 1012system.membus.snoop_fanout::total 30635 # Request fanout histogram 1013system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks) |
| 1014system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1014system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1015system.membus.respLayer1.occupancy 160321750 # Layer occupancy (ticks) | 1015system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks) |
| 1016system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 1017 1018---------- End Simulation Statistics ---------- | 1016system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 1017 1018---------- End Simulation Statistics ---------- |