| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061602 # Number of seconds simulated 4sim_ticks 61602395500 # Number of ticks simulated 5final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061602 # Number of seconds simulated 4sim_ticks 61602395500 # Number of ticks simulated 5final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 83209 # Simulator instruction rate (inst/s) 8host_op_rate 146518 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32444685 # Simulator tick rate (ticks/s) 10host_mem_usage 451056 # Number of bytes of host memory used 11host_seconds 1898.69 # Real time elapsed on the host | 7host_inst_rate 109389 # Simulator instruction rate (inst/s) 8host_op_rate 192617 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42652748 # Simulator tick rate (ticks/s) 10host_mem_usage 458300 # Number of bytes of host memory used 11host_seconds 1444.28 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory --- 197 unchanged lines hidden (view full) --- 217system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.888889 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.873018 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.781736 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory --- 197 unchanged lines hidden (view full) --- 217system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.888889 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.873018 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.781736 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads |
| 225system.physmem.totQLat 132992250 # Total ticks spent queuing 226system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM | 225system.physmem.totQLat 132940250 # Total ticks spent queuing 226system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM |
| 227system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers | 227system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers |
| 228system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst | 228system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst |
| 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 230system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst | 230system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst |
| 231system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.25 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 244system.physmem.writeRowHitRate 57.38 # Row buffer hit rate for writes 245system.physmem.avgGap 2012749.48 # Average gap between requests 246system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined 247system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) 248system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) 249system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) 250system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) 251system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) | 231system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.25 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 244system.physmem.writeRowHitRate 57.38 # Row buffer hit rate for writes 245system.physmem.avgGap 2012749.48 # Average gap between requests 246system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined 247system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) 248system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) 249system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) 250system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) 251system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) |
| 252system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ) 253system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ) 254system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ) 255system.physmem_0.averagePower 673.233667 # Core power per rank (mW) 256system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states | 252system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ) 253system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ) 254system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ) 255system.physmem_0.averagePower 673.233237 # Core power per rank (mW) 256system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states |
| 257system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states 258system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 257system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states 258system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 259system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states | 259system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states |
| 260system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 261system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) 262system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) 263system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) 264system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 265system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) | 260system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 261system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) 262system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) 263system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) 264system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 265system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) |
| 266system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ) 267system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ) 269system.physmem_1.averagePower 673.432156 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states | 266system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ) 267system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ) 269system.physmem_1.averagePower 673.431985 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states |
| 271system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 271system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 273system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states | 273system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states |
| 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.cpu.branchPred.lookups 36908902 # Number of BP lookups 276system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted 277system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect 278system.cpu.branchPred.BTBLookups 21094595 # Number of BTB lookups 279system.cpu.branchPred.BTBHits 21013332 # Number of BTB hits 280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 281system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage --- 38 unchanged lines hidden (view full) --- 320system.cpu.decode.IdleCycles 12941533 # Number of cycles decode is idle 321system.cpu.decode.BlockedCycles 63708539 # Number of cycles decode is blocked 322system.cpu.decode.RunCycles 35887594 # Number of cycles decode is running 323system.cpu.decode.UnblockCycles 9825707 # Number of cycles decode is unblocking 324system.cpu.decode.SquashCycles 776598 # Number of cycles decode is squashing 325system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode 326system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing 327system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle | 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.cpu.branchPred.lookups 36908902 # Number of BP lookups 276system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted 277system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect 278system.cpu.branchPred.BTBLookups 21094595 # Number of BTB lookups 279system.cpu.branchPred.BTBHits 21013332 # Number of BTB hits 280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 281system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage --- 38 unchanged lines hidden (view full) --- 320system.cpu.decode.IdleCycles 12941533 # Number of cycles decode is idle 321system.cpu.decode.BlockedCycles 63708539 # Number of cycles decode is blocked 322system.cpu.decode.RunCycles 35887594 # Number of cycles decode is running 323system.cpu.decode.UnblockCycles 9825707 # Number of cycles decode is unblocking 324system.cpu.decode.SquashCycles 776598 # Number of cycles decode is squashing 325system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode 326system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing 327system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle |
| 328system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking | 328system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking |
| 329system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst 330system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running | 329system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst 330system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running |
| 331system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking 332system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename | 331system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking 332system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename |
| 333system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full 334system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full | 333system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full 334system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full |
| 335system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full 336system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full 337system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed 338system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made 339system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups | 335system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full 336system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full 337system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed 338system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made 339system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups |
| 340system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups 341system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed | 340system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups 341system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed |
| 342system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing | 342system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing |
| 343system.cpu.rename.serializingInsts 492 # count of serializing insts renamed 344system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed | 343system.cpu.rename.serializingInsts 492 # count of serializing insts renamed 344system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed |
| 345system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer | 345system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer |
| 346system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. 347system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. 348system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. 349system.cpu.memDep0.conflictingStores 8500454 # Number of conflicting stores. 350system.cpu.iq.iqInstsAdded 322302016 # Number of instructions added to the IQ (excludes non-spec) 351system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ 352system.cpu.iq.iqInstsIssued 306103022 # Number of instructions issued 353system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued 354system.cpu.iq.iqSquashedInstsExamined 44111266 # Number of squashed instructions iterated over during squash; mainly for profiling 355system.cpu.iq.iqSquashedOperandsExamined 63884636 # Number of squashed operands that are examined and possibly removed from graph 356system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed 357system.cpu.iq.issued_per_cycle::samples 123139971 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 346system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. 347system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. 348system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. 349system.cpu.memDep0.conflictingStores 8500454 # Number of conflicting stores. 350system.cpu.iq.iqInstsAdded 322302016 # Number of instructions added to the IQ (excludes non-spec) 351system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ 352system.cpu.iq.iqInstsIssued 306103022 # Number of instructions issued 353system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued 354system.cpu.iq.iqSquashedInstsExamined 44111266 # Number of squashed instructions iterated over during squash; mainly for profiling 355system.cpu.iq.iqSquashedOperandsExamined 63884636 # Number of squashed operands that are examined and possibly removed from graph 356system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed 357system.cpu.iq.issued_per_cycle::samples 123139971 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 361system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle | 361system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle |
| 368system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::total 123139971 # Number of insts issued each cycle 374system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntAlu 338797 8.53% 8.53% # attempts to use FU when none available --- 20 unchanged lines hidden (view full) --- 396system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available | 368system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::total 123139971 # Number of insts issued each cycle 374system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntAlu 338797 8.53% 8.53% # attempts to use FU when none available --- 20 unchanged lines hidden (view full) --- 396system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available |
| 404system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available | 404system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available |
| 405system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available 406system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 407system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 408system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued 409system.cpu.iq.FU_type_0::IntAlu 174121945 56.88% 56.89% # Type of FU issued 410system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued 411system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued --- 23 unchanged lines hidden (view full) --- 436system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued 438system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued 439system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 441system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 442system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued 443system.cpu.iq.rate 2.484506 # Inst issue rate | 405system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available 406system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 407system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 408system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued 409system.cpu.iq.FU_type_0::IntAlu 174121945 56.88% 56.89% # Type of FU issued 410system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued 411system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued --- 23 unchanged lines hidden (view full) --- 436system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued 438system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued 439system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 441system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 442system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued 443system.cpu.iq.rate 2.484506 # Inst issue rate |
| 444system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested | 444system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested |
| 445system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) | 445system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) |
| 446system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads | 446system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads |
| 447system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes 448system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses 449system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads 450system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes 451system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses | 447system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes 448system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses 449system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads 450system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes 451system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses |
| 452system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses | 452system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses |
| 453system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses 454system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores 455system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 456system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed 457system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed 458system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations 459system.cpu.iew.lsq.thread0.squashedStores 4729641 # Number of stores squashed 460system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 461system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 462system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled 463system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Number of times an access to memory failed due to the cache being blocked 464system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 465system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing 466system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking | 453system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses 454system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores 455system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 456system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed 457system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed 458system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations 459system.cpu.iew.lsq.thread0.squashedStores 4729641 # Number of stores squashed 460system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 461system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 462system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled 463system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Number of times an access to memory failed due to the cache being blocked 464system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 465system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing 466system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking |
| 467system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking | 467system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking |
| 468system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ 469system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch 470system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions 471system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions 472system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions 473system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall | 468system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ 469system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch 470system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions 471system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions 472system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions 473system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall |
| 474system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall | 474system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall |
| 475system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations 476system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly 477system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly 478system.cpu.iew.branchMispredicts 786456 # Number of branch mispredicts detected at execute 479system.cpu.iew.iewExecutedInsts 305156723 # Number of executed instructions 480system.cpu.iew.iewExecLoadInsts 97750585 # Number of load instructions executed 481system.cpu.iew.iewExecSquashedInsts 946299 # Number of squashed instructions skipped in execute 482system.cpu.iew.exec_swp 0 # number of swp insts executed 483system.cpu.iew.exec_nop 0 # number of nop insts executed 484system.cpu.iew.exec_refs 131430383 # number of memory reference insts executed 485system.cpu.iew.exec_branches 31401847 # Number of branches executed 486system.cpu.iew.exec_stores 33679798 # Number of stores executed 487system.cpu.iew.exec_rate 2.476825 # Inst execution rate | 475system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations 476system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly 477system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly 478system.cpu.iew.branchMispredicts 786456 # Number of branch mispredicts detected at execute 479system.cpu.iew.iewExecutedInsts 305156723 # Number of executed instructions 480system.cpu.iew.iewExecLoadInsts 97750585 # Number of load instructions executed 481system.cpu.iew.iewExecSquashedInsts 946299 # Number of squashed instructions skipped in execute 482system.cpu.iew.exec_swp 0 # number of swp insts executed 483system.cpu.iew.exec_nop 0 # number of nop insts executed 484system.cpu.iew.exec_refs 131430383 # number of memory reference insts executed 485system.cpu.iew.exec_branches 31401847 # Number of branches executed 486system.cpu.iew.exec_stores 33679798 # Number of stores executed 487system.cpu.iew.exec_rate 2.476825 # Inst execution rate |
| 488system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit | 488system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit |
| 489system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back 490system.cpu.iew.wb_producers 230213925 # num instructions producing a value 491system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value 492system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 493system.cpu.iew.wb_rate 2.469732 # insts written-back per cycle 494system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back 495system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 496system.cpu.commit.commitSquashedInsts 44209684 # The number of squashed insts skipped by commit 497system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 498system.cpu.commit.branchMispredicts 742009 # The number of times a branch was mispredicted 499system.cpu.commit.committed_per_cycle::samples 117119203 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 489system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back 490system.cpu.iew.wb_producers 230213925 # num instructions producing a value 491system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value 492system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 493system.cpu.iew.wb_rate 2.469732 # insts written-back per cycle 494system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back 495system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 496system.cpu.commit.commitSquashedInsts 44209684 # The number of squashed insts skipped by commit 497system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 498system.cpu.commit.branchMispredicts 742009 # The number of times a branch was mispredicted 499system.cpu.commit.committed_per_cycle::samples 117119203 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 503system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle | 503system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle |
| 505system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle | 505system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle |
| 506system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle | 506system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle |
| 511system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::total 117119203 # Number of insts commited each cycle 516system.cpu.commit.committedInsts 157988547 # Number of instructions committed 517system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 518system.cpu.commit.swp_count 0 # Number of s/w prefetches committed --- 46 unchanged lines hidden (view full) --- 565system.cpu.idleCycles 64821 # Total number of cycles that the CPU has spent unscheduled due to idling 566system.cpu.committedInsts 157988547 # Number of Instructions Simulated 567system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 568system.cpu.cpi 0.779834 # CPI: Cycles Per Instruction 569system.cpu.cpi_total 0.779834 # CPI: Total CPI of All Threads 570system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle 571system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads 572system.cpu.int_regfile_reads 491477122 # number of integer regfile reads | 511system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::total 117119203 # Number of insts commited each cycle 516system.cpu.commit.committedInsts 157988547 # Number of instructions committed 517system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 518system.cpu.commit.swp_count 0 # Number of s/w prefetches committed --- 46 unchanged lines hidden (view full) --- 565system.cpu.idleCycles 64821 # Total number of cycles that the CPU has spent unscheduled due to idling 566system.cpu.committedInsts 157988547 # Number of Instructions Simulated 567system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 568system.cpu.cpi 0.779834 # CPI: Cycles Per Instruction 569system.cpu.cpi_total 0.779834 # CPI: Total CPI of All Threads 570system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle 571system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads 572system.cpu.int_regfile_reads 491477122 # number of integer regfile reads |
| 573system.cpu.int_regfile_writes 239432261 # number of integer regfile writes | 573system.cpu.int_regfile_writes 239432260 # number of integer regfile writes |
| 574system.cpu.fp_regfile_reads 110 # number of floating regfile reads 575system.cpu.fp_regfile_writes 84 # number of floating regfile writes 576system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads 577system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes 578system.cpu.misc_regfile_reads 195275944 # number of misc regfile reads 579system.cpu.misc_regfile_writes 1 # number of misc regfile writes 580system.cpu.dcache.tags.replacements 2072313 # number of replacements 581system.cpu.dcache.tags.tagsinuse 4068.012942 # Cycle average of tags in use --- 22 unchanged lines hidden (view full) --- 604system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses 605system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses 606system.cpu.dcache.WriteReq_misses::cpu.data 93928 # number of WriteReq misses 607system.cpu.dcache.WriteReq_misses::total 93928 # number of WriteReq misses 608system.cpu.dcache.demand_misses::cpu.data 2785082 # number of demand (read+write) misses 609system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses 610system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses 611system.cpu.dcache.overall_misses::total 2785082 # number of overall misses | 574system.cpu.fp_regfile_reads 110 # number of floating regfile reads 575system.cpu.fp_regfile_writes 84 # number of floating regfile writes 576system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads 577system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes 578system.cpu.misc_regfile_reads 195275944 # number of misc regfile reads 579system.cpu.misc_regfile_writes 1 # number of misc regfile writes 580system.cpu.dcache.tags.replacements 2072313 # number of replacements 581system.cpu.dcache.tags.tagsinuse 4068.012942 # Cycle average of tags in use --- 22 unchanged lines hidden (view full) --- 604system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses 605system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses 606system.cpu.dcache.WriteReq_misses::cpu.data 93928 # number of WriteReq misses 607system.cpu.dcache.WriteReq_misses::total 93928 # number of WriteReq misses 608system.cpu.dcache.demand_misses::cpu.data 2785082 # number of demand (read+write) misses 609system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses 610system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses 611system.cpu.dcache.overall_misses::total 2785082 # number of overall misses |
| 612system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles 613system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles 615system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles 616system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles 617system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles 618system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles 619system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles | 612system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles 613system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles 615system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles 616system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles 617system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles 618system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles 619system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles |
| 620system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 624system.cpu.dcache.demand_accesses::cpu.data 70856129 # number of demand (read+write) accesses 625system.cpu.dcache.demand_accesses::total 70856129 # number of demand (read+write) accesses 626system.cpu.dcache.overall_accesses::cpu.data 70856129 # number of overall (read+write) accesses 627system.cpu.dcache.overall_accesses::total 70856129 # number of overall (read+write) accesses 628system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses 629system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses 630system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses 631system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses 632system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses 633system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses 634system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses 635system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses | 620system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 624system.cpu.dcache.demand_accesses::cpu.data 70856129 # number of demand (read+write) accesses 625system.cpu.dcache.demand_accesses::total 70856129 # number of demand (read+write) accesses 626system.cpu.dcache.overall_accesses::cpu.data 70856129 # number of overall (read+write) accesses 627system.cpu.dcache.overall_accesses::total 70856129 # number of overall (read+write) accesses 628system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses 629system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses 630system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses 631system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses 632system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses 633system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses 634system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses 635system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses |
| 636system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency 637system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency 638system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency 639system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked | 636system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency 637system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency 638system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency 639system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked |
| 645system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 645system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 648system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked | 648system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked |
| 649system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed 652system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks 653system.cpu.dcache.writebacks::total 2066601 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11884 # number of WriteReq MSHR hits --- 5 unchanged lines hidden (view full) --- 662system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses 663system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses 664system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses 665system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses 666system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 # number of demand (read+write) MSHR misses 667system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses 668system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses 669system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses | 649system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed 652system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks 653system.cpu.dcache.writebacks::total 2066601 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11884 # number of WriteReq MSHR hits --- 5 unchanged lines hidden (view full) --- 662system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses 663system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses 664system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses 665system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses 666system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 # number of demand (read+write) MSHR misses 667system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses 668system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses 669system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses |
| 670system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles 671system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles 672system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles 673system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles 674system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles 675system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles 676system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles 677system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles | 670system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles 671system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles 672system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles 673system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles 674system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles 675system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles 676system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles 677system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles |
| 678system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses 679system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses 680system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 681system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses 682system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses 683system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses 684system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses 685system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses | 678system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses 679system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses 680system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 681system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses 682system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses 683system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses 684system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses 685system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses |
| 686system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency 687system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency 688system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency 689system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency 690system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency 691system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency 693system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency | 686system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency 687system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency 688system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency 689system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency 690system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency 691system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency 693system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency |
| 694system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 695system.cpu.icache.tags.replacements 53 # number of replacements | 694system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 695system.cpu.icache.tags.replacements 53 # number of replacements |
| 696system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use | 696system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use |
| 697system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. 698system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. 699system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. 700system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 697system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. 698system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. 699system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. 700system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 701system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor | 701system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor |
| 702system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy 703system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy 704system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 707system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 708system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id 709system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 716system.cpu.icache.overall_hits::cpu.inst 27442569 # number of overall hits 717system.cpu.icache.overall_hits::total 27442569 # number of overall hits 718system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses 719system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses 720system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses 721system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses 722system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses 723system.cpu.icache.overall_misses::total 1323 # number of overall misses | 702system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy 703system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy 704system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 707system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 708system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id 709system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 716system.cpu.icache.overall_hits::cpu.inst 27442569 # number of overall hits 717system.cpu.icache.overall_hits::total 27442569 # number of overall hits 718system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses 719system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses 720system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses 721system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses 722system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses 723system.cpu.icache.overall_misses::total 1323 # number of overall misses |
| 724system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles 725system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles 726system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles 727system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles 728system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles 729system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles | 724system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles 725system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles 726system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles 727system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles 728system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles 729system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles |
| 730system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) 731system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) 732system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses 733system.cpu.icache.demand_accesses::total 27443892 # number of demand (read+write) accesses 734system.cpu.icache.overall_accesses::cpu.inst 27443892 # number of overall (read+write) accesses 735system.cpu.icache.overall_accesses::total 27443892 # number of overall (read+write) accesses 736system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 737system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 738system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 739system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 740system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 741system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses | 730system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) 731system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) 732system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses 733system.cpu.icache.demand_accesses::total 27443892 # number of demand (read+write) accesses 734system.cpu.icache.overall_accesses::cpu.inst 27443892 # number of overall (read+write) accesses 735system.cpu.icache.overall_accesses::total 27443892 # number of overall (read+write) accesses 736system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 737system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 738system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 739system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 740system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 741system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses |
| 742system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency 743system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency 744system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency 745system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency 746system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency 747system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency | 742system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency 743system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency 744system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency 745system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency 746system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency 747system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency |
| 748system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 749system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 750system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 751system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 752system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 753system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu.icache.fast_writes 0 # number of fast writes performed 755system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 760system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits 761system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits 762system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses 763system.cpu.icache.ReadReq_mshr_misses::total 1014 # number of ReadReq MSHR misses 764system.cpu.icache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses 765system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses 766system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses 767system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses | 748system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 749system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 750system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 751system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 752system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 753system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu.icache.fast_writes 0 # number of fast writes performed 755system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 760system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits 761system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits 762system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses 763system.cpu.icache.ReadReq_mshr_misses::total 1014 # number of ReadReq MSHR misses 764system.cpu.icache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses 765system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses 766system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses 767system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses |
| 768system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles 769system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles 770system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles 771system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles 772system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles 773system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles | 768system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles 769system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles 770system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles 771system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles 772system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles 773system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles |
| 774system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 775system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 776system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 777system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 778system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 779system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses | 774system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 775system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 776system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 777system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 778system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 779system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses |
| 780system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency 781system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency 782system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency 783system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency 784system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency 785system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency | 780system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency 781system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency 782system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency 783system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency 784system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency 785system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency |
| 786system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 787system.cpu.l2cache.tags.replacements 487 # number of replacements | 786system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 787system.cpu.l2cache.tags.replacements 487 # number of replacements |
| 788system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use | 788system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use |
| 789system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. 790system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. 791system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. 792system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 789system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. 790system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. 791system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. 792system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 793system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor | 793system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor |
| 796system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::2 780 # Occupied blocks per task id --- 25 unchanged lines hidden (view full) --- 829system.cpu.l2cache.ReadSharedReq_misses::cpu.data 426 # number of ReadSharedReq misses 830system.cpu.l2cache.ReadSharedReq_misses::total 426 # number of ReadSharedReq misses 831system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses 832system.cpu.l2cache.demand_misses::cpu.data 29424 # number of demand (read+write) misses 833system.cpu.l2cache.demand_misses::total 30422 # number of demand (read+write) misses 834system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses 835system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses 836system.cpu.l2cache.overall_misses::total 30422 # number of overall misses | 796system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::2 780 # Occupied blocks per task id --- 25 unchanged lines hidden (view full) --- 829system.cpu.l2cache.ReadSharedReq_misses::cpu.data 426 # number of ReadSharedReq misses 830system.cpu.l2cache.ReadSharedReq_misses::total 426 # number of ReadSharedReq misses 831system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses 832system.cpu.l2cache.demand_misses::cpu.data 29424 # number of demand (read+write) misses 833system.cpu.l2cache.demand_misses::total 30422 # number of demand (read+write) misses 834system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses 835system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses 836system.cpu.l2cache.overall_misses::total 30422 # number of overall misses |
| 837system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles 839system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles 840system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles 841system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles 842system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles 846system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles 847system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles | 837system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles 839system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles 840system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles 841system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles 842system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles 846system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles 847system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles |
| 849system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses) 856system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 869system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000214 # miss rate for ReadSharedReq accesses 870system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000214 # miss rate for ReadSharedReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 0.014171 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses | 849system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses) 856system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 869system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000214 # miss rate for ReadSharedReq accesses 870system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000214 # miss rate for ReadSharedReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 0.014171 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses |
| 877system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency 879system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency 880system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency 881system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency 882system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency | 877system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency 879system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency 880system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency 881system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency 882system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency |
| 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.fast_writes 0 # number of fast writes performed 896system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 905system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 426 # number of ReadSharedReq MSHR misses 906system.cpu.l2cache.ReadSharedReq_mshr_misses::total 426 # number of ReadSharedReq MSHR misses 907system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses 908system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::total 30422 # number of demand (read+write) MSHR misses 910system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses 911system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses | 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.fast_writes 0 # number of fast writes performed 896system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 905system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 426 # number of ReadSharedReq MSHR misses 906system.cpu.l2cache.ReadSharedReq_mshr_misses::total 426 # number of ReadSharedReq MSHR misses 907system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses 908system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::total 30422 # number of demand (read+write) MSHR misses 910system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses 911system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses |
| 913system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles 916system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles 917system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles 918system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles | 913system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles 916system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles 917system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles 918system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles |
| 925system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 926system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 927system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses 928system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses 929system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses 930system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses 931system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses 932system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses 933system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses 934system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses 935system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses 936system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses 937system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses 938system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses | 925system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 926system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 927system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses 928system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses 929system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses 930system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses 931system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses 932system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses 933system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses 934system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses 935system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses 936system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses 937system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses 938system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses |
| 939system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency 940system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency 941system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency 942system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency 943system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency 944system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency 946system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency 947system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency 949system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency 950system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency | 939system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency 940system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency 941system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency 942system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency 943system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency 944system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency 946system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency 947system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency 949system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency 950system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency |
| 951system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 951system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 952system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. 953system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. 954system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 955system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. 956system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 957system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 952system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution 960system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution 961system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) 963system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) 964system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64896 # Cumulative packet size per connected master and slave (bytes) 965system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) 966system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) 967system.cpu.toL2Bus.snoops 487 # Total snoops (count) 968system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram | 958system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution 960system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution 965system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution 966system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution 967system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) 969system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) 970system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64896 # Cumulative packet size per connected master and slave (bytes) 971system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) 972system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) 973system.cpu.toL2Bus.snoops 487 # Total snoops (count) 974system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram |
| 969system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram | 975system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram |
| 971system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 977system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 972system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram 974system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram | 978system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram 980system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 975system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 981system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 976system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 982system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 978system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram 979system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) 980system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 981system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) 982system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 983system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) 984system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) 985system.membus.trans_dist::ReadResp 1424 # Transaction distribution --- 14 unchanged lines hidden (view full) --- 1000system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1001system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1002system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1004system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1005system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1006system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1007system.membus.snoop_fanout::total 30636 # Request fanout histogram | 984system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram 985system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) 986system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 987system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) 988system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 989system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) 990system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) 991system.membus.trans_dist::ReadResp 1424 # Transaction distribution --- 14 unchanged lines hidden (view full) --- 1006system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1007system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1008system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram 1009system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1010system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1011system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1012system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1013system.membus.snoop_fanout::total 30636 # Request fanout histogram |
| 1008system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks) | 1014system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks) |
| 1009system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1010system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) 1011system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 1012 1013---------- End Simulation Statistics ---------- | 1015system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1016system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) 1017system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 1018 1019---------- End Simulation Statistics ---------- |