| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062113 # Number of seconds simulated 4sim_ticks 62113055500 # Number of ticks simulated 5final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 113198 # Simulator instruction rate (inst/s) 8host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) --- 543 unchanged lines hidden (view full) --- 552system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 554system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 555system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 559system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062113 # Number of seconds simulated 4sim_ticks 62113055500 # Number of ticks simulated 5final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 113198 # Simulator instruction rate (inst/s) 8host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) --- 543 unchanged lines hidden (view full) --- 552system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 554system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 555system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 559system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached |
| 560system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 561system.cpu.rob.rob_reads 419820689 # The number of ROB reads 562system.cpu.rob.rob_writes 657620446 # The number of ROB writes 563system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself 564system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling 565system.cpu.committedInsts 157988547 # Number of Instructions Simulated 566system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 567system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction 568system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads --- 423 unchanged lines hidden --- | 560system.cpu.rob.rob_reads 419820689 # The number of ROB reads 561system.cpu.rob.rob_writes 657620446 # The number of ROB writes 562system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling 564system.cpu.committedInsts 157988547 # Number of Instructions Simulated 565system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 566system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads --- 423 unchanged lines hidden --- |