| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061857 # Number of seconds simulated 4sim_ticks 61857343500 # Number of ticks simulated 5final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061857 # Number of seconds simulated 4sim_ticks 61857343500 # Number of ticks simulated 5final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 117254 # Simulator instruction rate (inst/s) 8host_op_rate 206466 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45908562 # Simulator tick rate (ticks/s) 10host_mem_usage 395064 # Number of bytes of host memory used 11host_seconds 1347.40 # Real time elapsed on the host | 7host_inst_rate 113051 # Simulator instruction rate (inst/s) 8host_op_rate 199065 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44263102 # Simulator tick rate (ticks/s) 10host_mem_usage 453712 # Number of bytes of host memory used 11host_seconds 1397.49 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory --- 197 unchanged lines hidden (view full) --- 217system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory --- 197 unchanged lines hidden (view full) --- 217system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads |
| 225system.physmem.totQLat 131010750 # Total ticks spent queuing 226system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM | 225system.physmem.totQLat 130999000 # Total ticks spent queuing 226system.physmem.totMemAccLat 700455250 # Total ticks spent from burst creation until serviced by the DRAM |
| 227system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers | 227system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers |
| 228system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst | 228system.physmem.avgQLat 4313.29 # Average queueing delay per DRAM burst |
| 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 230system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst | 230system.physmem.avgMemAccLat 23063.29 # Average memory access latency per DRAM burst |
| 231system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.25 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing 241system.physmem.readRowHits 27696 # Number of row buffer hits during reads 242system.physmem.writeRowHits 119 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes 245system.physmem.avgGap 2017525.41 # Average gap between requests 246system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined | 231system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.25 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing 241system.physmem.readRowHits 27696 # Number of row buffer hits during reads 242system.physmem.writeRowHits 119 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes 245system.physmem.avgGap 2017525.41 # Average gap between requests 246system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined |
| 247system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states 248system.physmem.memoryStateTime::REF 2065440000 # Time in different power states 249system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states 251system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.physmem.actEnergy::0 10939320 # Energy for activate commands per rank (pJ) 253system.physmem.actEnergy::1 9623880 # Energy for activate commands per rank (pJ) 254system.physmem.preEnergy::0 5968875 # Energy for precharge commands per rank (pJ) 255system.physmem.preEnergy::1 5251125 # Energy for precharge commands per rank (pJ) 256system.physmem.readEnergy::0 122226000 # Energy for read commands per rank (pJ) 257system.physmem.readEnergy::1 114246600 # Energy for read commands per rank (pJ) 258system.physmem.writeEnergy::0 1095120 # Energy for write commands per rank (pJ) 259system.physmem.writeEnergy::1 51840 # Energy for write commands per rank (pJ) 260system.physmem.refreshEnergy::0 4040000640 # Energy for refresh commands per rank (pJ) 261system.physmem.refreshEnergy::1 4040000640 # Energy for refresh commands per rank (pJ) 262system.physmem.actBackEnergy::0 2776037940 # Energy for active background per rank (pJ) 263system.physmem.actBackEnergy::1 2977033050 # Energy for active background per rank (pJ) 264system.physmem.preBackEnergy::0 34677417000 # Energy for precharge background per rank (pJ) 265system.physmem.preBackEnergy::1 34501105500 # Energy for precharge background per rank (pJ) 266system.physmem.totalEnergy::0 41633684895 # Total energy per rank (pJ) 267system.physmem.totalEnergy::1 41647312635 # Total energy per rank (pJ) 268system.physmem.averagePower::0 673.093577 # Core power per rank (mW) 269system.physmem.averagePower::1 673.313897 # Core power per rank (mW) 270system.membus.trans_dist::ReadReq 1465 # Transaction distribution 271system.membus.trans_dist::ReadResp 1462 # Transaction distribution 272system.membus.trans_dist::Writeback 197 # Transaction distribution 273system.membus.trans_dist::ReadExReq 28998 # Transaction distribution 274system.membus.trans_dist::ReadExResp 28998 # Transaction distribution 275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) 276system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) 277system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) 278system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) 279system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) 280system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) 281system.membus.snoops 0 # Total snoops (count) 282system.membus.snoop_fanout::samples 30660 # Request fanout histogram 283system.membus.snoop_fanout::mean 0 # Request fanout histogram 284system.membus.snoop_fanout::stdev 0 # Request fanout histogram 285system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 286system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram 287system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 288system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 289system.membus.snoop_fanout::min_value 0 # Request fanout histogram 290system.membus.snoop_fanout::max_value 0 # Request fanout histogram 291system.membus.snoop_fanout::total 30660 # Request fanout histogram 292system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) 293system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 294system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) 295system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 296system.cpu_clk_domain.clock 500 # Clock period in ticks | 247system.physmem_0.actEnergy 10939320 # Energy for activate commands per rank (pJ) 248system.physmem_0.preEnergy 5968875 # Energy for precharge commands per rank (pJ) 249system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) 250system.physmem_0.writeEnergy 1095120 # Energy for write commands per rank (pJ) 251system.physmem_0.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) 252system.physmem_0.actBackEnergy 2776043070 # Energy for active background per rank (pJ) 253system.physmem_0.preBackEnergy 34677412500 # Energy for precharge background per rank (pJ) 254system.physmem_0.totalEnergy 41633685525 # Total energy per rank (pJ) 255system.physmem_0.averagePower 673.093587 # Core power per rank (mW) 256system.physmem_0.memoryStateTime::IDLE 57673269750 # Time in different power states 257system.physmem_0.memoryStateTime::REF 2065440000 # Time in different power states 258system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 259system.physmem_0.memoryStateTime::ACT 2115534000 # Time in different power states 260system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 261system.physmem_1.actEnergy 9623880 # Energy for activate commands per rank (pJ) 262system.physmem_1.preEnergy 5251125 # Energy for precharge commands per rank (pJ) 263system.physmem_1.readEnergy 114246600 # Energy for read commands per rank (pJ) 264system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 265system.physmem_1.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) 266system.physmem_1.actBackEnergy 2977027920 # Energy for active background per rank (pJ) 267system.physmem_1.preBackEnergy 34501101750 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 41647303755 # Total energy per rank (pJ) 269system.physmem_1.averagePower 673.313903 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 57380456750 # Time in different power states 271system.physmem_1.memoryStateTime::REF 2065440000 # Time in different power states 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem_1.memoryStateTime::ACT 2409426750 # Time in different power states 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 297system.cpu.branchPred.lookups 37414357 # Number of BP lookups 298system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted 299system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect 300system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups 301system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits 302system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 303system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage 304system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. 305system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. | 275system.cpu.branchPred.lookups 37414357 # Number of BP lookups 276system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted 277system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect 278system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups 279system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits 280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 281system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage 282system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. 283system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. |
| 284system.cpu_clk_domain.clock 500 # Clock period in ticks |
|
| 306system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 307system.cpu.workload.num_syscalls 444 # Number of system calls 308system.cpu.numCycles 123714688 # number of cpu cycles simulated 309system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 310system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 285system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 286system.cpu.workload.num_syscalls 444 # Number of system calls 287system.cpu.numCycles 123714688 # number of cpu cycles simulated 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 311system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss | 290system.cpu.fetch.icacheStallCycles 28240185 # Number of cycles fetch is stalled on an Icache miss |
| 312system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed 313system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered 314system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken | 291system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed 292system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered 293system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken |
| 315system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked | 294system.cpu.fetch.Cycles 94568946 # Number of cycles fetch has run and was not squashing or blocked |
| 316system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing 317system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 318system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps 319system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions 320system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR 321system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched 322system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed 323system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) --- 10 unchanged lines hidden (view full) --- 334system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle 341system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle | 295system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing 296system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 297system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps 298system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions 299system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR 300system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched 301system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed 302system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) --- 10 unchanged lines hidden (view full) --- 313system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle 320system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle |
| 342system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle 343system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked | 321system.cpu.decode.IdleCycles 13285381 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 63221156 # Number of cycles decode is blocked |
| 344system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running 345system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking 346system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing 347system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode 348system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing | 323system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing 326system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode 327system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing |
| 349system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle | 328system.cpu.rename.IdleCycles 18592314 # Number of cycles rename is idle |
| 350system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running | 329system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking 330system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst 331system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running |
| 353system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking | 332system.cpu.rename.UnblockCycles 54481538 # Number of cycles rename is unblocking |
| 354system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full | 333system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename 334system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full 335system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full |
| 357system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full | 336system.cpu.rename.LQFullEvents 48119117 # Number of times rename has blocked due to LQ full |
| 358system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full 359system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 475 # count of serializing insts renamed --- 9 unchanged lines hidden (view full) --- 375system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 337system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full 338system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed 339system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made 340system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups 341system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups 342system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 343system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing 344system.cpu.rename.serializingInsts 475 # count of serializing insts renamed --- 9 unchanged lines hidden (view full) --- 354system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued 355system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling 356system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph 357system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed 358system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle | 362system.cpu.iq.issued_per_cycle::0 30107102 24.35% 24.35% # Number of insts issued each cycle |
| 384system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle | 363system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle |
| 385system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle | 364system.cpu.iq.issued_per_cycle::2 16727632 13.53% 53.68% # Number of insts issued each cycle |
| 386system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle | 365system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle |
| 387system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle | 366system.cpu.iq.issued_per_cycle::4 16031841 12.96% 80.45% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::5 12684150 10.26% 90.71% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::6 5762404 4.66% 95.37% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::7 4173789 3.38% 98.74% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::8 1554837 1.26% 100.00% # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle 375system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available | 376system.cpu.iq.fu_full::IntAlu 316999 7.53% 7.53% # attempts to use FU when none available |
| 398system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available --- 52 unchanged lines hidden (view full) --- 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued 460system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 464system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued 465system.cpu.iq.rate 2.489411 # Inst issue rate | 377system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available --- 52 unchanged lines hidden (view full) --- 437system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued 439system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued 440system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued 441system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 442system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 443system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued 444system.cpu.iq.rate 2.489411 # Inst issue rate |
| 466system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested | 445system.cpu.iq.fu_busy_cnt 4211172 # FU busy when requested |
| 467system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) | 446system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) |
| 468system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads | 447system.cpu.iq.int_inst_queue_reads 743874545 # Number of integer instruction queue reads |
| 469system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses | 448system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes 449system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses 450system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads 451system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes 452system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses |
| 474system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses | 453system.cpu.iq.int_alu_accesses 312154274 # Number of integer alu accesses |
| 475system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses | 454system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses |
| 476system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores | 455system.cpu.iew.lsq.thread0.forwLoads 58255905 # Number of loads that had data forwarded from stores |
| 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 478system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled --- 19 unchanged lines hidden (view full) --- 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed 506system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed 507system.cpu.iew.exec_branches 31536734 # Number of branches executed 508system.cpu.iew.exec_stores 33824606 # Number of stores executed 509system.cpu.iew.exec_rate 2.480687 # Inst execution rate 510system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back | 456system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 457system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed 458system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed 459system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations 460system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed 461system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 462system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 463system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled --- 19 unchanged lines hidden (view full) --- 483system.cpu.iew.exec_swp 0 # number of swp insts executed 484system.cpu.iew.exec_nop 0 # number of nop insts executed 485system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed 486system.cpu.iew.exec_branches 31536734 # Number of branches executed 487system.cpu.iew.exec_stores 33824606 # Number of stores executed 488system.cpu.iew.exec_rate 2.480687 # Inst execution rate 489system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit 490system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back |
| 512system.cpu.iew.wb_producers 231632885 # num instructions producing a value 513system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value | 491system.cpu.iew.wb_producers 231632886 # num instructions producing a value 492system.cpu.iew.wb_consumers 336126880 # num instructions consuming a value |
| 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 515system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle 516system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 518system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 117208008 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 493system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 494system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle 495system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back 496system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 497system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit 498system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 499system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted 500system.cpu.commit.committed_per_cycle::samples 117208008 # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 525system.cpu.commit.committed_per_cycle::0 52857680 45.10% 45.10% # Number of insts commited each cycle | 504system.cpu.commit.committed_per_cycle::0 52857679 45.10% 45.10% # Number of insts commited each cycle |
| 526system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle | 505system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle |
| 527system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle | 506system.cpu.commit.committed_per_cycle::2 10970811 9.36% 68.08% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::3 8748487 7.46% 75.54% # Number of insts commited each cycle |
| 529system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle | 508system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle |
| 530system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle | 509system.cpu.commit.committed_per_cycle::5 1731776 1.48% 78.66% # Number of insts commited each cycle |
| 531system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::total 117208008 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 157988547 # Number of instructions committed --- 56 unchanged lines hidden (view full) --- 595system.cpu.int_regfile_reads 493625454 # number of integer regfile reads 596system.cpu.int_regfile_writes 240898259 # number of integer regfile writes 597system.cpu.fp_regfile_reads 178 # number of floating regfile reads 598system.cpu.fp_regfile_writes 135 # number of floating regfile writes 599system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads 600system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes 601system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads 602system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 510system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::total 117208008 # Number of insts commited each cycle 517system.cpu.commit.committedInsts 157988547 # Number of instructions committed --- 56 unchanged lines hidden (view full) --- 574system.cpu.int_regfile_reads 493625454 # number of integer regfile reads 575system.cpu.int_regfile_writes 240898259 # number of integer regfile writes 576system.cpu.fp_regfile_reads 178 # number of floating regfile reads 577system.cpu.fp_regfile_writes 135 # number of floating regfile writes 578system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads 579system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes 580system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads 581system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 603system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution 608system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.snoops 0 # Total snoops (count) 615system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram 616system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 618system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram 628system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) 629system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 630system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) 631system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 632system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks) 633system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) | 582system.cpu.dcache.tags.replacements 2072433 # number of replacements 583system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use 584system.cpu.dcache.tags.total_refs 68459745 # Total number of references to valid blocks. 585system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. 586system.cpu.dcache.tags.avg_refs 32.968355 # Average number of references to valid blocks. 587system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. 588system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor 589system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy 590system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy 591system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 592system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id 593system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id 594system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 595system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 596system.cpu.dcache.tags.tag_accesses 144502465 # Number of tag accesses 597system.cpu.dcache.tags.data_accesses 144502465 # Number of data accesses 598system.cpu.dcache.ReadReq_hits::cpu.data 37113882 # number of ReadReq hits 599system.cpu.dcache.ReadReq_hits::total 37113882 # number of ReadReq hits 600system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits 601system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits 602system.cpu.dcache.demand_hits::cpu.data 68459745 # number of demand (read+write) hits 603system.cpu.dcache.demand_hits::total 68459745 # number of demand (read+write) hits 604system.cpu.dcache.overall_hits::cpu.data 68459745 # number of overall hits 605system.cpu.dcache.overall_hits::total 68459745 # number of overall hits 606system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses 607system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses 608system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses 609system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses 610system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses 611system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses 612system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses 613system.cpu.dcache.overall_misses::total 2753223 # number of overall misses 614system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861027000 # number of ReadReq miss cycles 615system.cpu.dcache.ReadReq_miss_latency::total 31861027000 # number of ReadReq miss cycles 616system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155494 # number of WriteReq miss cycles 617system.cpu.dcache.WriteReq_miss_latency::total 2765155494 # number of WriteReq miss cycles 618system.cpu.dcache.demand_miss_latency::cpu.data 34626182494 # number of demand (read+write) miss cycles 619system.cpu.dcache.demand_miss_latency::total 34626182494 # number of demand (read+write) miss cycles 620system.cpu.dcache.overall_miss_latency::cpu.data 34626182494 # number of overall miss cycles 621system.cpu.dcache.overall_miss_latency::total 34626182494 # number of overall miss cycles 622system.cpu.dcache.ReadReq_accesses::cpu.data 39773216 # number of ReadReq accesses(hits+misses) 623system.cpu.dcache.ReadReq_accesses::total 39773216 # number of ReadReq accesses(hits+misses) 624system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 625system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 626system.cpu.dcache.demand_accesses::cpu.data 71212968 # number of demand (read+write) accesses 627system.cpu.dcache.demand_accesses::total 71212968 # number of demand (read+write) accesses 628system.cpu.dcache.overall_accesses::cpu.data 71212968 # number of overall (read+write) accesses 629system.cpu.dcache.overall_accesses::total 71212968 # number of overall (read+write) accesses 630system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses 631system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses 632system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses 633system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses 634system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses 635system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses 636system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses 637system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses 638system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411 # average ReadReq miss latency 639system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411 # average ReadReq miss latency 640system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437 # average WriteReq miss latency 641system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437 # average WriteReq miss latency 642system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency 643system.cpu.dcache.demand_avg_miss_latency::total 12576.599314 # average overall miss latency 644system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::total 12576.599314 # average overall miss latency 646system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked 647system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 648system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 652system.cpu.dcache.fast_writes 0 # number of fast writes performed 653system.cpu.dcache.cache_copies 0 # number of cache copies performed 654system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks 655system.cpu.dcache.writebacks::total 2066654 # number of writebacks 656system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits 657system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits 658system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits 659system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits 660system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits 661system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits 662system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits 663system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits 664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses 665system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses 666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses 668system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses 669system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses 670system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses 671system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses 672system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009124500 # number of ReadReq MSHR miss cycles 673system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009124500 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972744 # number of WriteReq MSHR miss cycles 675system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972744 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524097244 # number of demand (read+write) MSHR miss cycles 677system.cpu.dcache.demand_mshr_miss_latency::total 24524097244 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524097244 # number of overall MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::total 24524097244 # number of overall MSHR miss cycles 680system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses 681system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses 685system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses 686system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses 687system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses 688system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780 # average ReadReq mshr miss latency 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780 # average ReadReq mshr miss latency 690system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317 # average WriteReq mshr miss latency 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317 # average WriteReq mshr miss latency 692system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency 694system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency 696system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 634system.cpu.icache.tags.replacements 62 # number of replacements 635system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use 636system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. 637system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. 638system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. 639system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 640system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor 641system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy --- 13 unchanged lines hidden (view full) --- 655system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits 656system.cpu.icache.overall_hits::total 27848273 # number of overall hits 657system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses 658system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses 659system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses 660system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses 661system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses 662system.cpu.icache.overall_misses::total 1347 # number of overall misses | 697system.cpu.icache.tags.replacements 62 # number of replacements 698system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use 699system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. 700system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. 701system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. 702system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 703system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor 704system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy --- 13 unchanged lines hidden (view full) --- 718system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits 719system.cpu.icache.overall_hits::total 27848273 # number of overall hits 720system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses 721system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses 722system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses 723system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses 724system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses 725system.cpu.icache.overall_misses::total 1347 # number of overall misses |
| 663system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles 664system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles 665system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles 666system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles 667system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles 668system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles | 726system.cpu.icache.ReadReq_miss_latency::cpu.inst 92877749 # number of ReadReq miss cycles 727system.cpu.icache.ReadReq_miss_latency::total 92877749 # number of ReadReq miss cycles 728system.cpu.icache.demand_miss_latency::cpu.inst 92877749 # number of demand (read+write) miss cycles 729system.cpu.icache.demand_miss_latency::total 92877749 # number of demand (read+write) miss cycles 730system.cpu.icache.overall_miss_latency::cpu.inst 92877749 # number of overall miss cycles 731system.cpu.icache.overall_miss_latency::total 92877749 # number of overall miss cycles |
| 669system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) 670system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) 671system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses 672system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses 673system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses 674system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses 675system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 676system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 677system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 678system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 679system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 680system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses | 732system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) 733system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) 734system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses 735system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses 736system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses 737system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses 738system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 739system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 740system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 741system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 742system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 743system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses |
| 681system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency 682system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency 683system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency 684system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency 685system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency 686system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency | 744system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68951.558278 # average ReadReq miss latency 745system.cpu.icache.ReadReq_avg_miss_latency::total 68951.558278 # average ReadReq miss latency 746system.cpu.icache.demand_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency 747system.cpu.icache.demand_avg_miss_latency::total 68951.558278 # average overall miss latency 748system.cpu.icache.overall_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency 749system.cpu.icache.overall_avg_miss_latency::total 68951.558278 # average overall miss latency |
| 687system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked 688system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 690system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked 692system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.cpu.icache.fast_writes 0 # number of fast writes performed 694system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 699system.cpu.icache.overall_mshr_hits::cpu.inst 321 # number of overall MSHR hits 700system.cpu.icache.overall_mshr_hits::total 321 # number of overall MSHR hits 701system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026 # number of ReadReq MSHR misses 702system.cpu.icache.ReadReq_mshr_misses::total 1026 # number of ReadReq MSHR misses 703system.cpu.icache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses 704system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses 705system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses 706system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses | 750system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked 751system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 753system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked 755system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.icache.fast_writes 0 # number of fast writes performed 757system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 762system.cpu.icache.overall_mshr_hits::cpu.inst 321 # number of overall MSHR hits 763system.cpu.icache.overall_mshr_hits::total 321 # number of overall MSHR hits 764system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026 # number of ReadReq MSHR misses 765system.cpu.icache.ReadReq_mshr_misses::total 1026 # number of ReadReq MSHR misses 766system.cpu.icache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses 767system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses 768system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses 769system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses |
| 707system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72336999 # number of ReadReq MSHR miss cycles 708system.cpu.icache.ReadReq_mshr_miss_latency::total 72336999 # number of ReadReq MSHR miss cycles 709system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72336999 # number of demand (read+write) MSHR miss cycles 710system.cpu.icache.demand_mshr_miss_latency::total 72336999 # number of demand (read+write) MSHR miss cycles 711system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72336999 # number of overall MSHR miss cycles 712system.cpu.icache.overall_mshr_miss_latency::total 72336999 # number of overall MSHR miss cycles | 770system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72330999 # number of ReadReq MSHR miss cycles 771system.cpu.icache.ReadReq_mshr_miss_latency::total 72330999 # number of ReadReq MSHR miss cycles 772system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72330999 # number of demand (read+write) MSHR miss cycles 773system.cpu.icache.demand_mshr_miss_latency::total 72330999 # number of demand (read+write) MSHR miss cycles 774system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72330999 # number of overall MSHR miss cycles 775system.cpu.icache.overall_mshr_miss_latency::total 72330999 # number of overall MSHR miss cycles |
| 713system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 714system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 715system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 716system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 717system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 718system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses | 776system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 777system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 778system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 779system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 780system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 781system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses |
| 719system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661 # average ReadReq mshr miss latency 720system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661 # average ReadReq mshr miss latency 721system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency 722system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency 723system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency 724system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency | 782system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70498.049708 # average ReadReq mshr miss latency 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70498.049708 # average ReadReq mshr miss latency 784system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency 786system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency |
| 725system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 726system.cpu.l2cache.tags.replacements 515 # number of replacements | 788system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 789system.cpu.l2cache.tags.replacements 515 # number of replacements |
| 727system.cpu.l2cache.tags.tagsinuse 20693.420536 # Cycle average of tags in use | 790system.cpu.l2cache.tags.tagsinuse 20693.420547 # Cycle average of tags in use |
| 728system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. 729system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. 730system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. 731system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 791system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. 792system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. 793system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. 794system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 732system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871 # Average occupied blocks per requestor | 795system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319882 # Average occupied blocks per requestor |
| 733system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor 734system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor 735system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy 736system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020813 # Average percentage of cache occupancy 737system.cpu.l2cache.tags.occ_percent::cpu.data 0.007602 # Average percentage of cache occupancy 738system.cpu.l2cache.tags.occ_percent::total 0.631513 # Average percentage of cache occupancy 739system.cpu.l2cache.tags.occ_task_id_blocks::1024 29929 # Occupied blocks per task id 740system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id --- 23 unchanged lines hidden (view full) --- 764system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses 765system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses 766system.cpu.l2cache.demand_misses::cpu.inst 1010 # number of demand (read+write) misses 767system.cpu.l2cache.demand_misses::cpu.data 29453 # number of demand (read+write) misses 768system.cpu.l2cache.demand_misses::total 30463 # number of demand (read+write) misses 769system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses 770system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses 771system.cpu.l2cache.overall_misses::total 30463 # number of overall misses | 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor 797system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor 798system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020813 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::cpu.data 0.007602 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::total 0.631513 # Average percentage of cache occupancy 802system.cpu.l2cache.tags.occ_task_id_blocks::1024 29929 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id --- 23 unchanged lines hidden (view full) --- 827system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses 828system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses 829system.cpu.l2cache.demand_misses::cpu.inst 1010 # number of demand (read+write) misses 830system.cpu.l2cache.demand_misses::cpu.data 29453 # number of demand (read+write) misses 831system.cpu.l2cache.demand_misses::total 30463 # number of demand (read+write) misses 832system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses 833system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses 834system.cpu.l2cache.overall_misses::total 30463 # number of overall misses |
| 772system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71141750 # number of ReadReq miss cycles 773system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31680000 # number of ReadReq miss cycles 774system.cpu.l2cache.ReadReq_miss_latency::total 102821750 # number of ReadReq miss cycles 775system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914500 # number of ReadExReq miss cycles 776system.cpu.l2cache.ReadExReq_miss_latency::total 1901914500 # number of ReadExReq miss cycles 777system.cpu.l2cache.demand_miss_latency::cpu.inst 71141750 # number of demand (read+write) miss cycles 778system.cpu.l2cache.demand_miss_latency::cpu.data 1933594500 # number of demand (read+write) miss cycles 779system.cpu.l2cache.demand_miss_latency::total 2004736250 # number of demand (read+write) miss cycles 780system.cpu.l2cache.overall_miss_latency::cpu.inst 71141750 # number of overall miss cycles 781system.cpu.l2cache.overall_miss_latency::cpu.data 1933594500 # number of overall miss cycles 782system.cpu.l2cache.overall_miss_latency::total 2004736250 # number of overall miss cycles | 835system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71135750 # number of ReadReq miss cycles 836system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31674000 # number of ReadReq miss cycles 837system.cpu.l2cache.ReadReq_miss_latency::total 102809750 # number of ReadReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914750 # number of ReadExReq miss cycles 839system.cpu.l2cache.ReadExReq_miss_latency::total 1901914750 # number of ReadExReq miss cycles 840system.cpu.l2cache.demand_miss_latency::cpu.inst 71135750 # number of demand (read+write) miss cycles 841system.cpu.l2cache.demand_miss_latency::cpu.data 1933588750 # number of demand (read+write) miss cycles 842system.cpu.l2cache.demand_miss_latency::total 2004724500 # number of demand (read+write) miss cycles 843system.cpu.l2cache.overall_miss_latency::cpu.inst 71135750 # number of overall miss cycles 844system.cpu.l2cache.overall_miss_latency::cpu.data 1933588750 # number of overall miss cycles 845system.cpu.l2cache.overall_miss_latency::total 2004724500 # number of overall miss cycles |
| 783system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses) 785system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses) 786system.cpu.l2cache.Writeback_accesses::writebacks 2066654 # number of Writeback accesses(hits+misses) 787system.cpu.l2cache.Writeback_accesses::total 2066654 # number of Writeback accesses(hits+misses) 788system.cpu.l2cache.ReadExReq_accesses::cpu.data 82065 # number of ReadExReq accesses(hits+misses) 789system.cpu.l2cache.ReadExReq_accesses::total 82065 # number of ReadExReq accesses(hits+misses) 790system.cpu.l2cache.demand_accesses::cpu.inst 1026 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 799system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353354 # miss rate for ReadExReq accesses 800system.cpu.l2cache.ReadExReq_miss_rate::total 0.353354 # miss rate for ReadExReq accesses 801system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984405 # miss rate for demand accesses 802system.cpu.l2cache.demand_miss_rate::cpu.data 0.014184 # miss rate for demand accesses 803system.cpu.l2cache.demand_miss_rate::total 0.014663 # miss rate for demand accesses 804system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses 805system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses 806system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses | 846system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses) 847system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.Writeback_accesses::writebacks 2066654 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 2066654 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.ReadExReq_accesses::cpu.data 82065 # number of ReadExReq accesses(hits+misses) 852system.cpu.l2cache.ReadExReq_accesses::total 82065 # number of ReadExReq accesses(hits+misses) 853system.cpu.l2cache.demand_accesses::cpu.inst 1026 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 862system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353354 # miss rate for ReadExReq accesses 863system.cpu.l2cache.ReadExReq_miss_rate::total 0.353354 # miss rate for ReadExReq accesses 864system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984405 # miss rate for demand accesses 865system.cpu.l2cache.demand_miss_rate::cpu.data 0.014184 # miss rate for demand accesses 866system.cpu.l2cache.demand_miss_rate::total 0.014663 # miss rate for demand accesses 867system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses 868system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses 869system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses |
| 807system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238 # average ReadReq miss latency 808system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626 # average ReadReq miss latency 809system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881 # average ReadReq miss latency 810system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916 # average ReadExReq miss latency 811system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916 # average ReadExReq miss latency 812system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency 813system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency 814system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114 # average overall miss latency 815system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency 816system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency 817system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114 # average overall miss latency | 870system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70431.435644 # average ReadReq miss latency 871system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69613.186813 # average ReadReq miss latency 872system.cpu.l2cache.ReadReq_avg_miss_latency::total 70177.303754 # average ReadReq miss latency 873system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.790537 # average ReadExReq miss latency 874system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.790537 # average ReadExReq miss latency 875system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency 876system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency 877system.cpu.l2cache.demand_avg_miss_latency::total 65808.505400 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency 879system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency 880system.cpu.l2cache.overall_avg_miss_latency::total 65808.505400 # average overall miss latency |
| 818system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 819system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 821system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 822system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 823system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 824system.cpu.l2cache.fast_writes 0 # number of fast writes performed 825system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 831system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses 832system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses 833system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses 834system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses 837system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses 838system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses | 881system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 883system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 884system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 885system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 886system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 887system.cpu.l2cache.fast_writes 0 # number of fast writes performed 888system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 894system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses 895system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses 896system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses 897system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses 898system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses 899system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses 900system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses 901system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses |
| 839system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles 840system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles 841system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles 842system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles 843system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles 846system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles 849system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles | 902system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58476750 # number of ReadReq MSHR miss cycles 903system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26090500 # number of ReadReq MSHR miss cycles 904system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84567250 # number of ReadReq MSHR miss cycles 905system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042250 # number of ReadExReq MSHR miss cycles 906system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042250 # number of ReadExReq MSHR miss cycles 907system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58476750 # number of demand (read+write) MSHR miss cycles 908system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556132750 # number of demand (read+write) MSHR miss cycles 909system.cpu.l2cache.demand_mshr_miss_latency::total 1614609500 # number of demand (read+write) MSHR miss cycles 910system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58476750 # number of overall MSHR miss cycles 911system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556132750 # number of overall MSHR miss cycles 912system.cpu.l2cache.overall_mshr_miss_latency::total 1614609500 # number of overall MSHR miss cycles |
| 850system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses 851system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses 852system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses 853system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses 854system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses 855system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses 856system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses 857system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses 858system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses 859system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses 860system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses | 913system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses 914system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses 915system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses 916system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses 917system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses 918system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses 919system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses 920system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses 921system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses 922system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses 923system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses |
| 861system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency 862system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency 863system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency 865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency | 924system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277 # average ReadReq mshr miss latency 925system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242 # average ReadReq mshr miss latency 926system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57725.085324 # average ReadReq mshr miss latency 927system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.716463 # average ReadExReq mshr miss latency 928system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.716463 # average ReadExReq mshr miss latency 929system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency 930system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency 931system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency 932system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency 933system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency 934system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency |
| 872system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 935system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 873system.cpu.dcache.tags.replacements 2072433 # number of replacements 874system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use 875system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks. 876system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. 877system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks. 878system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. 879system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor 880system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy 881system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy 882system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 883system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id 884system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id 885system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 886system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 887system.cpu.dcache.tags.tag_accesses 144502463 # Number of tag accesses 888system.cpu.dcache.tags.data_accesses 144502463 # Number of data accesses 889system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits 890system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits 891system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits 892system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits 893system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits 894system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits 895system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits 896system.cpu.dcache.overall_hits::total 68459744 # number of overall hits 897system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses 898system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses 899system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses 900system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses 901system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses 902system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses 903system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses 904system.cpu.dcache.overall_misses::total 2753223 # number of overall misses 905system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles 906system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles 907system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles 908system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles 909system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles 910system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles 911system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles 912system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles 913system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses) 914system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses) 915system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 916system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 917system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses 918system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses 919system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses 920system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses 921system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses 922system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses 923system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses 924system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses 925system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses 926system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses 927system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses 928system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses 929system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency 930system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency 931system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency 932system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency 933system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency 934system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency 935system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency 936system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency 937system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked 938system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 939system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked 940system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 941system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked 942system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 943system.cpu.dcache.fast_writes 0 # number of fast writes performed 944system.cpu.dcache.cache_copies 0 # number of cache copies performed 945system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks 946system.cpu.dcache.writebacks::total 2066654 # number of writebacks 947system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits 948system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits 949system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits 950system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits 951system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits 952system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits 953system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits 954system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits 955system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses 956system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses 957system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses 958system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses 959system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses 960system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses 961system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses 962system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses 963system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles 964system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles 965system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles 966system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles 967system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles 968system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles 969system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles 970system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles 971system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses 972system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses 973system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses 974system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses 975system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses 976system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses 977system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses 978system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses 979system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency 980system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency 981system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency 982system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency 983system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency 984system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency 985system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency 986system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency 987system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 936system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution 941system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) 944system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) 947system.cpu.toL2Bus.snoops 0 # Total snoops (count) 948system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 960system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram 961system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) 962system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 963system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) 964system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 965system.cpu.toL2Bus.respLayer1.occupancy 3121417250 # Layer occupancy (ticks) 966system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) 967system.membus.trans_dist::ReadReq 1465 # Transaction distribution 968system.membus.trans_dist::ReadResp 1462 # Transaction distribution 969system.membus.trans_dist::Writeback 197 # Transaction distribution 970system.membus.trans_dist::ReadExReq 28998 # Transaction distribution 971system.membus.trans_dist::ReadExResp 28998 # Transaction distribution 972system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) 973system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) 974system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) 975system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) 976system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) 977system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) 978system.membus.snoops 0 # Total snoops (count) 979system.membus.snoop_fanout::samples 30660 # Request fanout histogram 980system.membus.snoop_fanout::mean 0 # Request fanout histogram 981system.membus.snoop_fanout::stdev 0 # Request fanout histogram 982system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 983system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram 984system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 985system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 986system.membus.snoop_fanout::min_value 0 # Request fanout histogram 987system.membus.snoop_fanout::max_value 0 # Request fanout histogram 988system.membus.snoop_fanout::total 30660 # Request fanout histogram 989system.membus.reqLayer0.occupancy 43499500 # Layer occupancy (ticks) 990system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 991system.membus.respLayer1.occupancy 291787500 # Layer occupancy (ticks) 992system.membus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 988 989---------- End Simulation Statistics ---------- | 993 994---------- End Simulation Statistics ---------- |