| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.065578 # Number of seconds simulated 4sim_ticks 65578127500 # Number of ticks simulated 5final_tick 65578127500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.065585 # Number of seconds simulated 4sim_ticks 65585340000 # Number of ticks simulated 5final_tick 65585340000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 88175 # Simulator instruction rate (inst/s) 8host_op_rate 155262 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36599742 # Simulator tick rate (ticks/s) 10host_mem_usage 427692 # Number of bytes of host memory used 11host_seconds 1791.76 # Real time elapsed on the host | 7host_inst_rate 87128 # Simulator instruction rate (inst/s) 8host_op_rate 153419 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36169402 # Simulator tick rate (ticks/s) 10host_mem_usage 428764 # Number of bytes of host memory used 11host_seconds 1813.28 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 63744 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1882880 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1946624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 63744 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 63744 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 10368 # Number of bytes written to this memory 22system.physmem.bytes_written::total 10368 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 996 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29420 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30416 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 162 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 162 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 972031 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 28712012 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 29684044 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 972031 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 972031 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 158101 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 158101 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 158101 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 972031 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 28712012 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 29842145 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30418 # Number of read requests accepted 40system.physmem.writeReqs 162 # Number of write requests accepted 41system.physmem.readBursts 30418 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 162 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1942912 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 3840 # Total number of bytes read from write queue 45system.physmem.bytesWritten 8384 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1946752 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 10368 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 60 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1883456 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory 22system.physmem.bytes_written::total 11200 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29429 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 175 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 976804 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 28717637 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 29694441 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 976804 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 976804 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 170770 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 170770 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 170770 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 976804 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 28717637 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 29865211 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30432 # Number of read requests accepted 40system.physmem.writeReqs 175 # Number of write requests accepted 41system.physmem.readBursts 30432 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1942848 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 4800 # Total number of bytes read from write queue 45system.physmem.bytesWritten 10048 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1947648 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 51system.physmem.perBankRdBursts::0 1927 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2065 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2026 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1928 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2026 # Per bank write bursts | 51system.physmem.perBankRdBursts::0 1922 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2061 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2029 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1929 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2025 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 1900 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 1900 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::6 1961 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1862 # Per bank write bursts | 57system.physmem.perBankRdBursts::6 1964 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1863 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::8 1940 # Per bank write bursts | 59system.physmem.perBankRdBursts::8 1940 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::9 1933 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1805 # Per bank write bursts | 60system.physmem.perBankRdBursts::9 1934 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1804 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::11 1796 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts | 62system.physmem.perBankRdBursts::11 1796 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts |
| 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1779 # Per bank write bursts 67system.physmem.perBankWrBursts::0 10 # Per bank write bursts 68system.physmem.perBankWrBursts::1 71 # Per bank write bursts 69system.physmem.perBankWrBursts::2 3 # Per bank write bursts 70system.physmem.perBankWrBursts::3 17 # Per bank write bursts 71system.physmem.perBankWrBursts::4 12 # Per bank write bursts | 65system.physmem.perBankRdBursts::14 1820 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 67system.physmem.perBankWrBursts::0 7 # Per bank write bursts 68system.physmem.perBankWrBursts::1 84 # Per bank write bursts 69system.physmem.perBankWrBursts::2 9 # Per bank write bursts 70system.physmem.perBankWrBursts::3 29 # Per bank write bursts 71system.physmem.perBankWrBursts::4 7 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::5 0 # Per bank write bursts | 72system.physmem.perBankWrBursts::5 0 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::6 10 # Per bank write bursts | 73system.physmem.perBankWrBursts::6 12 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::9 5 # Per bank write bursts | 76system.physmem.perBankWrBursts::9 6 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 65578111000 # Total gap between requests | 85system.physmem.totGap 65585323000 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 30418 # Read request sizes (log2) | 92system.physmem.readPktSize::6 30432 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 162 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29902 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 175 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 357 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see |
| 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see |
| 157system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see | 157system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see |
| 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see --- 4 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see --- 4 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 1672 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 934.162679 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 823.717230 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 264.349754 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 77 4.61% 4.61% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 54 3.23% 7.83% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 19 1.14% 8.97% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 10 0.60% 9.57% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 11 0.66% 10.23% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 5 0.30% 10.53% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 6 0.36% 10.89% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 4 0.24% 11.12% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1486 88.88% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 1672 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 4327.142857 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 47.742498 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 11404.448466 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 6 85.71% 85.71% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 14.29% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 18.714286 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 18.459831 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 3.545621 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 3 42.86% 42.86% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::19 3 42.86% 85.71% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::26 1 14.29% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads 225system.physmem.totQLat 98355750 # Total ticks spent queuing 226system.physmem.totMemAccLat 704267000 # Total ticks spent from burst creation until serviced by the DRAM 227system.physmem.totBusLat 151790000 # Total ticks spent in databus transfers 228system.physmem.totBankLat 454121250 # Total ticks spent accessing banks 229system.physmem.avgQLat 3239.86 # Average queueing delay per DRAM burst 230system.physmem.avgBankLat 14958.87 # Average bank access latency per DRAM burst | 196system.physmem.bytesPerActivate::samples 2701 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 722.766383 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 519.037520 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 387.855736 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 380 14.07% 14.07% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 203 7.52% 21.58% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 114 4.22% 25.81% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 105 3.89% 29.69% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 110 4.07% 33.77% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 132 4.89% 38.65% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 83 3.07% 41.73% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 80 2.96% 44.69% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1494 55.31% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2701 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 3366.777778 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 25.330646 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 10057.961719 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.444444 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.423969 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.881917 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2 22.22% 22.22% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 1 11.11% 33.33% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 6 66.67% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads 225system.physmem.totQLat 122012500 # Total ticks spent queuing 226system.physmem.totMemAccLat 691206250 # Total ticks spent from burst creation until serviced by the DRAM 227system.physmem.totBusLat 151785000 # Total ticks spent in databus transfers 228system.physmem.avgQLat 4019.25 # Average queueing delay per DRAM burst |
| 231system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 232system.physmem.avgMemAccLat 23198.73 # Average memory access latency per DRAM burst 233system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s 234system.physmem.avgWrBW 0.13 # Average achieved write bandwidth in MiByte/s 235system.physmem.avgRdBWSys 29.69 # Average system read bandwidth in MiByte/s 236system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s | 230system.physmem.avgMemAccLat 22769.25 # Average memory access latency per DRAM burst 231system.physmem.avgRdBW 29.62 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s |
| 237system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 238system.physmem.busUtil 0.23 # Data bus utilization in percentage 239system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads 240system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.23 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 241system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 242system.physmem.avgWrQLen 15.72 # Average write queue length when enqueuing 243system.physmem.readRowHits 27690 # Number of row buffer hits during reads 244system.physmem.writeRowHits 93 # Number of row buffer hits during writes 245system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads 246system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes 247system.physmem.avgGap 2144477.14 # Average gap between requests 248system.physmem.pageHitRate 91.03 # Row buffer hit rate, read and write combined 249system.physmem.prechargeAllPercent 1.03 # Percentage of time for which DRAM has all the banks in precharge state 250system.membus.throughput 29841169 # Throughput (bytes/s) 251system.membus.trans_dist::ReadReq 1415 # Transaction distribution 252system.membus.trans_dist::ReadResp 1412 # Transaction distribution 253system.membus.trans_dist::Writeback 162 # Transaction distribution 254system.membus.trans_dist::ReadExReq 29003 # Transaction distribution 255system.membus.trans_dist::ReadExResp 29003 # Transaction distribution 256system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60995 # Packet count per connected master and slave (bytes) 257system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60995 # Packet count per connected master and slave (bytes) 258system.membus.pkt_count::total 60995 # Packet count per connected master and slave (bytes) 259system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956928 # Cumulative packet size per connected master and slave (bytes) 260system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956928 # Cumulative packet size per connected master and slave (bytes) 261system.membus.tot_pkt_size::total 1956928 # Cumulative packet size per connected master and slave (bytes) 262system.membus.data_through_bus 1956928 # Total data (bytes) | 239system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 15.09 # Average write queue length when enqueuing 241system.physmem.readRowHits 27699 # Number of row buffer hits during reads 242system.physmem.writeRowHits 110 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 91.24 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 62.86 # Row buffer hit rate for writes 245system.physmem.avgGap 2142821.02 # Average gap between requests 246system.physmem.pageHitRate 91.08 # Row buffer hit rate, read and write combined 247system.physmem.memoryStateTime::IDLE 59149173500 # Time in different power states 248system.physmem.memoryStateTime::REF 2189980000 # Time in different power states 249system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem.memoryStateTime::ACT 4244704000 # Time in different power states 251system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.membus.throughput 29864235 # Throughput (bytes/s) 253system.membus.trans_dist::ReadReq 1427 # Transaction distribution 254system.membus.trans_dist::ReadResp 1424 # Transaction distribution 255system.membus.trans_dist::Writeback 175 # Transaction distribution 256system.membus.trans_dist::ReadExReq 29005 # Transaction distribution 257system.membus.trans_dist::ReadExResp 29005 # Transaction distribution 258system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61036 # Packet count per connected master and slave (bytes) 259system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61036 # Packet count per connected master and slave (bytes) 260system.membus.pkt_count::total 61036 # Packet count per connected master and slave (bytes) 261system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958656 # Cumulative packet size per connected master and slave (bytes) 262system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1958656 # Cumulative packet size per connected master and slave (bytes) 263system.membus.tot_pkt_size::total 1958656 # Cumulative packet size per connected master and slave (bytes) 264system.membus.data_through_bus 1958656 # Total data (bytes) |
| 263system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 265system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 264system.membus.reqLayer0.occupancy 34882000 # Layer occupancy (ticks) | 266system.membus.reqLayer0.occupancy 35026000 # Layer occupancy (ticks) |
| 265system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 267system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 266system.membus.respLayer1.occupancy 284250750 # Layer occupancy (ticks) | 268system.membus.respLayer1.occupancy 284359000 # Layer occupancy (ticks) |
| 267system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 269system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 270system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.branchPred.lookups 33848859 # Number of BP lookups 270system.cpu.branchPred.condPredicted 33848859 # Number of conditional branches predicted 271system.cpu.branchPred.condIncorrect 773675 # Number of conditional branches incorrect 272system.cpu.branchPred.BTBLookups 19289255 # Number of BTB lookups 273system.cpu.branchPred.BTBHits 19197917 # Number of BTB hits | 271system.cpu.branchPred.lookups 33857939 # Number of BP lookups 272system.cpu.branchPred.condPredicted 33857939 # Number of conditional branches predicted 273system.cpu.branchPred.condIncorrect 774699 # Number of conditional branches incorrect 274system.cpu.branchPred.BTBLookups 19294742 # Number of BTB lookups 275system.cpu.branchPred.BTBHits 19202488 # Number of BTB hits |
| 274system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 276system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 275system.cpu.branchPred.BTBHitPct 99.526482 # BTB Hit Percentage 276system.cpu.branchPred.usedRAS 5013789 # Number of times the RAS was used to get a target. 277system.cpu.branchPred.RASInCorrect 5382 # Number of incorrect RAS predictions. | 277system.cpu.branchPred.BTBHitPct 99.521870 # BTB Hit Percentage 278system.cpu.branchPred.usedRAS 5017287 # Number of times the RAS was used to get a target. 279system.cpu.branchPred.RASInCorrect 5447 # Number of incorrect RAS predictions. |
| 278system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 279system.cpu.workload.num_syscalls 444 # Number of system calls | 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 281system.cpu.workload.num_syscalls 444 # Number of system calls |
| 280system.cpu.numCycles 131156258 # number of cpu cycles simulated | 282system.cpu.numCycles 131170685 # number of cpu cycles simulated |
| 281system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 282system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 283system.cpu.fetch.icacheStallCycles 26124618 # Number of cycles fetch is stalled on an Icache miss 284system.cpu.fetch.Insts 182201449 # Number of instructions fetch has processed 285system.cpu.fetch.Branches 33848859 # Number of branches that fetch encountered 286system.cpu.fetch.predictedBranches 24211706 # Number of branches that fetch has predicted taken 287system.cpu.fetch.Cycles 55441130 # Number of cycles fetch has run and was not squashing or blocked 288system.cpu.fetch.SquashCycles 5339784 # Number of cycles fetch has spent squashing 289system.cpu.fetch.BlockedCycles 44953696 # Number of cycles fetch has spent blocked 290system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 291system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps | 285system.cpu.fetch.icacheStallCycles 26133192 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 182246280 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 33857939 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 24219775 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 55455334 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 5351155 # Number of cycles fetch has spent squashing 291system.cpu.fetch.BlockedCycles 44937204 # Number of cycles fetch has spent blocked 292system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 293system.cpu.fetch.PendingTrapStallCycles 289 # Number of stall cycles due to pending traps |
| 292system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR | 294system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR |
| 293system.cpu.fetch.CacheLines 25565447 # Number of cache lines fetched 294system.cpu.fetch.IcacheSquashes 166050 # Number of outstanding Icache misses that were squashed 295system.cpu.fetch.rateDist::samples 131050652 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::mean 2.451103 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::stdev 3.313857 # Number of instructions fetched each cycle (Total) | 295system.cpu.fetch.CacheLines 25572777 # Number of cache lines fetched 296system.cpu.fetch.IcacheSquashes 166462 # Number of outstanding Icache misses that were squashed 297system.cpu.fetch.rateDist::samples 131067108 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::mean 2.451414 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::stdev 3.313936 # Number of instructions fetched each cycle (Total) |
| 298system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 300system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 299system.cpu.fetch.rateDist::0 78085477 59.58% 59.58% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::1 1960121 1.50% 61.08% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::2 2941365 2.24% 63.32% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::3 3832581 2.92% 66.25% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::4 7765611 5.93% 72.17% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::5 4754905 3.63% 75.80% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::6 2663892 2.03% 77.84% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::7 1315906 1.00% 78.84% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::8 27730794 21.16% 100.00% # Number of instructions fetched each cycle (Total) | 301system.cpu.fetch.rateDist::0 78089059 59.58% 59.58% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::1 1960403 1.50% 61.08% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::2 2941378 2.24% 63.32% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::3 3833422 2.92% 66.24% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::4 7766051 5.93% 72.17% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::5 4756858 3.63% 75.80% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::6 2667148 2.03% 77.83% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::7 1317375 1.01% 78.84% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::8 27735414 21.16% 100.00% # Number of instructions fetched each cycle (Total) |
| 308system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 310system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 311system.cpu.fetch.rateDist::total 131050652 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.branchRate 0.258080 # Number of branch fetches per cycle 313system.cpu.fetch.rate 1.389194 # Number of inst fetches per cycle 314system.cpu.decode.IdleCycles 36811004 # Number of cycles decode is idle 315system.cpu.decode.BlockedCycles 37176024 # Number of cycles decode is blocked 316system.cpu.decode.RunCycles 43889002 # Number of cycles decode is running 317system.cpu.decode.UnblockCycles 8643749 # Number of cycles decode is unblocking 318system.cpu.decode.SquashCycles 4530873 # Number of cycles decode is squashing 319system.cpu.decode.DecodedInsts 318736109 # Number of instructions handled by decode 320system.cpu.rename.SquashCycles 4530873 # Number of cycles rename is squashing 321system.cpu.rename.IdleCycles 42298555 # Number of cycles rename is idle 322system.cpu.rename.BlockCycles 9762867 # Number of cycles rename is blocking 323system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst 324system.cpu.rename.RunCycles 46737142 # Number of cycles rename is running 325system.cpu.rename.UnblockCycles 27713810 # Number of cycles rename is unblocking 326system.cpu.rename.RenamedInsts 314904511 # Number of instructions processed by rename | 313system.cpu.fetch.rateDist::total 131067108 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.branchRate 0.258121 # Number of branch fetches per cycle 315system.cpu.fetch.rate 1.389383 # Number of inst fetches per cycle 316system.cpu.decode.IdleCycles 36820362 # Number of cycles decode is idle 317system.cpu.decode.BlockedCycles 37159698 # Number of cycles decode is blocked 318system.cpu.decode.RunCycles 43897766 # Number of cycles decode is running 319system.cpu.decode.UnblockCycles 8648241 # Number of cycles decode is unblocking 320system.cpu.decode.SquashCycles 4541041 # Number of cycles decode is squashing 321system.cpu.decode.DecodedInsts 318820485 # Number of instructions handled by decode 322system.cpu.rename.SquashCycles 4541041 # Number of cycles rename is squashing 323system.cpu.rename.IdleCycles 42311218 # Number of cycles rename is idle 324system.cpu.rename.BlockCycles 9731436 # Number of cycles rename is blocking 325system.cpu.rename.serializeStallCycles 7378 # count of cycles rename stalled for serializing inst 326system.cpu.rename.RunCycles 46747775 # Number of cycles rename is running 327system.cpu.rename.UnblockCycles 27728260 # Number of cycles rename is unblocking 328system.cpu.rename.RenamedInsts 314978384 # Number of instructions processed by rename |
| 327system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full | 329system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full |
| 328system.cpu.rename.IQFullEvents 26056 # Number of times rename has blocked due to IQ full 329system.cpu.rename.LSQFullEvents 25855633 # Number of times rename has blocked due to LSQ full 330system.cpu.rename.RenamedOperands 317074927 # Number of destination operands rename has renamed 331system.cpu.rename.RenameLookups 836235433 # Number of register rename lookups that rename has made 332system.cpu.rename.int_rename_lookups 514870937 # Number of integer rename lookups 333system.cpu.rename.fp_rename_lookups 492 # Number of floating rename lookups | 330system.cpu.rename.IQFullEvents 26284 # Number of times rename has blocked due to IQ full 331system.cpu.rename.LSQFullEvents 25867087 # Number of times rename has blocked due to LSQ full 332system.cpu.rename.RenamedOperands 317148193 # Number of destination operands rename has renamed 333system.cpu.rename.RenameLookups 836430617 # Number of register rename lookups that rename has made 334system.cpu.rename.int_rename_lookups 514996548 # Number of integer rename lookups 335system.cpu.rename.fp_rename_lookups 444 # Number of floating rename lookups |
| 334system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed | 336system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed |
| 335system.cpu.rename.UndoneMaps 37862180 # Number of HB maps that are undone due to squashing 336system.cpu.rename.serializingInsts 484 # count of serializing insts renamed 337system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed 338system.cpu.rename.skidInsts 62586078 # count of insts added to the skid buffer 339system.cpu.memDep0.insertedLoads 101522320 # Number of loads inserted to the mem dependence unit. 340system.cpu.memDep0.insertedStores 34765778 # Number of stores inserted to the mem dependence unit. 341system.cpu.memDep0.conflictingLoads 39602927 # Number of conflicting loads. 342system.cpu.memDep0.conflictingStores 5818030 # Number of conflicting stores. 343system.cpu.iq.iqInstsAdded 311370743 # Number of instructions added to the IQ (excludes non-spec) 344system.cpu.iq.iqNonSpecInstsAdded 1646 # Number of non-speculative instructions added to the IQ 345system.cpu.iq.iqInstsIssued 300208382 # Number of instructions issued 346system.cpu.iq.iqSquashedInstsIssued 88815 # Number of squashed instructions issued 347system.cpu.iq.iqSquashedInstsExamined 32598997 # Number of squashed instructions iterated over during squash; mainly for profiling 348system.cpu.iq.iqSquashedOperandsExamined 45935189 # Number of squashed operands that are examined and possibly removed from graph 349system.cpu.iq.iqSquashedNonSpecRemoved 1201 # Number of squashed non-spec instructions that were removed 350system.cpu.iq.issued_per_cycle::samples 131050652 # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::mean 2.290781 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::stdev 1.700647 # Number of insts issued each cycle | 337system.cpu.rename.UndoneMaps 37935446 # Number of HB maps that are undone due to squashing 338system.cpu.rename.serializingInsts 481 # count of serializing insts renamed 339system.cpu.rename.tempSerializingInsts 479 # count of temporary serializing insts renamed 340system.cpu.rename.skidInsts 62636107 # count of insts added to the skid buffer 341system.cpu.memDep0.insertedLoads 101548078 # Number of loads inserted to the mem dependence unit. 342system.cpu.memDep0.insertedStores 34773749 # Number of stores inserted to the mem dependence unit. 343system.cpu.memDep0.conflictingLoads 39632863 # Number of conflicting loads. 344system.cpu.memDep0.conflictingStores 5801803 # Number of conflicting stores. 345system.cpu.iq.iqInstsAdded 311454794 # Number of instructions added to the IQ (excludes non-spec) 346system.cpu.iq.iqNonSpecInstsAdded 1640 # Number of non-speculative instructions added to the IQ 347system.cpu.iq.iqInstsIssued 300260019 # Number of instructions issued 348system.cpu.iq.iqSquashedInstsIssued 90405 # Number of squashed instructions issued 349system.cpu.iq.iqSquashedInstsExamined 32683934 # Number of squashed instructions iterated over during squash; mainly for profiling 350system.cpu.iq.iqSquashedOperandsExamined 46065887 # Number of squashed operands that are examined and possibly removed from graph 351system.cpu.iq.iqSquashedNonSpecRemoved 1195 # Number of squashed non-spec instructions that were removed 352system.cpu.iq.issued_per_cycle::samples 131067108 # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::mean 2.290888 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::stdev 1.699985 # Number of insts issued each cycle |
| 353system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 355system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 354system.cpu.iq.issued_per_cycle::0 24364795 18.59% 18.59% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::1 23214690 17.71% 36.31% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::2 25426307 19.40% 55.71% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::3 25814267 19.70% 75.41% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::4 18862103 14.39% 89.80% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::5 8277108 6.32% 96.11% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::6 3959654 3.02% 99.14% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::7 947423 0.72% 99.86% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::8 184305 0.14% 100.00% # Number of insts issued each cycle | 356system.cpu.iq.issued_per_cycle::0 24336657 18.57% 18.57% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::1 23236619 17.73% 36.30% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::2 25445511 19.41% 55.71% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::3 25817468 19.70% 75.41% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::4 18870400 14.40% 89.81% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::5 8268823 6.31% 96.12% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::6 3966909 3.03% 99.14% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::7 944963 0.72% 99.86% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::8 179758 0.14% 100.00% # Number of insts issued each cycle |
| 363system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 365system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 366system.cpu.iq.issued_per_cycle::total 131050652 # Number of insts issued each cycle | 368system.cpu.iq.issued_per_cycle::total 131067108 # Number of insts issued each cycle |
| 367system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 369system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 368system.cpu.iq.fu_full::IntAlu 31474 1.53% 1.53% # attempts to use FU when none available | 370system.cpu.iq.fu_full::IntAlu 31509 1.53% 1.53% # attempts to use FU when none available |
| 369system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available 370system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available 372system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 389system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available | 371system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 391system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::MemRead 1916835 93.04% 94.57% # attempts to use FU when none available 398system.cpu.iq.fu_full::MemWrite 111878 5.43% 100.00% # attempts to use FU when none available | 399system.cpu.iq.fu_full::MemRead 1916553 93.05% 94.58% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemWrite 111592 5.42% 100.00% # attempts to use FU when none available |
| 399system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 400system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 401system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 401system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued 402system.cpu.iq.FU_type_0::IntAlu 169792966 56.56% 56.57% # Type of FU issued 403system.cpu.iq.FU_type_0::IntMult 11226 0.00% 56.57% # Type of FU issued 404system.cpu.iq.FU_type_0::IntDiv 332 0.00% 56.57% # Type of FU issued | 403system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued 404system.cpu.iq.FU_type_0::IntAlu 169826780 56.56% 56.57% # Type of FU issued 405system.cpu.iq.FU_type_0::IntMult 11192 0.00% 56.57% # Type of FU issued 406system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.57% # Type of FU issued |
| 405system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued 406system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 423system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued | 407system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 425system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued |
| 431system.cpu.iq.FU_type_0::MemRead 97287204 32.41% 88.98% # Type of FU issued 432system.cpu.iq.FU_type_0::MemWrite 33085346 11.02% 100.00% # Type of FU issued | 433system.cpu.iq.FU_type_0::MemRead 97302133 32.41% 88.98% # Type of FU issued 434system.cpu.iq.FU_type_0::MemWrite 33088277 11.02% 100.00% # Type of FU issued |
| 433system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 434system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 435system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 436system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 435system.cpu.iq.FU_type_0::total 300208382 # Type of FU issued 436system.cpu.iq.rate 2.288937 # Inst issue rate 437system.cpu.iq.fu_busy_cnt 2060187 # FU busy when requested 438system.cpu.iq.fu_busy_rate 0.006863 # FU busy rate (busy events/executed inst) 439system.cpu.iq.int_inst_queue_reads 733615929 # Number of integer instruction queue reads 440system.cpu.iq.int_inst_queue_writes 344003056 # Number of integer instruction queue writes 441system.cpu.iq.int_inst_queue_wakeup_accesses 297961989 # Number of integer instruction queue wakeup accesses 442system.cpu.iq.fp_inst_queue_reads 489 # Number of floating instruction queue reads 443system.cpu.iq.fp_inst_queue_writes 706 # Number of floating instruction queue writes 444system.cpu.iq.fp_inst_queue_wakeup_accesses 149 # Number of floating instruction queue wakeup accesses 445system.cpu.iq.int_alu_accesses 302237064 # Number of integer alu accesses 446system.cpu.iq.fp_alu_accesses 228 # Number of floating point alu accesses 447system.cpu.iew.lsq.thread0.forwLoads 54184589 # Number of loads that had data forwarded from stores | 437system.cpu.iq.FU_type_0::total 300260019 # Type of FU issued 438system.cpu.iq.rate 2.289079 # Inst issue rate 439system.cpu.iq.fu_busy_cnt 2059654 # FU busy when requested 440system.cpu.iq.fu_busy_rate 0.006860 # FU busy rate (busy events/executed inst) 441system.cpu.iq.int_inst_queue_reads 733736743 # Number of integer instruction queue reads 442system.cpu.iq.int_inst_queue_writes 344172361 # Number of integer instruction queue writes 443system.cpu.iq.int_inst_queue_wakeup_accesses 298003080 # Number of integer instruction queue wakeup accesses 444system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads 445system.cpu.iq.fp_inst_queue_writes 638 # Number of floating instruction queue writes 446system.cpu.iq.fp_inst_queue_wakeup_accesses 138 # Number of floating instruction queue wakeup accesses 447system.cpu.iq.int_alu_accesses 302288185 # Number of integer alu accesses 448system.cpu.iq.fp_alu_accesses 212 # Number of floating point alu accesses 449system.cpu.iew.lsq.thread0.forwLoads 54177955 # Number of loads that had data forwarded from stores |
| 448system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 450system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 449system.cpu.iew.lsq.thread0.squashedLoads 10742935 # Number of loads squashed 450system.cpu.iew.lsq.thread0.ignoredResponses 32064 # Number of memory responses ignored because the instruction is squashed 451system.cpu.iew.lsq.thread0.memOrderViolation 33208 # Number of memory ordering violations 452system.cpu.iew.lsq.thread0.squashedStores 3326026 # Number of stores squashed | 451system.cpu.iew.lsq.thread0.squashedLoads 10768693 # Number of loads squashed 452system.cpu.iew.lsq.thread0.ignoredResponses 31319 # Number of memory responses ignored because the instruction is squashed 453system.cpu.iew.lsq.thread0.memOrderViolation 33463 # Number of memory ordering violations 454system.cpu.iew.lsq.thread0.squashedStores 3333997 # Number of stores squashed |
| 453system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 454system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 455system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 456system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 455system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled 456system.cpu.iew.lsq.thread0.cacheBlocked 8575 # Number of times an access to memory failed due to the cache being blocked | 457system.cpu.iew.lsq.thread0.rescheduledLoads 3215 # Number of loads that were rescheduled 458system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked |
| 457system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 459system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 458system.cpu.iew.iewSquashCycles 4530873 # Number of cycles IEW is squashing 459system.cpu.iew.iewBlockCycles 2837927 # Number of cycles IEW is blocking 460system.cpu.iew.iewUnblockCycles 162034 # Number of cycles IEW is unblocking 461system.cpu.iew.iewDispatchedInsts 311372389 # Number of instructions dispatched to IQ 462system.cpu.iew.iewDispSquashedInsts 196090 # Number of squashed instructions skipped by dispatch 463system.cpu.iew.iewDispLoadInsts 101522320 # Number of dispatched load instructions 464system.cpu.iew.iewDispStoreInsts 34765778 # Number of dispatched store instructions 465system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions 466system.cpu.iew.iewIQFullEvents 2524 # Number of times the IQ has become full, causing a stall 467system.cpu.iew.iewLSQFullEvents 73590 # Number of times the LSQ has become full, causing a stall 468system.cpu.iew.memOrderViolationEvents 33208 # Number of memory order violations 469system.cpu.iew.predictedTakenIncorrect 392510 # Number of branches that were predicted taken incorrectly 470system.cpu.iew.predictedNotTakenIncorrect 427924 # Number of branches that were predicted not taken incorrectly 471system.cpu.iew.branchMispredicts 820434 # Number of branch mispredicts detected at execute 472system.cpu.iew.iewExecutedInsts 298810960 # Number of executed instructions 473system.cpu.iew.iewExecLoadInsts 96874788 # Number of load instructions executed 474system.cpu.iew.iewExecSquashedInsts 1397422 # Number of squashed instructions skipped in execute | 460system.cpu.iew.iewSquashCycles 4541041 # Number of cycles IEW is squashing 461system.cpu.iew.iewBlockCycles 2814889 # Number of cycles IEW is blocking 462system.cpu.iew.iewUnblockCycles 161942 # Number of cycles IEW is unblocking 463system.cpu.iew.iewDispatchedInsts 311456434 # Number of instructions dispatched to IQ 464system.cpu.iew.iewDispSquashedInsts 197084 # Number of squashed instructions skipped by dispatch 465system.cpu.iew.iewDispLoadInsts 101548078 # Number of dispatched load instructions 466system.cpu.iew.iewDispStoreInsts 34773749 # Number of dispatched store instructions 467system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions 468system.cpu.iew.iewIQFullEvents 2528 # Number of times the IQ has become full, causing a stall 469system.cpu.iew.iewLSQFullEvents 73554 # Number of times the LSQ has become full, causing a stall 470system.cpu.iew.memOrderViolationEvents 33463 # Number of memory order violations 471system.cpu.iew.predictedTakenIncorrect 393542 # Number of branches that were predicted taken incorrectly 472system.cpu.iew.predictedNotTakenIncorrect 427902 # Number of branches that were predicted not taken incorrectly 473system.cpu.iew.branchMispredicts 821444 # Number of branch mispredicts detected at execute 474system.cpu.iew.iewExecutedInsts 298855458 # Number of executed instructions 475system.cpu.iew.iewExecLoadInsts 96888981 # Number of load instructions executed 476system.cpu.iew.iewExecSquashedInsts 1404561 # Number of squashed instructions skipped in execute |
| 475system.cpu.iew.exec_swp 0 # number of swp insts executed 476system.cpu.iew.exec_nop 0 # number of nop insts executed | 477system.cpu.iew.exec_swp 0 # number of swp insts executed 478system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 477system.cpu.iew.exec_refs 129797042 # number of memory reference insts executed 478system.cpu.iew.exec_branches 30816203 # Number of branches executed 479system.cpu.iew.exec_stores 32922254 # Number of stores executed 480system.cpu.iew.exec_rate 2.278282 # Inst execution rate 481system.cpu.iew.wb_sent 298329085 # cumulative count of insts sent to commit 482system.cpu.iew.wb_count 297962138 # cumulative count of insts written-back 483system.cpu.iew.wb_producers 218205948 # num instructions producing a value 484system.cpu.iew.wb_consumers 296684532 # num instructions consuming a value | 479system.cpu.iew.exec_refs 129814280 # number of memory reference insts executed 480system.cpu.iew.exec_branches 30819367 # Number of branches executed 481system.cpu.iew.exec_stores 32925299 # Number of stores executed 482system.cpu.iew.exec_rate 2.278371 # Inst execution rate 483system.cpu.iew.wb_sent 298372320 # cumulative count of insts sent to commit 484system.cpu.iew.wb_count 298003218 # cumulative count of insts written-back 485system.cpu.iew.wb_producers 218247752 # num instructions producing a value 486system.cpu.iew.wb_consumers 296740863 # num instructions consuming a value |
| 485system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 487system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 486system.cpu.iew.wb_rate 2.271810 # insts written-back per cycle 487system.cpu.iew.wb_fanout 0.735481 # average fanout of values written-back | 488system.cpu.iew.wb_rate 2.271874 # insts written-back per cycle 489system.cpu.iew.wb_fanout 0.735483 # average fanout of values written-back |
| 488system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 490system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 489system.cpu.commit.commitSquashedInsts 33192838 # The number of squashed insts skipped by commit | 491system.cpu.commit.commitSquashedInsts 33277101 # The number of squashed insts skipped by commit |
| 490system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards | 492system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards |
| 491system.cpu.commit.branchMispredicts 773712 # The number of times a branch was mispredicted 492system.cpu.commit.committed_per_cycle::samples 126519779 # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::mean 2.198806 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::stdev 2.971927 # Number of insts commited each cycle | 493system.cpu.commit.branchMispredicts 774736 # The number of times a branch was mispredicted 494system.cpu.commit.committed_per_cycle::samples 126526067 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::mean 2.198697 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::stdev 2.971805 # Number of insts commited each cycle |
| 495system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 497system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 496system.cpu.commit.committed_per_cycle::0 58265880 46.05% 46.05% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::1 19155859 15.14% 61.19% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::2 11581370 9.15% 70.35% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::3 9445264 7.47% 77.81% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::4 1880302 1.49% 79.30% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::5 2071430 1.64% 80.94% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::6 1302334 1.03% 81.97% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::7 693009 0.55% 82.51% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::8 22124331 17.49% 100.00% # Number of insts commited each cycle | 498system.cpu.commit.committed_per_cycle::0 58264985 46.05% 46.05% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::1 19162475 15.15% 61.19% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::2 11581155 9.15% 70.35% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::3 9447794 7.47% 77.82% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::4 1880712 1.49% 79.30% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::5 2075089 1.64% 80.94% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::6 1295892 1.02% 81.97% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::7 693068 0.55% 82.51% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::8 22124897 17.49% 100.00% # Number of insts commited each cycle |
| 505system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 507system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 508system.cpu.commit.committed_per_cycle::total 126519779 # Number of insts commited each cycle | 510system.cpu.commit.committed_per_cycle::total 126526067 # Number of insts commited each cycle |
| 509system.cpu.commit.committedInsts 157988547 # Number of instructions committed 510system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 511system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 512system.cpu.commit.refs 122219137 # Number of memory references committed 513system.cpu.commit.loads 90779385 # Number of loads committed 514system.cpu.commit.membars 0 # Number of memory barriers committed 515system.cpu.commit.branches 29309705 # Number of branches committed 516system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 517system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 518system.cpu.commit.function_calls 4237596 # Number of function calls committed. | 511system.cpu.commit.committedInsts 157988547 # Number of instructions committed 512system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 513system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 514system.cpu.commit.refs 122219137 # Number of memory references committed 515system.cpu.commit.loads 90779385 # Number of loads committed 516system.cpu.commit.membars 0 # Number of memory barriers committed 517system.cpu.commit.branches 29309705 # Number of branches committed 518system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 519system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 520system.cpu.commit.function_calls 4237596 # Number of function calls committed. |
| 519system.cpu.commit.bw_lim_events 22124331 # number cycles where commit BW limit reached | 521system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 522system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 523system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 524system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 525system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 526system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 527system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 551system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 552system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 553system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 556system.cpu.commit.bw_lim_events 22124897 # number cycles where commit BW limit reached |
| 520system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 557system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 521system.cpu.rob.rob_reads 415780750 # The number of ROB reads 522system.cpu.rob.rob_writes 627305222 # The number of ROB writes 523system.cpu.timesIdled 13712 # Number of times that the entire CPU went into an idle state and unscheduled itself 524system.cpu.idleCycles 105606 # Total number of cycles that the CPU has spent unscheduled due to idling | 558system.cpu.rob.rob_reads 415870735 # The number of ROB reads 559system.cpu.rob.rob_writes 627483927 # The number of ROB writes 560system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself 561system.cpu.idleCycles 103577 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 525system.cpu.committedInsts 157988547 # Number of Instructions Simulated 526system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 527system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 562system.cpu.committedInsts 157988547 # Number of Instructions Simulated 563system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 564system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 528system.cpu.cpi 0.830163 # CPI: Cycles Per Instruction 529system.cpu.cpi_total 0.830163 # CPI: Total CPI of All Threads 530system.cpu.ipc 1.204583 # IPC: Instructions Per Cycle 531system.cpu.ipc_total 1.204583 # IPC: Total IPC of All Threads 532system.cpu.int_regfile_reads 483659759 # number of integer regfile reads 533system.cpu.int_regfile_writes 234542237 # number of integer regfile writes 534system.cpu.fp_regfile_reads 137 # number of floating regfile reads 535system.cpu.fp_regfile_writes 71 # number of floating regfile writes 536system.cpu.cc_regfile_reads 107049810 # number of cc regfile reads 537system.cpu.cc_regfile_writes 63997871 # number of cc regfile writes 538system.cpu.misc_regfile_reads 191792946 # number of misc regfile reads | 565system.cpu.cpi 0.830254 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 0.830254 # CPI: Total CPI of All Threads 567system.cpu.ipc 1.204450 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 1.204450 # IPC: Total IPC of All Threads 569system.cpu.int_regfile_reads 483721911 # number of integer regfile reads 570system.cpu.int_regfile_writes 234579114 # number of integer regfile writes 571system.cpu.fp_regfile_reads 126 # number of floating regfile reads 572system.cpu.fp_regfile_writes 70 # number of floating regfile writes 573system.cpu.cc_regfile_reads 107055944 # number of cc regfile reads 574system.cpu.cc_regfile_writes 64002928 # number of cc regfile writes 575system.cpu.misc_regfile_reads 191820739 # number of misc regfile reads |
| 539system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 576system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 540system.cpu.toL2Bus.throughput 4044284064 # Throughput (bytes/s) 541system.cpu.toL2Bus.trans_dist::ReadReq 1995295 # Transaction distribution 542system.cpu.toL2Bus.trans_dist::ReadResp 1995292 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::Writeback 2066395 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::ReadExReq 82322 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::ReadExResp 82322 # Transaction distribution 546system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2024 # Packet count per connected master and slave (bytes) 547system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219602 # Packet count per connected master and slave (bytes) 548system.cpu.toL2Bus.pkt_count::total 6221626 # Packet count per connected master and slave (bytes) 549system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64768 # Cumulative packet size per connected master and slave (bytes) 550system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265151808 # Cumulative packet size per connected master and slave (bytes) 551system.cpu.toL2Bus.tot_pkt_size::total 265216576 # Cumulative packet size per connected master and slave (bytes) 552system.cpu.toL2Bus.data_through_bus 265216576 # Total data (bytes) | 577system.cpu.toL2Bus.throughput 4043936892 # Throughput (bytes/s) 578system.cpu.toL2Bus.trans_dist::ReadReq 1995332 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadResp 1995329 # Transaction distribution 580system.cpu.toL2Bus.trans_dist::Writeback 2066459 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadExReq 82321 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadExResp 82321 # Transaction distribution 583system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2030 # Packet count per connected master and slave (bytes) 584system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219732 # Packet count per connected master and slave (bytes) 585system.cpu.toL2Bus.pkt_count::total 6221762 # Packet count per connected master and slave (bytes) 586system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64960 # Cumulative packet size per connected master and slave (bytes) 587system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265158016 # Cumulative packet size per connected master and slave (bytes) 588system.cpu.toL2Bus.tot_pkt_size::total 265222976 # Cumulative packet size per connected master and slave (bytes) 589system.cpu.toL2Bus.data_through_bus 265222976 # Total data (bytes) |
| 553system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 590system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 554system.cpu.toL2Bus.reqLayer0.occupancy 4138401000 # Layer occupancy (ticks) | 591system.cpu.toL2Bus.reqLayer0.occupancy 4138515000 # Layer occupancy (ticks) |
| 555system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) | 592system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) |
| 556system.cpu.toL2Bus.respLayer0.occupancy 1688749 # Layer occupancy (ticks) | 593system.cpu.toL2Bus.respLayer0.occupancy 1696250 # Layer occupancy (ticks) |
| 557system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 594system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 558system.cpu.toL2Bus.respLayer1.occupancy 3121628749 # Layer occupancy (ticks) | 595system.cpu.toL2Bus.respLayer1.occupancy 3121723249 # Layer occupancy (ticks) |
| 559system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) 560system.cpu.icache.tags.replacements 55 # number of replacements | 596system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) 597system.cpu.icache.tags.replacements 55 # number of replacements |
| 561system.cpu.icache.tags.tagsinuse 821.703802 # Cycle average of tags in use 562system.cpu.icache.tags.total_refs 25564150 # Total number of references to valid blocks. 563system.cpu.icache.tags.sampled_refs 1012 # Sample count of references to valid blocks. 564system.cpu.icache.tags.avg_refs 25261.017787 # Average number of references to valid blocks. | 598system.cpu.icache.tags.tagsinuse 822.073751 # Cycle average of tags in use 599system.cpu.icache.tags.total_refs 25571467 # Total number of references to valid blocks. 600system.cpu.icache.tags.sampled_refs 1015 # Sample count of references to valid blocks. 601system.cpu.icache.tags.avg_refs 25193.563547 # Average number of references to valid blocks. |
| 565system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 602system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 566system.cpu.icache.tags.occ_blocks::cpu.inst 821.703802 # Average occupied blocks per requestor 567system.cpu.icache.tags.occ_percent::cpu.inst 0.401223 # Average percentage of cache occupancy 568system.cpu.icache.tags.occ_percent::total 0.401223 # Average percentage of cache occupancy 569system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id 570system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id | 603system.cpu.icache.tags.occ_blocks::cpu.inst 822.073751 # Average occupied blocks per requestor 604system.cpu.icache.tags.occ_percent::cpu.inst 0.401403 # Average percentage of cache occupancy 605system.cpu.icache.tags.occ_percent::total 0.401403 # Average percentage of cache occupancy 606system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id 607system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id |
| 571system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 572system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id | 608system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 609system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id |
| 573system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id 574system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id 575system.cpu.icache.tags.tag_accesses 51131906 # Number of tag accesses 576system.cpu.icache.tags.data_accesses 51131906 # Number of data accesses 577system.cpu.icache.ReadReq_hits::cpu.inst 25564150 # number of ReadReq hits 578system.cpu.icache.ReadReq_hits::total 25564150 # number of ReadReq hits 579system.cpu.icache.demand_hits::cpu.inst 25564150 # number of demand (read+write) hits 580system.cpu.icache.demand_hits::total 25564150 # number of demand (read+write) hits 581system.cpu.icache.overall_hits::cpu.inst 25564150 # number of overall hits 582system.cpu.icache.overall_hits::total 25564150 # number of overall hits 583system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses 584system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses 585system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses 586system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses 587system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses 588system.cpu.icache.overall_misses::total 1297 # number of overall misses 589system.cpu.icache.ReadReq_miss_latency::cpu.inst 90379749 # number of ReadReq miss cycles 590system.cpu.icache.ReadReq_miss_latency::total 90379749 # number of ReadReq miss cycles 591system.cpu.icache.demand_miss_latency::cpu.inst 90379749 # number of demand (read+write) miss cycles 592system.cpu.icache.demand_miss_latency::total 90379749 # number of demand (read+write) miss cycles 593system.cpu.icache.overall_miss_latency::cpu.inst 90379749 # number of overall miss cycles 594system.cpu.icache.overall_miss_latency::total 90379749 # number of overall miss cycles 595system.cpu.icache.ReadReq_accesses::cpu.inst 25565447 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.ReadReq_accesses::total 25565447 # number of ReadReq accesses(hits+misses) 597system.cpu.icache.demand_accesses::cpu.inst 25565447 # number of demand (read+write) accesses 598system.cpu.icache.demand_accesses::total 25565447 # number of demand (read+write) accesses 599system.cpu.icache.overall_accesses::cpu.inst 25565447 # number of overall (read+write) accesses 600system.cpu.icache.overall_accesses::total 25565447 # number of overall (read+write) accesses | 610system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id 611system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id 612system.cpu.icache.tags.tag_accesses 51146569 # Number of tag accesses 613system.cpu.icache.tags.data_accesses 51146569 # Number of data accesses 614system.cpu.icache.ReadReq_hits::cpu.inst 25571467 # number of ReadReq hits 615system.cpu.icache.ReadReq_hits::total 25571467 # number of ReadReq hits 616system.cpu.icache.demand_hits::cpu.inst 25571467 # number of demand (read+write) hits 617system.cpu.icache.demand_hits::total 25571467 # number of demand (read+write) hits 618system.cpu.icache.overall_hits::cpu.inst 25571467 # number of overall hits 619system.cpu.icache.overall_hits::total 25571467 # number of overall hits 620system.cpu.icache.ReadReq_misses::cpu.inst 1310 # number of ReadReq misses 621system.cpu.icache.ReadReq_misses::total 1310 # number of ReadReq misses 622system.cpu.icache.demand_misses::cpu.inst 1310 # number of demand (read+write) misses 623system.cpu.icache.demand_misses::total 1310 # number of demand (read+write) misses 624system.cpu.icache.overall_misses::cpu.inst 1310 # number of overall misses 625system.cpu.icache.overall_misses::total 1310 # number of overall misses 626system.cpu.icache.ReadReq_miss_latency::cpu.inst 88805250 # number of ReadReq miss cycles 627system.cpu.icache.ReadReq_miss_latency::total 88805250 # number of ReadReq miss cycles 628system.cpu.icache.demand_miss_latency::cpu.inst 88805250 # number of demand (read+write) miss cycles 629system.cpu.icache.demand_miss_latency::total 88805250 # number of demand (read+write) miss cycles 630system.cpu.icache.overall_miss_latency::cpu.inst 88805250 # number of overall miss cycles 631system.cpu.icache.overall_miss_latency::total 88805250 # number of overall miss cycles 632system.cpu.icache.ReadReq_accesses::cpu.inst 25572777 # number of ReadReq accesses(hits+misses) 633system.cpu.icache.ReadReq_accesses::total 25572777 # number of ReadReq accesses(hits+misses) 634system.cpu.icache.demand_accesses::cpu.inst 25572777 # number of demand (read+write) accesses 635system.cpu.icache.demand_accesses::total 25572777 # number of demand (read+write) accesses 636system.cpu.icache.overall_accesses::cpu.inst 25572777 # number of overall (read+write) accesses 637system.cpu.icache.overall_accesses::total 25572777 # number of overall (read+write) accesses |
| 601system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 602system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 603system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 604system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 605system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 606system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses | 638system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 640system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 641system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 642system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 643system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses |
| 607system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69683.692367 # average ReadReq miss latency 608system.cpu.icache.ReadReq_avg_miss_latency::total 69683.692367 # average ReadReq miss latency 609system.cpu.icache.demand_avg_miss_latency::cpu.inst 69683.692367 # average overall miss latency 610system.cpu.icache.demand_avg_miss_latency::total 69683.692367 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::cpu.inst 69683.692367 # average overall miss latency 612system.cpu.icache.overall_avg_miss_latency::total 69683.692367 # average overall miss latency 613system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked | 644system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67790.267176 # average ReadReq miss latency 645system.cpu.icache.ReadReq_avg_miss_latency::total 67790.267176 # average ReadReq miss latency 646system.cpu.icache.demand_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency 647system.cpu.icache.demand_avg_miss_latency::total 67790.267176 # average overall miss latency 648system.cpu.icache.overall_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency 649system.cpu.icache.overall_avg_miss_latency::total 67790.267176 # average overall miss latency 650system.cpu.icache.blocked_cycles::no_mshrs 116 # number of cycles access was blocked |
| 614system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 616system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 651system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 653system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 617system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked | 654system.cpu.icache.avg_blocked_cycles::no_mshrs 38.666667 # average number of cycles each access was blocked |
| 618system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu.icache.fast_writes 0 # number of fast writes performed 620system.cpu.icache.cache_copies 0 # number of cache copies performed | 655system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.icache.fast_writes 0 # number of fast writes performed 657system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 621system.cpu.icache.ReadReq_mshr_hits::cpu.inst 285 # number of ReadReq MSHR hits 622system.cpu.icache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits 623system.cpu.icache.demand_mshr_hits::cpu.inst 285 # number of demand (read+write) MSHR hits 624system.cpu.icache.demand_mshr_hits::total 285 # number of demand (read+write) MSHR hits 625system.cpu.icache.overall_mshr_hits::cpu.inst 285 # number of overall MSHR hits 626system.cpu.icache.overall_mshr_hits::total 285 # number of overall MSHR hits 627system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1012 # number of ReadReq MSHR misses 628system.cpu.icache.ReadReq_mshr_misses::total 1012 # number of ReadReq MSHR misses 629system.cpu.icache.demand_mshr_misses::cpu.inst 1012 # number of demand (read+write) MSHR misses 630system.cpu.icache.demand_mshr_misses::total 1012 # number of demand (read+write) MSHR misses 631system.cpu.icache.overall_mshr_misses::cpu.inst 1012 # number of overall MSHR misses 632system.cpu.icache.overall_mshr_misses::total 1012 # number of overall MSHR misses 633system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70911751 # number of ReadReq MSHR miss cycles 634system.cpu.icache.ReadReq_mshr_miss_latency::total 70911751 # number of ReadReq MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70911751 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.demand_mshr_miss_latency::total 70911751 # number of demand (read+write) MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70911751 # number of overall MSHR miss cycles 638system.cpu.icache.overall_mshr_miss_latency::total 70911751 # number of overall MSHR miss cycles | 658system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits 659system.cpu.icache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits 660system.cpu.icache.demand_mshr_hits::cpu.inst 295 # number of demand (read+write) MSHR hits 661system.cpu.icache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits 662system.cpu.icache.overall_mshr_hits::cpu.inst 295 # number of overall MSHR hits 663system.cpu.icache.overall_mshr_hits::total 295 # number of overall MSHR hits 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1015 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 1015 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 1015 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 1015 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 1015 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 1015 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69941750 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 69941750 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69941750 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 69941750 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69941750 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 69941750 # number of overall MSHR miss cycles |
| 639system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 640system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 641system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 642system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 643system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 644system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70070.900198 # average ReadReq mshr miss latency 646system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70070.900198 # average ReadReq mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70070.900198 # average overall mshr miss latency 648system.cpu.icache.demand_avg_mshr_miss_latency::total 70070.900198 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70070.900198 # average overall mshr miss latency 650system.cpu.icache.overall_avg_mshr_miss_latency::total 70070.900198 # average overall mshr miss latency | 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68908.128079 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68908.128079 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68908.128079 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 68908.128079 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68908.128079 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 68908.128079 # average overall mshr miss latency |
| 651system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 688system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 652system.cpu.l2cache.tags.replacements 479 # number of replacements 653system.cpu.l2cache.tags.tagsinuse 20808.807905 # Cycle average of tags in use 654system.cpu.l2cache.tags.total_refs 4029125 # Total number of references to valid blocks. 655system.cpu.l2cache.tags.sampled_refs 30398 # Sample count of references to valid blocks. 656system.cpu.l2cache.tags.avg_refs 132.545727 # Average number of references to valid blocks. | 689system.cpu.l2cache.tags.replacements 490 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 20815.284491 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 4029213 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 30412 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 132.487604 # Average number of references to valid blocks. |
| 657system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 694system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 658system.cpu.l2cache.tags.occ_blocks::writebacks 19891.385936 # Average occupied blocks per requestor 659system.cpu.l2cache.tags.occ_blocks::cpu.inst 670.059760 # Average occupied blocks per requestor 660system.cpu.l2cache.tags.occ_blocks::cpu.data 247.362209 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_percent::writebacks 0.607037 # Average percentage of cache occupancy 662system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020449 # Average percentage of cache occupancy 663system.cpu.l2cache.tags.occ_percent::cpu.data 0.007549 # Average percentage of cache occupancy 664system.cpu.l2cache.tags.occ_percent::total 0.635034 # Average percentage of cache occupancy 665system.cpu.l2cache.tags.occ_task_id_blocks::1024 29919 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id | 695system.cpu.l2cache.tags.occ_blocks::writebacks 19896.837490 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.064611 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 247.382390 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.607203 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020479 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.007550 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.635232 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 29922 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id |
| 667system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id | 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id |
| 668system.cpu.l2cache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id 669system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1379 # Occupied blocks per task id 670system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27657 # Occupied blocks per task id 671system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913055 # Percentage of cache occupancy per task id 672system.cpu.l2cache.tags.tag_accesses 33264816 # Number of tag accesses 673system.cpu.l2cache.tags.data_accesses 33264816 # Number of data accesses 674system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 675system.cpu.l2cache.ReadReq_hits::cpu.data 1993864 # number of ReadReq hits 676system.cpu.l2cache.ReadReq_hits::total 1993880 # number of ReadReq hits 677system.cpu.l2cache.Writeback_hits::writebacks 2066395 # number of Writeback hits 678system.cpu.l2cache.Writeback_hits::total 2066395 # number of Writeback hits 679system.cpu.l2cache.ReadExReq_hits::cpu.data 53319 # number of ReadExReq hits 680system.cpu.l2cache.ReadExReq_hits::total 53319 # number of ReadExReq hits 681system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 682system.cpu.l2cache.demand_hits::cpu.data 2047183 # number of demand (read+write) hits 683system.cpu.l2cache.demand_hits::total 2047199 # number of demand (read+write) hits 684system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 685system.cpu.l2cache.overall_hits::cpu.data 2047183 # number of overall hits 686system.cpu.l2cache.overall_hits::total 2047199 # number of overall hits 687system.cpu.l2cache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses 688system.cpu.l2cache.ReadReq_misses::cpu.data 419 # number of ReadReq misses 689system.cpu.l2cache.ReadReq_misses::total 1415 # number of ReadReq misses 690system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses 691system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses 692system.cpu.l2cache.demand_misses::cpu.inst 996 # number of demand (read+write) misses 693system.cpu.l2cache.demand_misses::cpu.data 29422 # number of demand (read+write) misses 694system.cpu.l2cache.demand_misses::total 30418 # number of demand (read+write) misses 695system.cpu.l2cache.overall_misses::cpu.inst 996 # number of overall misses 696system.cpu.l2cache.overall_misses::cpu.data 29422 # number of overall misses 697system.cpu.l2cache.overall_misses::total 30418 # number of overall misses 698system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 69735750 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30889250 # number of ReadReq miss cycles 700system.cpu.l2cache.ReadReq_miss_latency::total 100625000 # number of ReadReq miss cycles 701system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1899321750 # number of ReadExReq miss cycles 702system.cpu.l2cache.ReadExReq_miss_latency::total 1899321750 # number of ReadExReq miss cycles 703system.cpu.l2cache.demand_miss_latency::cpu.inst 69735750 # number of demand (read+write) miss cycles 704system.cpu.l2cache.demand_miss_latency::cpu.data 1930211000 # number of demand (read+write) miss cycles 705system.cpu.l2cache.demand_miss_latency::total 1999946750 # number of demand (read+write) miss cycles 706system.cpu.l2cache.overall_miss_latency::cpu.inst 69735750 # number of overall miss cycles 707system.cpu.l2cache.overall_miss_latency::cpu.data 1930211000 # number of overall miss cycles 708system.cpu.l2cache.overall_miss_latency::total 1999946750 # number of overall miss cycles 709system.cpu.l2cache.ReadReq_accesses::cpu.inst 1012 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.ReadReq_accesses::cpu.data 1994283 # number of ReadReq accesses(hits+misses) 711system.cpu.l2cache.ReadReq_accesses::total 1995295 # number of ReadReq accesses(hits+misses) 712system.cpu.l2cache.Writeback_accesses::writebacks 2066395 # number of Writeback accesses(hits+misses) 713system.cpu.l2cache.Writeback_accesses::total 2066395 # number of Writeback accesses(hits+misses) 714system.cpu.l2cache.ReadExReq_accesses::cpu.data 82322 # number of ReadExReq accesses(hits+misses) 715system.cpu.l2cache.ReadExReq_accesses::total 82322 # number of ReadExReq accesses(hits+misses) 716system.cpu.l2cache.demand_accesses::cpu.inst 1012 # number of demand (read+write) accesses 717system.cpu.l2cache.demand_accesses::cpu.data 2076605 # number of demand (read+write) accesses 718system.cpu.l2cache.demand_accesses::total 2077617 # number of demand (read+write) accesses 719system.cpu.l2cache.overall_accesses::cpu.inst 1012 # number of overall (read+write) accesses 720system.cpu.l2cache.overall_accesses::cpu.data 2076605 # number of overall (read+write) accesses 721system.cpu.l2cache.overall_accesses::total 2077617 # number of overall (read+write) accesses 722system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984190 # miss rate for ReadReq accesses 723system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000210 # miss rate for ReadReq accesses 724system.cpu.l2cache.ReadReq_miss_rate::total 0.000709 # miss rate for ReadReq accesses 725system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352312 # miss rate for ReadExReq accesses 726system.cpu.l2cache.ReadExReq_miss_rate::total 0.352312 # miss rate for ReadExReq accesses 727system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984190 # miss rate for demand accesses 728system.cpu.l2cache.demand_miss_rate::cpu.data 0.014168 # miss rate for demand accesses 729system.cpu.l2cache.demand_miss_rate::total 0.014641 # miss rate for demand accesses 730system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984190 # miss rate for overall accesses 731system.cpu.l2cache.overall_miss_rate::cpu.data 0.014168 # miss rate for overall accesses 732system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses 733system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70015.813253 # average ReadReq miss latency 734system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73721.360382 # average ReadReq miss latency 735system.cpu.l2cache.ReadReq_avg_miss_latency::total 71113.074205 # average ReadReq miss latency 736system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65487.078923 # average ReadExReq miss latency 737system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65487.078923 # average ReadExReq miss latency 738system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70015.813253 # average overall miss latency 739system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65604.343688 # average overall miss latency 740system.cpu.l2cache.demand_avg_miss_latency::total 65748.791834 # average overall miss latency 741system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70015.813253 # average overall miss latency 742system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65604.343688 # average overall miss latency 743system.cpu.l2cache.overall_avg_miss_latency::total 65748.791834 # average overall miss latency | 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27649 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913147 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 33265629 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 33265629 # Number of data accesses 711system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits 712system.cpu.l2cache.ReadReq_hits::cpu.data 1993891 # number of ReadReq hits 713system.cpu.l2cache.ReadReq_hits::total 1993905 # number of ReadReq hits 714system.cpu.l2cache.Writeback_hits::writebacks 2066459 # number of Writeback hits 715system.cpu.l2cache.Writeback_hits::total 2066459 # number of Writeback hits 716system.cpu.l2cache.ReadExReq_hits::cpu.data 53316 # number of ReadExReq hits 717system.cpu.l2cache.ReadExReq_hits::total 53316 # number of ReadExReq hits 718system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits 719system.cpu.l2cache.demand_hits::cpu.data 2047207 # number of demand (read+write) hits 720system.cpu.l2cache.demand_hits::total 2047221 # number of demand (read+write) hits 721system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits 722system.cpu.l2cache.overall_hits::cpu.data 2047207 # number of overall hits 723system.cpu.l2cache.overall_hits::total 2047221 # number of overall hits 724system.cpu.l2cache.ReadReq_misses::cpu.inst 1001 # number of ReadReq misses 725system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses 726system.cpu.l2cache.ReadReq_misses::total 1427 # number of ReadReq misses 727system.cpu.l2cache.ReadExReq_misses::cpu.data 29005 # number of ReadExReq misses 728system.cpu.l2cache.ReadExReq_misses::total 29005 # number of ReadExReq misses 729system.cpu.l2cache.demand_misses::cpu.inst 1001 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::cpu.data 29431 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::total 30432 # number of demand (read+write) misses 732system.cpu.l2cache.overall_misses::cpu.inst 1001 # number of overall misses 733system.cpu.l2cache.overall_misses::cpu.data 29431 # number of overall misses 734system.cpu.l2cache.overall_misses::total 30432 # number of overall misses 735system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68781250 # number of ReadReq miss cycles 736system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30133000 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::total 98914250 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1888274750 # number of ReadExReq miss cycles 739system.cpu.l2cache.ReadExReq_miss_latency::total 1888274750 # number of ReadExReq miss cycles 740system.cpu.l2cache.demand_miss_latency::cpu.inst 68781250 # number of demand (read+write) miss cycles 741system.cpu.l2cache.demand_miss_latency::cpu.data 1918407750 # number of demand (read+write) miss cycles 742system.cpu.l2cache.demand_miss_latency::total 1987189000 # number of demand (read+write) miss cycles 743system.cpu.l2cache.overall_miss_latency::cpu.inst 68781250 # number of overall miss cycles 744system.cpu.l2cache.overall_miss_latency::cpu.data 1918407750 # number of overall miss cycles 745system.cpu.l2cache.overall_miss_latency::total 1987189000 # number of overall miss cycles 746system.cpu.l2cache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses) 747system.cpu.l2cache.ReadReq_accesses::cpu.data 1994317 # number of ReadReq accesses(hits+misses) 748system.cpu.l2cache.ReadReq_accesses::total 1995332 # number of ReadReq accesses(hits+misses) 749system.cpu.l2cache.Writeback_accesses::writebacks 2066459 # number of Writeback accesses(hits+misses) 750system.cpu.l2cache.Writeback_accesses::total 2066459 # number of Writeback accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::cpu.data 82321 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.ReadExReq_accesses::total 82321 # number of ReadExReq accesses(hits+misses) 753system.cpu.l2cache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::cpu.data 2076638 # number of demand (read+write) accesses 755system.cpu.l2cache.demand_accesses::total 2077653 # number of demand (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::cpu.data 2076638 # number of overall (read+write) accesses 758system.cpu.l2cache.overall_accesses::total 2077653 # number of overall (read+write) accesses 759system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986207 # miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_miss_rate::total 0.000715 # miss rate for ReadReq accesses 762system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352340 # miss rate for ReadExReq accesses 763system.cpu.l2cache.ReadExReq_miss_rate::total 0.352340 # miss rate for ReadExReq accesses 764system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986207 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::cpu.data 0.014172 # miss rate for demand accesses 766system.cpu.l2cache.demand_miss_rate::total 0.014647 # miss rate for demand accesses 767system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986207 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::cpu.data 0.014172 # miss rate for overall accesses 769system.cpu.l2cache.overall_miss_rate::total 0.014647 # miss rate for overall accesses 770system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68712.537463 # average ReadReq miss latency 771system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70734.741784 # average ReadReq miss latency 772system.cpu.l2cache.ReadReq_avg_miss_latency::total 69316.222845 # average ReadReq miss latency 773system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65101.697983 # average ReadExReq miss latency 774system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65101.697983 # average ReadExReq miss latency 775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68712.537463 # average overall miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65183.233665 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::total 65299.323081 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68712.537463 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65183.233665 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::total 65299.323081 # average overall miss latency |
| 744system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 745system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 746system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 747system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 748system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 749system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 750system.cpu.l2cache.fast_writes 0 # number of fast writes performed 751system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 781system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu.l2cache.fast_writes 0 # number of fast writes performed 788system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 752system.cpu.l2cache.writebacks::writebacks 162 # number of writebacks 753system.cpu.l2cache.writebacks::total 162 # number of writebacks 754system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 996 # number of ReadReq MSHR misses 755system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 419 # number of ReadReq MSHR misses 756system.cpu.l2cache.ReadReq_mshr_misses::total 1415 # number of ReadReq MSHR misses 757system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses 758system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses 759system.cpu.l2cache.demand_mshr_misses::cpu.inst 996 # number of demand (read+write) MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::total 30418 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.overall_mshr_misses::cpu.inst 996 # number of overall MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::total 30418 # number of overall MSHR misses 765system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 57248250 # number of ReadReq MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25743750 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82992000 # number of ReadReq MSHR miss cycles 768system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1534558750 # number of ReadExReq MSHR miss cycles 769system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1534558750 # number of ReadExReq MSHR miss cycles 770system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 57248250 # number of demand (read+write) MSHR miss cycles 771system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1560302500 # number of demand (read+write) MSHR miss cycles 772system.cpu.l2cache.demand_mshr_miss_latency::total 1617550750 # number of demand (read+write) MSHR miss cycles 773system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 57248250 # number of overall MSHR miss cycles 774system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1560302500 # number of overall MSHR miss cycles 775system.cpu.l2cache.overall_mshr_miss_latency::total 1617550750 # number of overall MSHR miss cycles 776system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984190 # mshr miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000210 # mshr miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses 779system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352312 # mshr miss rate for ReadExReq accesses 780system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352312 # mshr miss rate for ReadExReq accesses 781system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984190 # mshr miss rate for demand accesses 782system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014168 # mshr miss rate for demand accesses 783system.cpu.l2cache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses 784system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984190 # mshr miss rate for overall accesses 785system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014168 # mshr miss rate for overall accesses 786system.cpu.l2cache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses 787system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57478.162651 # average ReadReq mshr miss latency 788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61440.930788 # average ReadReq mshr miss latency 789system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58651.590106 # average ReadReq mshr miss latency 790system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52910.345482 # average ReadExReq mshr miss latency 791system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52910.345482 # average ReadExReq mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57478.162651 # average overall mshr miss latency 793system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53031.829923 # average overall mshr miss latency 794system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53177.419620 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57478.162651 # average overall mshr miss latency 796system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53031.829923 # average overall mshr miss latency 797system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53177.419620 # average overall mshr miss latency | 789system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks 790system.cpu.l2cache.writebacks::total 175 # number of writebacks 791system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1001 # number of ReadReq MSHR misses 792system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses 793system.cpu.l2cache.ReadReq_mshr_misses::total 1427 # number of ReadReq MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29005 # number of ReadExReq MSHR misses 795system.cpu.l2cache.ReadExReq_mshr_misses::total 29005 # number of ReadExReq MSHR misses 796system.cpu.l2cache.demand_mshr_misses::cpu.inst 1001 # number of demand (read+write) MSHR misses 797system.cpu.l2cache.demand_mshr_misses::cpu.data 29431 # number of demand (read+write) MSHR misses 798system.cpu.l2cache.demand_mshr_misses::total 30432 # number of demand (read+write) MSHR misses 799system.cpu.l2cache.overall_mshr_misses::cpu.inst 1001 # number of overall MSHR misses 800system.cpu.l2cache.overall_mshr_misses::cpu.data 29431 # number of overall MSHR misses 801system.cpu.l2cache.overall_mshr_misses::total 30432 # number of overall MSHR misses 802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 56223750 # number of ReadReq MSHR miss cycles 803system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24897500 # number of ReadReq MSHR miss cycles 804system.cpu.l2cache.ReadReq_mshr_miss_latency::total 81121250 # number of ReadReq MSHR miss cycles 805system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1523473250 # number of ReadExReq MSHR miss cycles 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1523473250 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56223750 # number of demand (read+write) MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1548370750 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.demand_mshr_miss_latency::total 1604594500 # number of demand (read+write) MSHR miss cycles 810system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56223750 # number of overall MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1548370750 # number of overall MSHR miss cycles 812system.cpu.l2cache.overall_mshr_miss_latency::total 1604594500 # number of overall MSHR miss cycles 813system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for ReadReq accesses 814system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses 815system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000715 # mshr miss rate for ReadReq accesses 816system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352340 # mshr miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352340 # mshr miss rate for ReadExReq accesses 818system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for demand accesses 819system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014172 # mshr miss rate for demand accesses 820system.cpu.l2cache.demand_mshr_miss_rate::total 0.014647 # mshr miss rate for demand accesses 821system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for overall accesses 822system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014172 # mshr miss rate for overall accesses 823system.cpu.l2cache.overall_mshr_miss_rate::total 0.014647 # mshr miss rate for overall accesses 824system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56167.582418 # average ReadReq mshr miss latency 825system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58444.835681 # average ReadReq mshr miss latency 826system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56847.407148 # average ReadReq mshr miss latency 827system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52524.504396 # average ReadExReq mshr miss latency 828system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52524.504396 # average ReadExReq mshr miss latency 829system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56167.582418 # average overall mshr miss latency 830system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52610.198430 # average overall mshr miss latency 831system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52727.211488 # average overall mshr miss latency 832system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56167.582418 # average overall mshr miss latency 833system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52610.198430 # average overall mshr miss latency 834system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52727.211488 # average overall mshr miss latency |
| 798system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 835system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 799system.cpu.dcache.tags.replacements 2072506 # number of replacements 800system.cpu.dcache.tags.tagsinuse 4069.429006 # Cycle average of tags in use 801system.cpu.dcache.tags.total_refs 71361494 # Total number of references to valid blocks. 802system.cpu.dcache.tags.sampled_refs 2076602 # Sample count of references to valid blocks. 803system.cpu.dcache.tags.avg_refs 34.364550 # Average number of references to valid blocks. 804system.cpu.dcache.tags.warmup_cycle 20660759250 # Cycle when the warmup percentage was hit. 805system.cpu.dcache.tags.occ_blocks::cpu.data 4069.429006 # Average occupied blocks per requestor 806system.cpu.dcache.tags.occ_percent::cpu.data 0.993513 # Average percentage of cache occupancy 807system.cpu.dcache.tags.occ_percent::total 0.993513 # Average percentage of cache occupancy | 836system.cpu.dcache.tags.replacements 2072539 # number of replacements 837system.cpu.dcache.tags.tagsinuse 4069.510002 # Cycle average of tags in use 838system.cpu.dcache.tags.total_refs 71382775 # Total number of references to valid blocks. 839system.cpu.dcache.tags.sampled_refs 2076635 # Sample count of references to valid blocks. 840system.cpu.dcache.tags.avg_refs 34.374252 # Average number of references to valid blocks. 841system.cpu.dcache.tags.warmup_cycle 20654566000 # Cycle when the warmup percentage was hit. 842system.cpu.dcache.tags.occ_blocks::cpu.data 4069.510002 # Average occupied blocks per requestor 843system.cpu.dcache.tags.occ_percent::cpu.data 0.993533 # Average percentage of cache occupancy 844system.cpu.dcache.tags.occ_percent::total 0.993533 # Average percentage of cache occupancy |
| 808system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 845system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 809system.cpu.dcache.tags.age_task_id_blocks_1024::0 573 # Occupied blocks per task id 810system.cpu.dcache.tags.age_task_id_blocks_1024::1 3367 # Occupied blocks per task id 811system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id | 846system.cpu.dcache.tags.age_task_id_blocks_1024::0 584 # Occupied blocks per task id 847system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id 848system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id |
| 812system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 849system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 813system.cpu.dcache.tags.tag_accesses 150248380 # Number of tag accesses 814system.cpu.dcache.tags.data_accesses 150248380 # Number of data accesses 815system.cpu.dcache.ReadReq_hits::cpu.data 40019790 # number of ReadReq hits 816system.cpu.dcache.ReadReq_hits::total 40019790 # number of ReadReq hits 817system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits 818system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits 819system.cpu.dcache.demand_hits::cpu.data 71361494 # number of demand (read+write) hits 820system.cpu.dcache.demand_hits::total 71361494 # number of demand (read+write) hits 821system.cpu.dcache.overall_hits::cpu.data 71361494 # number of overall hits 822system.cpu.dcache.overall_hits::total 71361494 # number of overall hits 823system.cpu.dcache.ReadReq_misses::cpu.data 2626347 # number of ReadReq misses 824system.cpu.dcache.ReadReq_misses::total 2626347 # number of ReadReq misses 825system.cpu.dcache.WriteReq_misses::cpu.data 98048 # number of WriteReq misses 826system.cpu.dcache.WriteReq_misses::total 98048 # number of WriteReq misses 827system.cpu.dcache.demand_misses::cpu.data 2724395 # number of demand (read+write) misses 828system.cpu.dcache.demand_misses::total 2724395 # number of demand (read+write) misses 829system.cpu.dcache.overall_misses::cpu.data 2724395 # number of overall misses 830system.cpu.dcache.overall_misses::total 2724395 # number of overall misses 831system.cpu.dcache.ReadReq_miss_latency::cpu.data 31407355250 # number of ReadReq miss cycles 832system.cpu.dcache.ReadReq_miss_latency::total 31407355250 # number of ReadReq miss cycles 833system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801736997 # number of WriteReq miss cycles 834system.cpu.dcache.WriteReq_miss_latency::total 2801736997 # number of WriteReq miss cycles 835system.cpu.dcache.demand_miss_latency::cpu.data 34209092247 # number of demand (read+write) miss cycles 836system.cpu.dcache.demand_miss_latency::total 34209092247 # number of demand (read+write) miss cycles 837system.cpu.dcache.overall_miss_latency::cpu.data 34209092247 # number of overall miss cycles 838system.cpu.dcache.overall_miss_latency::total 34209092247 # number of overall miss cycles 839system.cpu.dcache.ReadReq_accesses::cpu.data 42646137 # number of ReadReq accesses(hits+misses) 840system.cpu.dcache.ReadReq_accesses::total 42646137 # number of ReadReq accesses(hits+misses) | 850system.cpu.dcache.tags.tag_accesses 150290167 # Number of tag accesses 851system.cpu.dcache.tags.data_accesses 150290167 # Number of data accesses 852system.cpu.dcache.ReadReq_hits::cpu.data 40041040 # number of ReadReq hits 853system.cpu.dcache.ReadReq_hits::total 40041040 # number of ReadReq hits 854system.cpu.dcache.WriteReq_hits::cpu.data 31341735 # number of WriteReq hits 855system.cpu.dcache.WriteReq_hits::total 31341735 # number of WriteReq hits 856system.cpu.dcache.demand_hits::cpu.data 71382775 # number of demand (read+write) hits 857system.cpu.dcache.demand_hits::total 71382775 # number of demand (read+write) hits 858system.cpu.dcache.overall_hits::cpu.data 71382775 # number of overall hits 859system.cpu.dcache.overall_hits::total 71382775 # number of overall hits 860system.cpu.dcache.ReadReq_misses::cpu.data 2625974 # number of ReadReq misses 861system.cpu.dcache.ReadReq_misses::total 2625974 # number of ReadReq misses 862system.cpu.dcache.WriteReq_misses::cpu.data 98017 # number of WriteReq misses 863system.cpu.dcache.WriteReq_misses::total 98017 # number of WriteReq misses 864system.cpu.dcache.demand_misses::cpu.data 2723991 # number of demand (read+write) misses 865system.cpu.dcache.demand_misses::total 2723991 # number of demand (read+write) misses 866system.cpu.dcache.overall_misses::cpu.data 2723991 # number of overall misses 867system.cpu.dcache.overall_misses::total 2723991 # number of overall misses 868system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399512249 # number of ReadReq miss cycles 869system.cpu.dcache.ReadReq_miss_latency::total 31399512249 # number of ReadReq miss cycles 870system.cpu.dcache.WriteReq_miss_latency::cpu.data 2790424746 # number of WriteReq miss cycles 871system.cpu.dcache.WriteReq_miss_latency::total 2790424746 # number of WriteReq miss cycles 872system.cpu.dcache.demand_miss_latency::cpu.data 34189936995 # number of demand (read+write) miss cycles 873system.cpu.dcache.demand_miss_latency::total 34189936995 # number of demand (read+write) miss cycles 874system.cpu.dcache.overall_miss_latency::cpu.data 34189936995 # number of overall miss cycles 875system.cpu.dcache.overall_miss_latency::total 34189936995 # number of overall miss cycles 876system.cpu.dcache.ReadReq_accesses::cpu.data 42667014 # number of ReadReq accesses(hits+misses) 877system.cpu.dcache.ReadReq_accesses::total 42667014 # number of ReadReq accesses(hits+misses) |
| 841system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 842system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 878system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 879system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 843system.cpu.dcache.demand_accesses::cpu.data 74085889 # number of demand (read+write) accesses 844system.cpu.dcache.demand_accesses::total 74085889 # number of demand (read+write) accesses 845system.cpu.dcache.overall_accesses::cpu.data 74085889 # number of overall (read+write) accesses 846system.cpu.dcache.overall_accesses::total 74085889 # number of overall (read+write) accesses 847system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061585 # miss rate for ReadReq accesses 848system.cpu.dcache.ReadReq_miss_rate::total 0.061585 # miss rate for ReadReq accesses 849system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses 850system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses 851system.cpu.dcache.demand_miss_rate::cpu.data 0.036773 # miss rate for demand accesses 852system.cpu.dcache.demand_miss_rate::total 0.036773 # miss rate for demand accesses 853system.cpu.dcache.overall_miss_rate::cpu.data 0.036773 # miss rate for overall accesses 854system.cpu.dcache.overall_miss_rate::total 0.036773 # miss rate for overall accesses 855system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.570307 # average ReadReq miss latency 856system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.570307 # average ReadReq miss latency 857system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28575.157035 # average WriteReq miss latency 858system.cpu.dcache.WriteReq_avg_miss_latency::total 28575.157035 # average WriteReq miss latency 859system.cpu.dcache.demand_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency 860system.cpu.dcache.demand_avg_miss_latency::total 12556.583112 # average overall miss latency 861system.cpu.dcache.overall_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency 862system.cpu.dcache.overall_avg_miss_latency::total 12556.583112 # average overall miss latency 863system.cpu.dcache.blocked_cycles::no_mshrs 32689 # number of cycles access was blocked | 880system.cpu.dcache.demand_accesses::cpu.data 74106766 # number of demand (read+write) accesses 881system.cpu.dcache.demand_accesses::total 74106766 # number of demand (read+write) accesses 882system.cpu.dcache.overall_accesses::cpu.data 74106766 # number of overall (read+write) accesses 883system.cpu.dcache.overall_accesses::total 74106766 # number of overall (read+write) accesses 884system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061546 # miss rate for ReadReq accesses 885system.cpu.dcache.ReadReq_miss_rate::total 0.061546 # miss rate for ReadReq accesses 886system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003118 # miss rate for WriteReq accesses 887system.cpu.dcache.WriteReq_miss_rate::total 0.003118 # miss rate for WriteReq accesses 888system.cpu.dcache.demand_miss_rate::cpu.data 0.036758 # miss rate for demand accesses 889system.cpu.dcache.demand_miss_rate::total 0.036758 # miss rate for demand accesses 890system.cpu.dcache.overall_miss_rate::cpu.data 0.036758 # miss rate for overall accesses 891system.cpu.dcache.overall_miss_rate::total 0.036758 # miss rate for overall accesses 892system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11957.282231 # average ReadReq miss latency 893system.cpu.dcache.ReadReq_avg_miss_latency::total 11957.282231 # average ReadReq miss latency 894system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28468.783436 # average WriteReq miss latency 895system.cpu.dcache.WriteReq_avg_miss_latency::total 28468.783436 # average WriteReq miss latency 896system.cpu.dcache.demand_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency 897system.cpu.dcache.demand_avg_miss_latency::total 12551.413347 # average overall miss latency 898system.cpu.dcache.overall_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency 899system.cpu.dcache.overall_avg_miss_latency::total 12551.413347 # average overall miss latency 900system.cpu.dcache.blocked_cycles::no_mshrs 32593 # number of cycles access was blocked |
| 864system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 901system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 865system.cpu.dcache.blocked::no_mshrs 9492 # number of cycles access was blocked | 902system.cpu.dcache.blocked::no_mshrs 9513 # number of cycles access was blocked |
| 866system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 903system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 867system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443847 # average number of cycles each access was blocked | 904system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.426154 # average number of cycles each access was blocked |
| 868system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 869system.cpu.dcache.fast_writes 0 # number of fast writes performed 870system.cpu.dcache.cache_copies 0 # number of cache copies performed | 905system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.dcache.fast_writes 0 # number of fast writes performed 907system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 871system.cpu.dcache.writebacks::writebacks 2066395 # number of writebacks 872system.cpu.dcache.writebacks::total 2066395 # number of writebacks 873system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631958 # number of ReadReq MSHR hits 874system.cpu.dcache.ReadReq_mshr_hits::total 631958 # number of ReadReq MSHR hits 875system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15832 # number of WriteReq MSHR hits 876system.cpu.dcache.WriteReq_mshr_hits::total 15832 # number of WriteReq MSHR hits 877system.cpu.dcache.demand_mshr_hits::cpu.data 647790 # number of demand (read+write) MSHR hits 878system.cpu.dcache.demand_mshr_hits::total 647790 # number of demand (read+write) MSHR hits 879system.cpu.dcache.overall_mshr_hits::cpu.data 647790 # number of overall MSHR hits 880system.cpu.dcache.overall_mshr_hits::total 647790 # number of overall MSHR hits 881system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994389 # number of ReadReq MSHR misses 882system.cpu.dcache.ReadReq_mshr_misses::total 1994389 # number of ReadReq MSHR misses 883system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses 884system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses 885system.cpu.dcache.demand_mshr_misses::cpu.data 2076605 # number of demand (read+write) MSHR misses 886system.cpu.dcache.demand_mshr_misses::total 2076605 # number of demand (read+write) MSHR misses 887system.cpu.dcache.overall_mshr_misses::cpu.data 2076605 # number of overall MSHR misses 888system.cpu.dcache.overall_mshr_misses::total 2076605 # number of overall MSHR misses 889system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21997400000 # number of ReadReq MSHR miss cycles 890system.cpu.dcache.ReadReq_mshr_miss_latency::total 21997400000 # number of ReadReq MSHR miss cycles 891system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514181749 # number of WriteReq MSHR miss cycles 892system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514181749 # number of WriteReq MSHR miss cycles 893system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24511581749 # number of demand (read+write) MSHR miss cycles 894system.cpu.dcache.demand_mshr_miss_latency::total 24511581749 # number of demand (read+write) MSHR miss cycles 895system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24511581749 # number of overall MSHR miss cycles 896system.cpu.dcache.overall_mshr_miss_latency::total 24511581749 # number of overall MSHR miss cycles 897system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046766 # mshr miss rate for ReadReq accesses 898system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046766 # mshr miss rate for ReadReq accesses | 908system.cpu.dcache.writebacks::writebacks 2066459 # number of writebacks 909system.cpu.dcache.writebacks::total 2066459 # number of writebacks 910system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631537 # number of ReadReq MSHR hits 911system.cpu.dcache.ReadReq_mshr_hits::total 631537 # number of ReadReq MSHR hits 912system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15816 # number of WriteReq MSHR hits 913system.cpu.dcache.WriteReq_mshr_hits::total 15816 # number of WriteReq MSHR hits 914system.cpu.dcache.demand_mshr_hits::cpu.data 647353 # number of demand (read+write) MSHR hits 915system.cpu.dcache.demand_mshr_hits::total 647353 # number of demand (read+write) MSHR hits 916system.cpu.dcache.overall_mshr_hits::cpu.data 647353 # number of overall MSHR hits 917system.cpu.dcache.overall_mshr_hits::total 647353 # number of overall MSHR hits 918system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994437 # number of ReadReq MSHR misses 919system.cpu.dcache.ReadReq_mshr_misses::total 1994437 # number of ReadReq MSHR misses 920system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82201 # number of WriteReq MSHR misses 921system.cpu.dcache.WriteReq_mshr_misses::total 82201 # number of WriteReq MSHR misses 922system.cpu.dcache.demand_mshr_misses::cpu.data 2076638 # number of demand (read+write) MSHR misses 923system.cpu.dcache.demand_mshr_misses::total 2076638 # number of demand (read+write) MSHR misses 924system.cpu.dcache.overall_mshr_misses::cpu.data 2076638 # number of overall MSHR misses 925system.cpu.dcache.overall_mshr_misses::total 2076638 # number of overall MSHR misses 926system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996919001 # number of ReadReq MSHR miss cycles 927system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996919001 # number of ReadReq MSHR miss cycles 928system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502949746 # number of WriteReq MSHR miss cycles 929system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502949746 # number of WriteReq MSHR miss cycles 930system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24499868747 # number of demand (read+write) MSHR miss cycles 931system.cpu.dcache.demand_mshr_miss_latency::total 24499868747 # number of demand (read+write) MSHR miss cycles 932system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24499868747 # number of overall MSHR miss cycles 933system.cpu.dcache.overall_mshr_miss_latency::total 24499868747 # number of overall MSHR miss cycles 934system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046744 # mshr miss rate for ReadReq accesses 935system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046744 # mshr miss rate for ReadReq accesses |
| 899system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses 900system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses | 936system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses 937system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses |
| 901system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for demand accesses 902system.cpu.dcache.demand_mshr_miss_rate::total 0.028030 # mshr miss rate for demand accesses 903system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for overall accesses 904system.cpu.dcache.overall_mshr_miss_rate::total 0.028030 # mshr miss rate for overall accesses 905system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.643665 # average ReadReq mshr miss latency 906system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.643665 # average ReadReq mshr miss latency 907system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30580.200314 # average WriteReq mshr miss latency 908system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30580.200314 # average WriteReq mshr miss latency 909system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency 910system.cpu.dcache.demand_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency 911system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency 912system.cpu.dcache.overall_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency | 938system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for demand accesses 939system.cpu.dcache.demand_mshr_miss_rate::total 0.028022 # mshr miss rate for demand accesses 940system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for overall accesses 941system.cpu.dcache.overall_mshr_miss_rate::total 0.028022 # mshr miss rate for overall accesses 942system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.137045 # average ReadReq mshr miss latency 943system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.137045 # average ReadReq mshr miss latency 944system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30449.139864 # average WriteReq mshr miss latency 945system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30449.139864 # average WriteReq mshr miss latency 946system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency 947system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency 948system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency 949system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency |
| 913system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 914 915---------- End Simulation Statistics ---------- | 950system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 951 952---------- End Simulation Statistics ---------- |