7,11c7,11
< host_inst_rate 90206 # Simulator instruction rate (inst/s)
< host_op_rate 158838 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37463203 # Simulator tick rate (ticks/s)
< host_mem_usage 416624 # Number of bytes of host memory used
< host_seconds 1751.42 # Real time elapsed on the host
---
> host_inst_rate 72100 # Simulator instruction rate (inst/s)
> host_op_rate 126957 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 29943715 # Simulator tick rate (ticks/s)
> host_mem_usage 436724 # Number of bytes of host memory used
> host_seconds 2191.24 # Real time elapsed on the host
299c299
< system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks)
301c301
< system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks)
376c376
< system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec)
378c378
< system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued
380,381c380,381
< system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph
388c388
< system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle
390,393c390,393
< system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle
430c430
< system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available
435c435
< system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued
464c464
< system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued
468c468
< system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued
470c470
< system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested
472,474c472,474
< system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses
478c478
< system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses
483,484c483,484
< system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations
---
> system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations
494c494
< system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ
501c501
< system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations
---
> system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations
505,507c505,507
< system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute
510c510
< system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed
512c512
< system.cpu.iew.exec_stores 32925944 # Number of stores executed
---
> system.cpu.iew.exec_stores 32925943 # Number of stores executed
514,517c514,517
< system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 218260008 # num instructions producing a value
< system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 218260006 # num instructions producing a value
> system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value
522c522
< system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit
554,555c554,555
< system.cpu.rob.rob_reads 415950983 # The number of ROB reads
< system.cpu.rob.rob_writes 627545403 # The number of ROB writes
---
> system.cpu.rob.rob_reads 415950981 # The number of ROB reads
> system.cpu.rob.rob_writes 627545399 # The number of ROB writes
565,566c565,566
< system.cpu.int_regfile_reads 483744134 # number of integer regfile reads
< system.cpu.int_regfile_writes 234595253 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 483744129 # number of integer regfile reads
> system.cpu.int_regfile_writes 234595251 # number of integer regfile writes
571c571
< system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads
614,619c614,619
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles
632,637c632,637
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency
658,663c658,663
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles
670,675c670,675
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency
714c714
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles
716c716
< system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles
719c719
< system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles
721,722c721,722
< system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles
724c724
< system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles
749c749
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency
751c751
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency
754c754
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency
756,757c756,757
< system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency
759c759
< system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency
817c817
< system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks.
824,825c824,825
< system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits
828,831c828,831
< system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits
< system.cpu.dcache.overall_hits::total 71413624 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits
> system.cpu.dcache.overall_hits::total 71413623 # number of overall hits
848,849c848,849
< system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses)
852,855c852,855
< system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses
< host_inst_rate 90206 # Simulator instruction rate (inst/s)
< host_op_rate 158838 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37463203 # Simulator tick rate (ticks/s)
< host_mem_usage 416624 # Number of bytes of host memory used
< host_seconds 1751.42 # Real time elapsed on the host
---
> host_inst_rate 72100 # Simulator instruction rate (inst/s)
> host_op_rate 126957 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 29943715 # Simulator tick rate (ticks/s)
> host_mem_usage 436724 # Number of bytes of host memory used
> host_seconds 2191.24 # Real time elapsed on the host
299c299
< system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks)
301c301
< system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks)
376c376
< system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec)
378c378
< system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued
380,381c380,381
< system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph
388c388
< system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle
390,393c390,393
< system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle
430c430
< system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available
435c435
< system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued
464c464
< system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued
468c468
< system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued
470c470
< system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested
472,474c472,474
< system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses
478c478
< system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses
483,484c483,484
< system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations
---
> system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations
494c494
< system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ
501c501
< system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations
---
> system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations
505,507c505,507
< system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute
510c510
< system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed
512c512
< system.cpu.iew.exec_stores 32925944 # Number of stores executed
---
> system.cpu.iew.exec_stores 32925943 # Number of stores executed
514,517c514,517
< system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 218260008 # num instructions producing a value
< system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 218260006 # num instructions producing a value
> system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value
522c522
< system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit
554,555c554,555
< system.cpu.rob.rob_reads 415950983 # The number of ROB reads
< system.cpu.rob.rob_writes 627545403 # The number of ROB writes
---
> system.cpu.rob.rob_reads 415950981 # The number of ROB reads
> system.cpu.rob.rob_writes 627545399 # The number of ROB writes
565,566c565,566
< system.cpu.int_regfile_reads 483744134 # number of integer regfile reads
< system.cpu.int_regfile_writes 234595253 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 483744129 # number of integer regfile reads
> system.cpu.int_regfile_writes 234595251 # number of integer regfile writes
571c571
< system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads
614,619c614,619
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles
632,637c632,637
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency
658,663c658,663
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles
670,675c670,675
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency
714c714
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles
716c716
< system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles
719c719
< system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles
721,722c721,722
< system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles
724c724
< system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles
749c749
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency
751c751
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency
754c754
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency
756,757c756,757
< system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency
759c759
< system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency
817c817
< system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks.
824,825c824,825
< system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits
828,831c828,831
< system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits
< system.cpu.dcache.overall_hits::total 71413624 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits
> system.cpu.dcache.overall_hits::total 71413623 # number of overall hits
848,849c848,849
< system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses)
852,855c852,855
< system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses