3,5c3,5
< sim_seconds 0.065497 # Number of seconds simulated
< sim_ticks 65497052500 # Number of ticks simulated
< final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.065614 # Number of seconds simulated
> sim_ticks 65613727000 # Number of ticks simulated
> final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 99498 # Simulator instruction rate (inst/s)
< host_op_rate 175200 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 41248682 # Simulator tick rate (ticks/s)
< host_mem_usage 388584 # Number of bytes of host memory used
< host_seconds 1587.86 # Real time elapsed on the host
---
> host_inst_rate 90206 # Simulator instruction rate (inst/s)
> host_op_rate 158838 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 37463203 # Simulator tick rate (ticks/s)
> host_mem_usage 416624 # Number of bytes of host memory used
> host_seconds 1751.42 # Real time elapsed on the host
14,99c14,101
< system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory
< system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9984 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 156 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 1945536 # Total number of bytes read from memory
< system.physmem.bytesWritten 9984 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 65497035500 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 0 # Categorize read packet sizes
< system.physmem.readPktSize::3 0 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 30400 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 0 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 156 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
---
> system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory
> system.physmem.bytes_written::total 10688 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 167 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 30419 # Number of read requests accepted
> system.physmem.writeReqs 167 # Number of write requests accepted
> system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 1928 # Per bank write bursts
> system.physmem.perBankRdBursts::1 2077 # Per bank write bursts
> system.physmem.perBankRdBursts::2 2029 # Per bank write bursts
> system.physmem.perBankRdBursts::3 1927 # Per bank write bursts
> system.physmem.perBankRdBursts::4 2026 # Per bank write bursts
> system.physmem.perBankRdBursts::5 1899 # Per bank write bursts
> system.physmem.perBankRdBursts::6 1963 # Per bank write bursts
> system.physmem.perBankRdBursts::7 1862 # Per bank write bursts
> system.physmem.perBankRdBursts::8 1939 # Per bank write bursts
> system.physmem.perBankRdBursts::9 1933 # Per bank write bursts
> system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
> system.physmem.perBankRdBursts::11 1795 # Per bank write bursts
> system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
> system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
> system.physmem.perBankRdBursts::14 1821 # Per bank write bursts
> system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
> system.physmem.perBankWrBursts::0 15 # Per bank write bursts
> system.physmem.perBankWrBursts::1 95 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7 # Per bank write bursts
> system.physmem.perBankWrBursts::3 11 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6 # Per bank write bursts
> system.physmem.perBankWrBursts::5 0 # Per bank write bursts
> system.physmem.perBankWrBursts::6 12 # Per bank write bursts
> system.physmem.perBankWrBursts::7 0 # Per bank write bursts
> system.physmem.perBankWrBursts::8 0 # Per bank write bursts
> system.physmem.perBankWrBursts::9 5 # Per bank write bursts
> system.physmem.perBankWrBursts::10 3 # Per bank write bursts
> system.physmem.perBankWrBursts::11 0 # Per bank write bursts
> system.physmem.perBankWrBursts::12 0 # Per bank write bursts
> system.physmem.perBankWrBursts::13 0 # Per bank write bursts
> system.physmem.perBankWrBursts::14 0 # Per bank write bursts
> system.physmem.perBankWrBursts::15 0 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 65613689500 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 0 # Read request sizes (log2)
> system.physmem.readPktSize::3 0 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 30419 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 0 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 167 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
128,140c130,142
< system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see
146,150c148,152
< system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
160,219c162,272
< system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation
< system.physmem.totQLat 5969250 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests
< system.physmem.totBusLat 151785000 # Total cycles spent in databus access
< system.physmem.totBankLat 423720000 # Total cycles spent in bank access
< system.physmem.avgQLat 196.64 # Average queueing delay per request
< system.physmem.avgBankLat 13957.90 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 19154.54 # Average memory access latency
< system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
---
> system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation
> system.physmem.totQLat 92483500 # Total ticks spent queuing
> system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 434417500 # Total ticks spent accessing banks
> system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
221,240c274,297
< system.physmem.avgRdQLen 0.01 # Average read queue length over time
< system.physmem.avgWrQLen 12.39 # Average write queue length over time
< system.physmem.readRowHits 29864 # Number of row buffer hits during reads
< system.physmem.writeRowHits 96 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes
< system.physmem.avgGap 2143508.17 # Average gap between requests
< system.membus.throughput 29855634 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 1399 # Transaction distribution
< system.membus.trans_dist::ReadResp 1397 # Transaction distribution
< system.membus.trans_dist::Writeback 156 # Transaction distribution
< system.membus.trans_dist::ReadExReq 29001 # Transaction distribution
< system.membus.trans_dist::ReadExResp 29001 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 1955456 # Total data (bytes)
---
> system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing
> system.physmem.readRowHits 29156 # Number of row buffer hits during reads
> system.physmem.writeRowHits 97 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes
> system.physmem.avgGap 2145219.69 # Average gap between requests
> system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 29832782 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 1416 # Transaction distribution
> system.membus.trans_dist::ReadResp 1415 # Transaction distribution
> system.membus.trans_dist::Writeback 167 # Transaction distribution
> system.membus.trans_dist::ReadExReq 29003 # Transaction distribution
> system.membus.trans_dist::ReadExResp 29003 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 1957440 # Total data (bytes)
242c299
< system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks)
244c301
< system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks)
246,250c303,307
< system.cpu.branchPred.lookups 33858224 # Number of BP lookups
< system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits
---
> system.cpu.branchPred.lookups 33859770 # Number of BP lookups
> system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits
252,254c309,311
< system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions.
256c313
< system.cpu.numCycles 130994109 # number of cpu cycles simulated
---
> system.cpu.numCycles 131227460 # number of cpu cycles simulated
259,267c316,324
< system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps
269,273c326,330
< system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total)
275,283c332,340
< system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total)
287,309c344,366
< system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups
311c368
< system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing
314,328c371,385
< system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle
---
> system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle
330,338c387,395
< system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle
342c399
< system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle
344,374c401,431
< system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available
377,408c434,465
< system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued
411,423c468,480
< system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued
< system.cpu.iq.rate 2.292178 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued
> system.cpu.iq.rate 2.288206 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores
425,428c482,485
< system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed
431,432c488,489
< system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked
434,450c491,507
< system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute
453,460c510,517
< system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed
< system.cpu.iew.exec_branches 30818444 # Number of branches executed
< system.cpu.iew.exec_stores 32924311 # Number of stores executed
< system.cpu.iew.exec_rate 2.281453 # Inst execution rate
< system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 218253384 # num instructions producing a value
< system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed
> system.cpu.iew.exec_branches 30820824 # Number of branches executed
> system.cpu.iew.exec_stores 32925944 # Number of stores executed
> system.cpu.iew.exec_rate 2.277516 # Inst execution rate
> system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 218260008 # num instructions producing a value
> system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value
462,463c519,520
< system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back
465c522
< system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit
467,470c524,527
< system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle
472,480c529,537
< system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle
484c541
< system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle
495c552
< system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached
497,500c554,557
< system.cpu.rob.rob_reads 415712868 # The number of ROB reads
< system.cpu.rob.rob_writes 627529396 # The number of ROB writes
< system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 415950983 # The number of ROB reads
> system.cpu.rob.rob_writes 627545403 # The number of ROB writes
> system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling
504,514c561,571
< system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 483722109 # number of integer regfile reads
< system.cpu.int_regfile_writes 234582139 # number of integer regfile writes
< system.cpu.fp_regfile_reads 117 # number of floating regfile reads
< system.cpu.fp_regfile_writes 75 # number of floating regfile writes
< system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads
< system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes
< system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads
---
> system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 483744134 # number of integer regfile reads
> system.cpu.int_regfile_writes 234595253 # number of integer regfile writes
> system.cpu.fp_regfile_reads 141 # number of floating regfile reads
> system.cpu.fp_regfile_writes 77 # number of floating regfile writes
> system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads
> system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes
> system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads
516,528c573,585
< system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes)
---
> system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes)
530c587
< system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks)
532c589
< system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks)
534c591
< system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks)
536,540c593,597
< system.cpu.icache.tags.replacements 55 # number of replacements
< system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 57 # number of replacements
> system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1011 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 25295.833828 # Average number of references to valid blocks.
542,568c599,625
< system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits
< system.cpu.icache.overall_hits::total 25573067 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses
< system.cpu.icache.overall_misses::total 1295 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 25574088 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits
> system.cpu.icache.overall_hits::total 25574088 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses
> system.cpu.icache.overall_misses::total 1305 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses
575,581c632,638
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
585c642
< system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked
589,618c646,675
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 289 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 289 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1006 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1006 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1006 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1006 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1006 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1006 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67541250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 67541250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67541250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 67541250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67541250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67138.419483 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67138.419483 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 294 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 294 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 294 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 294 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 294 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1011 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1011 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1011 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
620,624c677,681
< system.cpu.l2cache.tags.replacements 461 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 20819.547231 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4029398 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 30381 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 132.628880 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 479 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4029616 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 132.548798 # Average number of references to valid blocks.
626,632c683,689
< system.cpu.l2cache.tags.occ_blocks::writebacks 19905.791561 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.283783 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 246.471887 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.607477 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020364 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.007522 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.635362 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 670.515764 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 244.870550 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.607028 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020463 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.007473 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.634964 # Average percentage of cache occupancy
634,639c691,696
< system.cpu.l2cache.ReadReq_hits::cpu.data 1993882 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1993899 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 2066630 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 2066630 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 53298 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 53298 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 1993866 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1993883 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 2066887 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 2066887 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 53320 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 53320 # number of ReadExReq hits
641,642c698,699
< system.cpu.l2cache.demand_hits::cpu.data 2047180 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2047197 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 2047186 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2047203 # number of demand (read+write) hits
644,702c701,759
< system.cpu.l2cache.overall_hits::cpu.data 2047180 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2047197 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1399 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 989 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 29411 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 30400 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 989 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 29411 # number of overall misses
< system.cpu.l2cache.overall_misses::total 30400 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 66362250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27817000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 94179250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1783074500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1783074500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 66362250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1810891500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1877253750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 66362250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1810891500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1877253750 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1006 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1994292 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1995298 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 2066630 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 2066630 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 82299 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 82299 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1006 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2076591 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2077597 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1006 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2076591 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2077597 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983101 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000206 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352386 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.352386 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983101 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.014163 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.014632 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983101 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.014163 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.014632 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67100.353893 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67846.341463 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67318.977841 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61483.207476 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61483.207476 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 61751.768092 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 61751.768092 # average overall miss latency
---
> system.cpu.l2cache.overall_hits::cpu.data 2047186 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2047203 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 994 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1416 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses
> system.cpu.l2cache.overall_misses::total 30419 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 2066887 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 2066887 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 82323 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 82323 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1011 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2076611 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2077622 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1011 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2076611 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2077622 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983185 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000212 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.000710 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352307 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.352307 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983185 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.014641 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency
711,756c768,813
< system.cpu.l2cache.writebacks::writebacks 156 # number of writebacks
< system.cpu.l2cache.writebacks::total 156 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 989 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1399 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 989 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 29411 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 30400 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 989 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 29411 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 30400 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53927250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22692500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 76619750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417840500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417840500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53927250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1440533000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 1494460250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53927250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1440533000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1494460250 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000206 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000701 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352386 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352386 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.014632 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.014632 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54527.047523 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55347.560976 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54767.512509 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.365884 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.365884 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency
---
> system.cpu.l2cache.writebacks::writebacks 167 # number of writebacks
> system.cpu.l2cache.writebacks::total 167 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1416 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 994 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 30419 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 994 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 30419 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55574500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24773500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80348000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1511756500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1511756500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55574500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1536530000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1592104500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55574500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1536530000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1592104500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352307 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352307 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55909.959759 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56742.937853 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52124.142330 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52124.142330 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency
758,792c815,849
< system.cpu.dcache.tags.replacements 2072493 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4069.881910 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 71371808 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2076589 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 34.369732 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 20650704250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4069.881910 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 40030061 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 40030061 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 31341747 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 31341747 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 71371808 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 71371808 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 71371808 # number of overall hits
< system.cpu.dcache.overall_hits::total 71371808 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2626396 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2626396 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 98005 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 98005 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2724401 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2724401 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2724401 # number of overall misses
< system.cpu.dcache.overall_misses::total 2724401 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 31387330250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 31387330250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2685755248 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2685755248 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34073085498 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34073085498 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34073085498 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34073085498 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 42656457 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 42656457 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.replacements 2072514 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits
> system.cpu.dcache.overall_hits::total 71413624 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 98059 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2723805 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2723805 # number of overall misses
> system.cpu.dcache.overall_misses::total 2723805 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399016250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31399016250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2779679498 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2779679498 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses)
795,815c852,872
< system.cpu.dcache.demand_accesses::cpu.data 74096209 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 74096209 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 74096209 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 74096209 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061571 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.061571 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003117 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.003117 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.036768 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.036768 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036768 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036768 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11950.722682 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11950.722682 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27404.267619 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27404.267619 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 12506.633751 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 12506.633751 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 32988 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked
817c874
< system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked
819c876
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.476080 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443930 # average number of cycles each access was blocked
823,864c880,921
< system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks
< system.cpu.dcache.writebacks::total 2066630 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631996 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 631996 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15814 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 15814 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 647810 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 647810 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 647810 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 647810 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994400 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1994400 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82191 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 82191 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2076591 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2076591 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2076591 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2076591 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994515250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994515250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397679498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397679498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392194748 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 24392194748 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392194748 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 24392194748 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046755 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046755 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.028026 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028026 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.136407 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.136407 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29172.044360 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29172.044360 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks
> system.cpu.dcache.writebacks::total 2066887 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency