7,11c7,11
< host_inst_rate 71115 # Simulator instruction rate (inst/s)
< host_op_rate 125222 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 29700736 # Simulator tick rate (ticks/s)
< host_mem_usage 413360 # Number of bytes of host memory used
< host_seconds 2221.59 # Real time elapsed on the host
---
> host_inst_rate 39069 # Simulator instruction rate (inst/s)
> host_op_rate 68794 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16316772 # Simulator tick rate (ticks/s)
> host_mem_usage 376348 # Number of bytes of host memory used
> host_seconds 4043.87 # Real time elapsed on the host
80c80
< system.physmem.totGap 65982842000 # Total gap between requests
---
> system.physmem.totGap 65982843000 # Total gap between requests
174,175c174,175
< system.physmem.totQLat 10444357 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests
---
> system.physmem.totQLat 10445857 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests
178c178
< system.physmem.avgQLat 343.72 # Average queueing delay per request
---
> system.physmem.avgQLat 343.77 # Average queueing delay per request
181c181
< system.physmem.avgMemAccLat 18811.37 # Average memory access latency
---
> system.physmem.avgMemAccLat 18811.42 # Average memory access latency
194c194
< system.physmem.avgGap 2155034.36 # Average gap between requests
---
> system.physmem.avgGap 2155034.39 # Average gap between requests
207c207
< system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
214c214
< system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
217,218c217,218
< system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed
463c463
< system.cpu.icache.tagsinuse 836.141366 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use
468c468
< system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor
477,494c477,494
< system.cpu.icache.ReadReq_misses::cpu.inst 1350 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1350 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1350 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1350 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1350 # number of overall misses
< system.cpu.icache.overall_misses::total 1350 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 65277000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 65277000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 25952050 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 25952050 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 25952050 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses
> system.cpu.icache.overall_misses::total 1351 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses
501,506c501,506
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 48353.333333 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency
515,520c515,520
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits
527,532c527,532
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52080000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 52080000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52080000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 52080000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52080000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 52080000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles
539,544c539,544
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50076.923077 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50077.884615 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50077.884615 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency
546,653d545
< system.cpu.dcache.replacements 2072071 # number of replacements
< system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use
< system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4072.565348 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
< system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
< system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321017500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 31321017500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 33409125998 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 33409125998 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 33409125998 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 33409125998 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.970796 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.970796 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 12267.153350 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 12267.153350 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
< system.cpu.dcache.writebacks::total 2066432 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983433500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983433500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23796285498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23796285498 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531267 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531267 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
655c547
< system.cpu.l2cache.tagsinuse 20806.359939 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use
661c553
< system.cpu.l2cache.occ_blocks::cpu.inst 692.491885 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 692.491887 # Average occupied blocks per requestor
693,695c585,587
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50832500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21222500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 72055000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50833500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21223000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 72056500 # number of ReadReq miss cycles
698,703c590,595
< system.cpu.l2cache.demand_miss_latency::cpu.inst 50832500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1220342500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1271175000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 50832500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1220342500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1271175000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 50833500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1220343000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1271176500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 50833500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1220343000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1271176500 # number of overall miss cycles
732,734c624,626
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49884.690873 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50053.066038 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 49934.164934 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49885.672228 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50054.245283 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 49935.204435 # average ReadReq miss latency
737,742c629,634
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 41754.582184 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency
766,768c658,660
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37999583 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880149 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles
773,778c665,670
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38000083 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840076044 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 878076127 # number of overall MSHR miss cycles
792,794c684,686
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency
799,804c691,696
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
805a698,805
> system.cpu.dcache.replacements 2072071 # number of replacements
> system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use
> system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
> system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
> system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
> system.cpu.dcache.writebacks::total 2066432 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 71115 # Simulator instruction rate (inst/s)
< host_op_rate 125222 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 29700736 # Simulator tick rate (ticks/s)
< host_mem_usage 413360 # Number of bytes of host memory used
< host_seconds 2221.59 # Real time elapsed on the host
---
> host_inst_rate 39069 # Simulator instruction rate (inst/s)
> host_op_rate 68794 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16316772 # Simulator tick rate (ticks/s)
> host_mem_usage 376348 # Number of bytes of host memory used
> host_seconds 4043.87 # Real time elapsed on the host
80c80
< system.physmem.totGap 65982842000 # Total gap between requests
---
> system.physmem.totGap 65982843000 # Total gap between requests
174,175c174,175
< system.physmem.totQLat 10444357 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests
---
> system.physmem.totQLat 10445857 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests
178c178
< system.physmem.avgQLat 343.72 # Average queueing delay per request
---
> system.physmem.avgQLat 343.77 # Average queueing delay per request
181c181
< system.physmem.avgMemAccLat 18811.37 # Average memory access latency
---
> system.physmem.avgMemAccLat 18811.42 # Average memory access latency
194c194
< system.physmem.avgGap 2155034.36 # Average gap between requests
---
> system.physmem.avgGap 2155034.39 # Average gap between requests
207c207
< system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
214c214
< system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
217,218c217,218
< system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed
463c463
< system.cpu.icache.tagsinuse 836.141366 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use
468c468
< system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor
477,494c477,494
< system.cpu.icache.ReadReq_misses::cpu.inst 1350 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1350 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1350 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1350 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1350 # number of overall misses
< system.cpu.icache.overall_misses::total 1350 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 65277000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 65277000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 25952050 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 25952050 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 25952050 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses
> system.cpu.icache.overall_misses::total 1351 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses
501,506c501,506
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 48353.333333 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency
515,520c515,520
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits
527,532c527,532
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52080000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 52080000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52080000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 52080000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52080000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 52080000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles
539,544c539,544
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50076.923077 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50077.884615 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50077.884615 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency
546,653d545
< system.cpu.dcache.replacements 2072071 # number of replacements
< system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use
< system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4072.565348 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
< system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
< system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321017500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 31321017500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 33409125998 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 33409125998 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 33409125998 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 33409125998 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.970796 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.970796 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 12267.153350 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 12267.153350 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
< system.cpu.dcache.writebacks::total 2066432 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983433500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983433500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23796285498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23796285498 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531267 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531267 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
655c547
< system.cpu.l2cache.tagsinuse 20806.359939 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use
661c553
< system.cpu.l2cache.occ_blocks::cpu.inst 692.491885 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 692.491887 # Average occupied blocks per requestor
693,695c585,587
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50832500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21222500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 72055000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50833500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21223000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 72056500 # number of ReadReq miss cycles
698,703c590,595
< system.cpu.l2cache.demand_miss_latency::cpu.inst 50832500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1220342500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1271175000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 50832500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1220342500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1271175000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 50833500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1220343000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1271176500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 50833500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1220343000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1271176500 # number of overall miss cycles
732,734c624,626
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49884.690873 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50053.066038 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 49934.164934 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49885.672228 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50054.245283 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 49935.204435 # average ReadReq miss latency
737,742c629,634
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 41754.582184 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency
766,768c658,660
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37999583 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880149 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles
773,778c665,670
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38000083 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840076044 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 878076127 # number of overall MSHR miss cycles
792,794c684,686
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency
799,804c691,696
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
805a698,805
> system.cpu.dcache.replacements 2072071 # number of replacements
> system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use
> system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
> system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
> system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
> system.cpu.dcache.writebacks::total 2066432 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate