3,5c3,5
< sim_seconds 0.066546 # Number of seconds simulated
< sim_ticks 66545720000 # Number of ticks simulated
< final_tick 66545720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.068340 # Number of seconds simulated
> sim_ticks 68340167000 # Number of ticks simulated
> final_tick 68340167000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 128459 # Simulator instruction rate (inst/s)
< host_op_rate 226196 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 54107733 # Simulator tick rate (ticks/s)
< host_mem_usage 365700 # Number of bytes of host memory used
< host_seconds 1229.87 # Real time elapsed on the host
---
> host_inst_rate 107513 # Simulator instruction rate (inst/s)
> host_op_rate 189313 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 46506224 # Simulator tick rate (ticks/s)
> host_mem_usage 365660 # Number of bytes of host memory used
> host_seconds 1469.48 # Real time elapsed on the host
14,36c14,36
< system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 1892992 # Number of bytes read from this memory
< system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 20032 # Number of bytes written to this memory
< system.physmem.bytes_written::total 20032 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 29578 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 313 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 313 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1027143 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 28446488 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 29473631 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1027143 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1027143 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 301026 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 301026 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 301026 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1027143 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 28446488 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 29774657 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 68608 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 1893120 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 68608 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 68608 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory
> system.physmem.bytes_written::total 20288 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 1072 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 29580 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 317 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1003919 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 27701425 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 28705344 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1003919 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1003919 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 296868 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 296868 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 296868 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1003919 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 27701425 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 29002212 # Total bandwidth to/from this memory (bytes/s)
38c38
< system.cpu.numCycles 133091441 # number of cpu cycles simulated
---
> system.cpu.numCycles 136680335 # number of cpu cycles simulated
41,45c41,45
< system.cpu.BPredUnit.lookups 36127369 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 36127369 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 1087558 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 25661122 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 25550646 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 36129289 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 36129289 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 1086629 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 25668657 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 25566381 # Number of BTB hits
49,62c49,62
< system.cpu.fetch.icacheStallCycles 27995643 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 196446977 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 36127369 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 25550646 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 59425857 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 8408654 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 38346383 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 123 # Number of stall cycles due to pending traps
< system.cpu.fetch.CacheLines 27275955 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 142407 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 133058866 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.595223 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.362713 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 28038648 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 196448149 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 36129289 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 25566381 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 59446336 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 8437809 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 41835148 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 182 # Number of stall cycles due to pending traps
> system.cpu.fetch.CacheLines 27320717 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 151811 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 136641889 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.527241 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.343736 # Number of instructions fetched each cycle (Total)
64,72c64,72
< system.cpu.fetch.rateDist::0 76373838 57.40% 57.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2167538 1.63% 59.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 2997061 2.25% 61.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 4104688 3.08% 64.36% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 8024100 6.03% 70.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 5043618 3.79% 74.19% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 2895035 2.18% 76.36% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1466845 1.10% 77.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 29986143 22.54% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 79944033 58.51% 58.51% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2167208 1.59% 60.09% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 2997757 2.19% 62.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 4111297 3.01% 65.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 8027988 5.88% 71.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 5053640 3.70% 74.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 2897429 2.12% 76.99% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1474644 1.08% 78.07% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 29967893 21.93% 100.00% # Number of instructions fetched each cycle (Total)
76,99c76,99
< system.cpu.fetch.rateDist::total 133058866 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.271448 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.476030 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 40459991 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 29238616 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 46513629 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 9555795 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 7290835 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 341218691 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 7290835 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 45832356 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 4342736 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 9009 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 50371616 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 25212314 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 337359064 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 3751 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 23039182 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 70135 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 414697998 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1009810700 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1009808348 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 2352 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 136641889 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.264334 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.437282 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 40756149 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 32464330 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 46271327 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 9828540 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 7321543 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 341364323 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 7321543 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 46061495 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 6368629 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 8995 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 50367831 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 26513396 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 337564097 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 5026 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 24245573 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 73928 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 414895608 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1010438546 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1010435932 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 2614 # Number of floating rename lookups
101c101
< system.cpu.rename.UndoneMaps 73687058 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 73884668 # Number of HB maps that are undone due to squashing
103,118c103,118
< system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 55957632 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 108146065 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 37162932 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 46284047 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 7887005 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 331670931 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2660 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 311367761 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 187011 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 53218475 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 92468498 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 133058866 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.340075 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.723307 # Number of insts issued each cycle
---
> system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 57387793 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 108215751 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 37227533 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 46388866 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 7855106 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 331925513 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2461 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 311467723 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 186069 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 53480941 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 93052835 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 2015 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 136641889 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.279445 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.722907 # Number of insts issued each cycle
120,128c120,128
< system.cpu.iq.issued_per_cycle::0 27262165 20.49% 20.49% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 17087897 12.84% 33.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 25427949 19.11% 52.44% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 31141299 23.40% 75.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 17714013 13.31% 89.16% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 9070422 6.82% 95.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 3766330 2.83% 98.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1516401 1.14% 99.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 72390 0.05% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 29493706 21.58% 21.58% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 18268502 13.37% 34.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 26067174 19.08% 54.03% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 31248056 22.87% 76.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 17426975 12.75% 89.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 8824728 6.46% 96.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 3769643 2.76% 98.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1473533 1.08% 99.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 69572 0.05% 100.00% # Number of insts issued each cycle
132c132
< system.cpu.iq.issued_per_cycle::total 133058866 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 136641889 # Number of insts issued each cycle
134,164c134,164
< system.cpu.iq.fu_full::IntAlu 23137 1.10% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 1959411 92.81% 93.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 128735 6.10% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 22788 1.09% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 1944579 92.77% 93.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 128653 6.14% 100.00% # attempts to use FU when none available
167,198c167,198
< system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 177167866 56.90% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 103 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 99703270 32.02% 88.93% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 34465151 11.07% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 177257579 56.91% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 99693088 32.01% 88.93% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 34487693 11.07% 100.00% # Type of FU issued
201,213c201,213
< system.cpu.iq.FU_type_0::total 311367761 # Type of FU issued
< system.cpu.iq.rate 2.339503 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2111283 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.006781 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 758091805 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 384922588 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 308230879 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 877 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 1235 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 313447268 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 405 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 52556752 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 311467723 # Type of FU issued
> system.cpu.iq.rate 2.278804 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2096020 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.006729 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 761858485 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 385440526 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 308377955 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 939 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 1362 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 296 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 313534078 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 418 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 52563213 # Number of loads that had data forwarded from stores
215,218c215,218
< system.cpu.iew.lsq.thread0.squashedLoads 17366677 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 97430 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 32398 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 5723181 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 17436363 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 94862 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 33518 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 5787782 # Number of stores squashed
221,222c221,222
< system.cpu.iew.lsq.thread0.rescheduledLoads 3328 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 3855 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 3294 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 766 # Number of times an access to memory failed due to the cache being blocked
224,240c224,240
< system.cpu.iew.iewSquashCycles 7290835 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 316808 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 29284 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 331673591 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 45940 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 108146065 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 37162932 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 478 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 230 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 5075 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 32398 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 615271 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 578255 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1193526 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 309404440 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 99168969 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1963321 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 7321543 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 823106 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 106434 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 331927974 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 49382 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 108215751 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 37227533 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1169 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 29139 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 33518 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 614396 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 578149 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1192545 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 309546199 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 99164124 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1921524 # Number of squashed instructions skipped in execute
243,250c243,250
< system.cpu.iew.exec_refs 133248637 # number of memory reference insts executed
< system.cpu.iew.exec_branches 31530009 # Number of branches executed
< system.cpu.iew.exec_stores 34079668 # Number of stores executed
< system.cpu.iew.exec_rate 2.324751 # Inst execution rate
< system.cpu.iew.wb_sent 308773966 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 308231167 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 227547609 # num instructions producing a value
< system.cpu.iew.wb_consumers 467201547 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 133270548 # number of memory reference insts executed
> system.cpu.iew.exec_branches 31554842 # Number of branches executed
> system.cpu.iew.exec_stores 34106424 # Number of stores executed
> system.cpu.iew.exec_rate 2.264746 # Inst execution rate
> system.cpu.iew.wb_sent 308908711 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 308378251 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 227159905 # num instructions producing a value
> system.cpu.iew.wb_consumers 466461304 # num instructions consuming a value
252,253c252,253
< system.cpu.iew.wb_rate 2.315935 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.487044 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 2.256201 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.486986 # average fanout of values written-back
257c257
< system.cpu.commit.commitSquashedInsts 53483171 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 53739498 # The number of squashed insts skipped by commit
259,262c259,262
< system.cpu.commit.branchMispredicts 1087573 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 125768031 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.211949 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.676987 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 1086653 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 129320346 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.151189 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.664667 # Number of insts commited each cycle
264,272c264,272
< system.cpu.commit.committed_per_cycle::0 45423361 36.12% 36.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 24208560 19.25% 55.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 16905668 13.44% 68.81% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 12615481 10.03% 78.84% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 3337463 2.65% 81.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 3557456 2.83% 84.32% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 2707212 2.15% 86.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1156864 0.92% 87.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 15855966 12.61% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 48978430 37.87% 37.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 24328173 18.81% 56.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 16731567 12.94% 69.62% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 12545678 9.70% 79.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 3454921 2.67% 82.00% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 3553253 2.75% 84.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 2757236 2.13% 86.88% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1133891 0.88% 87.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 15837197 12.25% 100.00% # Number of insts commited each cycle
276c276
< system.cpu.commit.committed_per_cycle::total 125768031 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 129320346 # Number of insts commited each cycle
287c287
< system.cpu.commit.bw_lim_events 15855966 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 15837197 # number cycles where commit BW limit reached
289,292c289,292
< system.cpu.rob.rob_reads 441587755 # The number of ROB reads
< system.cpu.rob.rob_writes 670650798 # The number of ROB writes
< system.cpu.timesIdled 771 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 32575 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 445415166 # The number of ROB reads
> system.cpu.rob.rob_writes 671194708 # The number of ROB writes
> system.cpu.timesIdled 2012 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 38446 # Total number of cycles that the CPU has spent unscheduled due to idling
296,307c296,307
< system.cpu.cpi 0.842412 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.842412 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.187068 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.187068 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 705256530 # number of integer regfile reads
< system.cpu.int_regfile_writes 373197329 # number of integer regfile writes
< system.cpu.fp_regfile_reads 323 # number of floating regfile reads
< system.cpu.fp_regfile_writes 179 # number of floating regfile writes
< system.cpu.misc_regfile_reads 197910485 # number of misc regfile reads
< system.cpu.icache.replacements 89 # number of replacements
< system.cpu.icache.tagsinuse 845.508761 # Cycle average of tags in use
< system.cpu.icache.total_refs 27274550 # Total number of references to valid blocks.
---
> system.cpu.cpi 0.865128 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.865128 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.155898 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.155898 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 705405399 # number of integer regfile reads
> system.cpu.int_regfile_writes 373270395 # number of integer regfile writes
> system.cpu.fp_regfile_reads 345 # number of floating regfile reads
> system.cpu.fp_regfile_writes 188 # number of floating regfile writes
> system.cpu.misc_regfile_reads 197984504 # number of misc regfile reads
> system.cpu.icache.replacements 90 # number of replacements
> system.cpu.icache.tagsinuse 845.686115 # Cycle average of tags in use
> system.cpu.icache.total_refs 27319306 # Total number of references to valid blocks.
309c309
< system.cpu.icache.avg_refs 25277.618165 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 25319.097312 # Average number of references to valid blocks.
311,349c311,349
< system.cpu.icache.occ_blocks::cpu.inst 845.508761 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.412846 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.412846 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 27274554 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27274554 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27274554 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27274554 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27274554 # number of overall hits
< system.cpu.icache.overall_hits::total 27274554 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1401 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1401 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1401 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1401 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1401 # number of overall misses
< system.cpu.icache.overall_misses::total 1401 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 49669500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 49669500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 49669500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 49669500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 49669500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 49669500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27275955 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27275955 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27275955 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27275955 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27275955 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27275955 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35452.890792 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 35452.890792 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 35452.890792 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 35452.890792 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 35452.890792 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 35452.890792 # average overall miss latency
---
> system.cpu.icache.occ_blocks::cpu.inst 845.686115 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.412933 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.412933 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 27319307 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27319307 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27319307 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27319307 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27319307 # number of overall hits
> system.cpu.icache.overall_hits::total 27319307 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1410 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1410 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1410 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1410 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1410 # number of overall misses
> system.cpu.icache.overall_misses::total 1410 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 52106500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 52106500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 52106500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 52106500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 52106500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 52106500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27320717 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27320717 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27320717 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27320717 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27320717 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27320717 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36954.964539 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 36954.964539 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 36954.964539 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 36954.964539 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 36954.964539 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 36954.964539 # average overall miss latency
358,375c358,375
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 317 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 317 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 317 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 317 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 317 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 317 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1084 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1084 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1084 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1084 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1084 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1084 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37853000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 37853000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37853000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 37853000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37853000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 37853000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1082 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1082 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1082 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1082 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1082 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1082 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39682000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 39682000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39682000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 39682000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39682000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 39682000 # number of overall MSHR miss cycles
382,387c382,387
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34919.741697 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34919.741697 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34919.741697 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 34919.741697 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34919.741697 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 34919.741697 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36674.676525 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36674.676525 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36674.676525 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 36674.676525 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36674.676525 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 36674.676525 # average overall mshr miss latency
389,423c389,423
< system.cpu.dcache.replacements 2072094 # number of replacements
< system.cpu.dcache.tagsinuse 4072.411380 # Cycle average of tags in use
< system.cpu.dcache.total_refs 75633227 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 2076190 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 36.428856 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 22601159000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4072.411380 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.994241 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.994241 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 44275835 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 44275835 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 31357376 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 31357376 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 75633211 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 75633211 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 75633211 # number of overall hits
< system.cpu.dcache.overall_hits::total 75633211 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2285631 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2285631 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 82375 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 82375 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2368006 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2368006 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2368006 # number of overall misses
< system.cpu.dcache.overall_misses::total 2368006 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12197942000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12197942000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1391130788 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1391130788 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13589072788 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13589072788 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13589072788 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13589072788 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 46561466 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 46561466 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.replacements 2072150 # number of replacements
> system.cpu.dcache.tagsinuse 4072.380318 # Cycle average of tags in use
> system.cpu.dcache.total_refs 75593684 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 2076246 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 36.408828 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 22734551000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4072.380318 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.994233 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.994233 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 44236411 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 44236411 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 31357262 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 31357262 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 75593673 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 75593673 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 75593673 # number of overall hits
> system.cpu.dcache.overall_hits::total 75593673 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2315078 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2315078 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 82489 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 82489 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2397567 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2397567 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2397567 # number of overall misses
> system.cpu.dcache.overall_misses::total 2397567 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 16784018500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 16784018500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571310000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1571310000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18355328500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18355328500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18355328500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18355328500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 46551489 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 46551489 # number of ReadReq accesses(hits+misses)
426,445c426,445
< system.cpu.dcache.demand_accesses::cpu.data 78001217 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 78001217 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 78001217 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 78001217 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049088 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.049088 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002620 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.002620 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.030359 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.030359 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.030359 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.030359 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5336.794084 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 5336.794084 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16887.778914 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 16887.778914 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 5738.614171 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 5738.614171 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 5738.614171 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 5738.614171 # average overall miss latency
---
> system.cpu.dcache.demand_accesses::cpu.data 77991240 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 77991240 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 77991240 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 77991240 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049732 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.049732 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.030741 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.030741 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.030741 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.030741 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7249.871711 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 7249.871711 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19048.721648 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 19048.721648 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 7655.814624 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 7655.814624 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 7655.814624 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 7655.814624 # average overall miss latency
454,495c454,495
< system.cpu.dcache.writebacks::writebacks 2064779 # number of writebacks
< system.cpu.dcache.writebacks::total 2064779 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291515 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 291515 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 294 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 294 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 291809 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 291809 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 291809 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 291809 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994116 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1994116 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82081 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 82081 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2076197 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2076197 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2076197 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2076197 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4625699000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4625699000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1142906788 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1142906788 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5768605788 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 5768605788 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5768605788 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 5768605788 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042828 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042828 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.026617 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.026617 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2319.673981 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2319.673981 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13924.133332 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13924.133332 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2778.448186 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 2778.448186 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2778.448186 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 2778.448186 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 2064802 # number of writebacks
> system.cpu.dcache.writebacks::total 2064802 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320846 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 320846 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 321315 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 321315 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 321315 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 321315 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994232 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1994232 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82020 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 82020 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2076252 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2076252 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2076252 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2076252 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6184007000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6184007000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313707000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313707000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497714000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7497714000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497714000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7497714000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042839 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042839 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.026622 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.026622 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.946630 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.946630 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16016.910510 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16016.910510 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.177256 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.177256 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.177256 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.177256 # average overall mshr miss latency
497,501c497,501
< system.cpu.l2cache.replacements 1461 # number of replacements
< system.cpu.l2cache.tagsinuse 19902.779056 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 4027062 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 30627 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 131.487315 # Average number of references to valid blocks.
---
> system.cpu.l2cache.replacements 1468 # number of replacements
> system.cpu.l2cache.tagsinuse 20085.228280 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 4027172 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 30631 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 131.473736 # Average number of references to valid blocks.
503,514c503,514
< system.cpu.l2cache.occ_blocks::writebacks 19403.134879 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 269.722529 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 229.921648 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.592137 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.008231 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.007017 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.607385 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 11 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1993423 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1993434 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 2064779 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 2064779 # number of Writeback hits
---
> system.cpu.l2cache.occ_blocks::writebacks 19589.019970 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 262.767533 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 233.440777 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.597809 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.008019 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.007124 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.612953 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1993528 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1993535 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 2064802 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 2064802 # number of Writeback hits
517,548c517,548
< system.cpu.l2cache.ReadExReq_hits::cpu.data 53191 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 53191 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2046614 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2046625 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2046614 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2046625 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 585 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1653 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 28993 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 28993 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 29578 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 30646 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 29578 # number of overall misses
< system.cpu.l2cache.overall_misses::total 30646 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36597500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20018000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 56615500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988202000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 988202000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36597500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1008220000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1044817500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36597500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1008220000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1044817500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 53141 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 53141 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2046669 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2046676 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2046669 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2046676 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 588 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1660 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 28992 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 28992 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 29580 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 30652 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 1072 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 29580 # number of overall misses
> system.cpu.l2cache.overall_misses::total 30652 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38191500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20878500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 59070000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989300500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 989300500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 38191500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1010179000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1048370500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 38191500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1010179000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1048370500 # number of overall miss cycles
550,557c550,557
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1994008 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1995087 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 2064779 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 2064779 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 82184 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 82184 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1994116 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1995195 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 2064802 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 2064802 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses)
559,560c559,560
< system.cpu.l2cache.demand_accesses::cpu.data 2076192 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2077271 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 2076249 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2077328 # number of demand (read+write) accesses
562,587c562,587
< system.cpu.l2cache.overall_accesses::cpu.data 2076192 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2077271 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989805 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000293 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352782 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.352782 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989805 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.014246 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989805 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.014246 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.322097 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34218.803419 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 34250.151240 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.158245 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.158245 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.322097 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34086.821286 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 34093.111662 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.322097 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34086.821286 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 34093.111662 # average overall miss latency
---
> system.cpu.l2cache.overall_accesses::cpu.data 2076249 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2077328 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993513 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.000832 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993513 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.014247 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993513 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.014247 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.399254 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35507.653061 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 35584.337349 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.223648 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.223648 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 34202.352212 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 34202.352212 # average overall miss latency
596,639c596,639
< system.cpu.l2cache.writebacks::writebacks 313 # number of writebacks
< system.cpu.l2cache.writebacks::total 313 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1653 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 29578 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 29578 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33172000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18151500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51323500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 898797500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 898797500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33172000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 916949000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 950121000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33172000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 916949000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 950121000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352782 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352782 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014246 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014246 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31059.925094 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31028.205128 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31048.699335 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks
> system.cpu.l2cache.writebacks::total 317 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1660 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 29580 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 29580 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34797000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19023000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53820000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899044500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899044500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34797000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918067500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 952864500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34797000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918067500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 952864500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000832 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32459.888060 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32352.040816 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32421.686747 # average ReadReq mshr miss latency
642,649c642,649
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.500121 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.500121 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.088990 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.088990 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency