7,11c7,11
< host_inst_rate 83209 # Simulator instruction rate (inst/s)
< host_op_rate 146518 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 32444685 # Simulator tick rate (ticks/s)
< host_mem_usage 451056 # Number of bytes of host memory used
< host_seconds 1898.69 # Real time elapsed on the host
---
> host_inst_rate 109389 # Simulator instruction rate (inst/s)
> host_op_rate 192617 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 42652748 # Simulator tick rate (ticks/s)
> host_mem_usage 458300 # Number of bytes of host memory used
> host_seconds 1444.28 # Real time elapsed on the host
225,226c225,226
< system.physmem.totQLat 132992250 # Total ticks spent queuing
< system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 132940250 # Total ticks spent queuing
> system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM
228c228
< system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst
230c230
< system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst
252,256c252,256
< system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ)
< system.physmem_0.averagePower 673.233667 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states
---
> system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ)
> system.physmem_0.averagePower 673.233237 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states
259c259
< system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states
266,270c266,270
< system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ)
< system.physmem_1.averagePower 673.432156 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states
---
> system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ)
> system.physmem_1.averagePower 673.431985 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states
273c273
< system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states
328c328
< system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking
331,332c331,332
< system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename
---
> system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename
335,339c335,339
< system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups
---
> system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups
342c342
< system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing
345c345
< system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer
361,367c361,367
< system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle
404c404
< system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available
444c444
< system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested
446c446
< system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads
452c452
< system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses
467c467
< system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking
---
> system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking
474c474
< system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall
488c488
< system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit
---
> system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit
503,504c503,504
< system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle
506,510c506,510
< system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle
573c573
< system.cpu.int_regfile_writes 239432261 # number of integer regfile writes
---
> system.cpu.int_regfile_writes 239432260 # number of integer regfile writes
612,619c612,619
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles
636,644c636,644
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked
648c648
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked
670,677c670,677
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles
686,693c686,693
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency
696c696
< system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use
701c701
< system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor
724,729c724,729
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles
742,747c742,747
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency
768,773c768,773
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles
780,785c780,785
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency
788c788
< system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use
793,795c793,795
< system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor
837,848c837,848
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles
877,888c877,888
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency
913,924c913,924
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles
939,950c939,950
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency
951a952,957
> system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
969,970c975,976
< system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram
972,974c978,980
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
976,977c982,983
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1008c1014
< system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks)
< host_inst_rate 83209 # Simulator instruction rate (inst/s)
< host_op_rate 146518 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 32444685 # Simulator tick rate (ticks/s)
< host_mem_usage 451056 # Number of bytes of host memory used
< host_seconds 1898.69 # Real time elapsed on the host
---
> host_inst_rate 109389 # Simulator instruction rate (inst/s)
> host_op_rate 192617 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 42652748 # Simulator tick rate (ticks/s)
> host_mem_usage 458300 # Number of bytes of host memory used
> host_seconds 1444.28 # Real time elapsed on the host
225,226c225,226
< system.physmem.totQLat 132992250 # Total ticks spent queuing
< system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 132940250 # Total ticks spent queuing
> system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM
228c228
< system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst
230c230
< system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst
252,256c252,256
< system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ)
< system.physmem_0.averagePower 673.233667 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states
---
> system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ)
> system.physmem_0.averagePower 673.233237 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states
259c259
< system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states
266,270c266,270
< system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ)
< system.physmem_1.averagePower 673.432156 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states
---
> system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ)
> system.physmem_1.averagePower 673.431985 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states
273c273
< system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states
328c328
< system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking
331,332c331,332
< system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename
---
> system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename
335,339c335,339
< system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups
---
> system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups
342c342
< system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing
345c345
< system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer
361,367c361,367
< system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle
404c404
< system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available
444c444
< system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested
446c446
< system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads
452c452
< system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses
467c467
< system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking
---
> system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking
474c474
< system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall
488c488
< system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit
---
> system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit
503,504c503,504
< system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle
506,510c506,510
< system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle
573c573
< system.cpu.int_regfile_writes 239432261 # number of integer regfile writes
---
> system.cpu.int_regfile_writes 239432260 # number of integer regfile writes
612,619c612,619
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles
636,644c636,644
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked
648c648
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked
670,677c670,677
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles
686,693c686,693
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency
696c696
< system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use
701c701
< system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor
724,729c724,729
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles
742,747c742,747
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency
768,773c768,773
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles
780,785c780,785
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency
788c788
< system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use
793,795c793,795
< system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor
837,848c837,848
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles
877,888c877,888
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency
913,924c913,924
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles
939,950c939,950
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency
951a952,957
> system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
969,970c975,976
< system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram
972,974c978,980
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
976,977c982,983
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1008c1014
< system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks)