Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

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stats.txt (10726:8a20e2a1562d)	stats.txt (10736:4433fb00fa7d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062113 # Number of seconds simulated 4sim_ticks 62113055500 # Number of ticks simulated 5final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 113198 # Simulator instruction rate (inst/s) 8host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44503726 # Simulator tick rate (ticks/s) 10host_mem_usage 454072 # Number of bytes of host memory used 11host_seconds 1395.68 # Real time elapsed on the host 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory 22system.physmem.bytes_written::total 10624 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 166 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30436 # Number of read requests accepted 40system.physmem.writeReqs 166 # Number of write requests accepted 41system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue 45system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1923 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2063 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2030 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1928 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2026 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1903 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1964 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1866 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1938 # Per bank write bursts 60system.physmem.perBankRdBursts::9 1940 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1805 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1795 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1779 # Per bank write bursts 67system.physmem.perBankWrBursts::0 15 # Per bank write bursts 68system.physmem.perBankWrBursts::1 80 # Per bank write bursts 69system.physmem.perBankWrBursts::2 11 # Per bank write bursts 70system.physmem.perBankWrBursts::3 10 # Per bank write bursts 71system.physmem.perBankWrBursts::4 7 # Per bank write bursts 72system.physmem.perBankWrBursts::5 0 # Per bank write bursts 73system.physmem.perBankWrBursts::6 13 # Per bank write bursts 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5 # Per bank write bursts 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 62113012500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 30436 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 166 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads 222system.physmem.totQLat 135350500 # Total ticks spent queuing 223system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM 224system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers 225system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst 226system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 227system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst 228system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s 229system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s 230system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s 231system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s 232system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 233system.physmem.busUtil 0.25 # Data bus utilization in percentage 234system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads 235system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 236system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 237system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing 238system.physmem.readRowHits 27681 # Number of row buffer hits during reads 239system.physmem.writeRowHits 96 # Number of row buffer hits during writes 240system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads 241system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes 242system.physmem.avgGap 2029704.35 # Average gap between requests 243system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined 244system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ) 245system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ) 246system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ) 247system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ) 248system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) 249system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ) 250system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ) 251system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ) 252system.physmem_0.averagePower 673.255215 # Core power per rank (mW) 253system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states 254system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states 255system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states 257system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 258system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) 259system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) 260system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ) 261system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 262system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) 263system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ) 264system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ) 265system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ) 266system.physmem_1.averagePower 673.417815 # Core power per rank (mW) 267system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states 268system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states 269system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 270system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states 271system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 272system.cpu.branchPred.lookups 37409115 # Number of BP lookups 273system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted 274system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect 275system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups 276system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits 277system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 278system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage 279system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target. 280system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions. 281system.cpu_clk_domain.clock 500 # Clock period in ticks 282system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 283system.cpu.workload.num_syscalls 444 # Number of system calls 284system.cpu.numCycles 124226112 # number of cpu cycles simulated 285system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 286system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 287system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss 288system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed 289system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered 290system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken 291system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked 292system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing 293system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 294system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps 295system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 296system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR 297system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched 298system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed 299system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle 317system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle 318system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle 319system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked 320system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running 321system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking 322system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing 323system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode 324system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename 331system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full 332system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full 333system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full 334system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full 335system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed 336system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made 337system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups 338system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups 339system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 340system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing 341system.cpu.rename.serializingInsts 478 # count of serializing insts renamed 342system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed 343system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer 344system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit. 345system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit. 346system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads. 347system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores. 348system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ 350system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued 351system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued 352system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling 353system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph 354system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed 355system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle 372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available 403system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued 407system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued 408system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued 409system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued 436system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued 437system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued 441system.cpu.iq.rate 2.479264 # Inst issue rate 442system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested 443system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst) 444system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads 445system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes 446system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses 447system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads 448system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes 449system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses 450system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses 451system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses 452system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores 453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed 455system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed 456system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations 457system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed 458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 459system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 460system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled 461system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked 462system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 463system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing 464system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking 465system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking 466system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ 467system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch 468system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions 469system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions 470system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions 471system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall 472system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall 473system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations 474system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly 475system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly 476system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute 477system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions 478system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed 479system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute 480system.cpu.iew.exec_swp 0 # number of swp insts executed 481system.cpu.iew.exec_nop 0 # number of nop insts executed 482system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed 483system.cpu.iew.exec_branches 31536553 # Number of branches executed 484system.cpu.iew.exec_stores 33820383 # Number of stores executed 485system.cpu.iew.exec_rate 2.470626 # Inst execution rate 486system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit 487system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back 488system.cpu.iew.wb_producers 231581512 # num instructions producing a value 489system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value 490system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 491system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle 492system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back 493system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 494system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit 495system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 496system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted 497system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle 514system.cpu.commit.committedInsts 157988547 # Number of instructions committed 515system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 516system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 517system.cpu.commit.refs 122219137 # Number of memory references committed 518system.cpu.commit.loads 90779385 # Number of loads committed 519system.cpu.commit.membars 0 # Number of memory barriers committed 520system.cpu.commit.branches 29309705 # Number of branches committed 521system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 522system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 523system.cpu.commit.function_calls 4237596 # Number of function calls committed. 524system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 525system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 526system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 527system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 531system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 532system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 533system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 554system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 555system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 559system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062113 # Number of seconds simulated 4sim_ticks 62113055500 # Number of ticks simulated 5final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 113198 # Simulator instruction rate (inst/s) 8host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44503726 # Simulator tick rate (ticks/s) 10host_mem_usage 454072 # Number of bytes of host memory used 11host_seconds 1395.68 # Real time elapsed on the host 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory 22system.physmem.bytes_written::total 10624 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 166 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30436 # Number of read requests accepted 40system.physmem.writeReqs 166 # Number of write requests accepted 41system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue 45system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1923 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2063 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2030 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1928 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2026 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1903 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1964 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1866 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1938 # Per bank write bursts 60system.physmem.perBankRdBursts::9 1940 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1805 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1795 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1779 # Per bank write bursts 67system.physmem.perBankWrBursts::0 15 # Per bank write bursts 68system.physmem.perBankWrBursts::1 80 # Per bank write bursts 69system.physmem.perBankWrBursts::2 11 # Per bank write bursts 70system.physmem.perBankWrBursts::3 10 # Per bank write bursts 71system.physmem.perBankWrBursts::4 7 # Per bank write bursts 72system.physmem.perBankWrBursts::5 0 # Per bank write bursts 73system.physmem.perBankWrBursts::6 13 # Per bank write bursts 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5 # Per bank write bursts 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 62113012500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 30436 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 166 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads 222system.physmem.totQLat 135350500 # Total ticks spent queuing 223system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM 224system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers 225system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst 226system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 227system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst 228system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s 229system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s 230system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s 231system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s 232system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 233system.physmem.busUtil 0.25 # Data bus utilization in percentage 234system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads 235system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 236system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 237system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing 238system.physmem.readRowHits 27681 # Number of row buffer hits during reads 239system.physmem.writeRowHits 96 # Number of row buffer hits during writes 240system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads 241system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes 242system.physmem.avgGap 2029704.35 # Average gap between requests 243system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined 244system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ) 245system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ) 246system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ) 247system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ) 248system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) 249system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ) 250system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ) 251system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ) 252system.physmem_0.averagePower 673.255215 # Core power per rank (mW) 253system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states 254system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states 255system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states 257system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 258system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) 259system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) 260system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ) 261system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 262system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) 263system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ) 264system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ) 265system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ) 266system.physmem_1.averagePower 673.417815 # Core power per rank (mW) 267system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states 268system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states 269system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 270system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states 271system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 272system.cpu.branchPred.lookups 37409115 # Number of BP lookups 273system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted 274system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect 275system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups 276system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits 277system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 278system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage 279system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target. 280system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions. 281system.cpu_clk_domain.clock 500 # Clock period in ticks 282system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 283system.cpu.workload.num_syscalls 444 # Number of system calls 284system.cpu.numCycles 124226112 # number of cpu cycles simulated 285system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 286system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 287system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss 288system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed 289system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered 290system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken 291system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked 292system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing 293system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 294system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps 295system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 296system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR 297system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched 298system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed 299system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle 317system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle 318system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle 319system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked 320system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running 321system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking 322system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing 323system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode 324system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename 331system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full 332system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full 333system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full 334system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full 335system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed 336system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made 337system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups 338system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups 339system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 340system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing 341system.cpu.rename.serializingInsts 478 # count of serializing insts renamed 342system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed 343system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer 344system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit. 345system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit. 346system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads. 347system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores. 348system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ 350system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued 351system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued 352system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling 353system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph 354system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed 355system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle 372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available 403system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued 407system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued 408system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued 409system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued 436system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued 437system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued 441system.cpu.iq.rate 2.479264 # Inst issue rate 442system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested 443system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst) 444system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads 445system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes 446system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses 447system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads 448system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes 449system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses 450system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses 451system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses 452system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores 453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed 455system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed 456system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations 457system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed 458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 459system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 460system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled 461system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked 462system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 463system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing 464system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking 465system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking 466system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ 467system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch 468system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions 469system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions 470system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions 471system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall 472system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall 473system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations 474system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly 475system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly 476system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute 477system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions 478system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed 479system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute 480system.cpu.iew.exec_swp 0 # number of swp insts executed 481system.cpu.iew.exec_nop 0 # number of nop insts executed 482system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed 483system.cpu.iew.exec_branches 31536553 # Number of branches executed 484system.cpu.iew.exec_stores 33820383 # Number of stores executed 485system.cpu.iew.exec_rate 2.470626 # Inst execution rate 486system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit 487system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back 488system.cpu.iew.wb_producers 231581512 # num instructions producing a value 489system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value 490system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 491system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle 492system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back 493system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 494system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit 495system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 496system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted 497system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle 514system.cpu.commit.committedInsts 157988547 # Number of instructions committed 515system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 516system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 517system.cpu.commit.refs 122219137 # Number of memory references committed 518system.cpu.commit.loads 90779385 # Number of loads committed 519system.cpu.commit.membars 0 # Number of memory barriers committed 520system.cpu.commit.branches 29309705 # Number of branches committed 521system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 522system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 523system.cpu.commit.function_calls 4237596 # Number of function calls committed. 524system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 525system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 526system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 527system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 531system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 532system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 533system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 554system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 555system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 559system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached
560system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
561system.cpu.rob.rob_reads 419820689 # The number of ROB reads 562system.cpu.rob.rob_writes 657620446 # The number of ROB writes 563system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself 564system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling 565system.cpu.committedInsts 157988547 # Number of Instructions Simulated 566system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 567system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction 568system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads 569system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle 570system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads 571system.cpu.int_regfile_reads 493661924 # number of integer regfile reads 572system.cpu.int_regfile_writes 240899982 # number of integer regfile writes 573system.cpu.fp_regfile_reads 121 # number of floating regfile reads 574system.cpu.fp_regfile_writes 99 # number of floating regfile writes 575system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads 576system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes 577system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads 578system.cpu.misc_regfile_writes 1 # number of misc regfile writes 579system.cpu.dcache.tags.replacements 2072451 # number of replacements 580system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use 581system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks. 582system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks. 583system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks. 584system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit. 585system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor 586system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy 588system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id 591system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id 592system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 593system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses 594system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses 595system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits 599system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits 600system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits 601system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits 602system.cpu.dcache.overall_hits::total 68431233 # number of overall hits 603system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses 604system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses 605system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses 606system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses 607system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses 608system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses 609system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses 610system.cpu.dcache.overall_misses::total 2779048 # number of overall misses 611system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles 612system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles 615system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles 616system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles 617system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles 618system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles 619system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses 624system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses 625system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses 626system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses 627system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses 628system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses 629system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses 630system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses 631system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses 632system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses 633system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses 634system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses 635system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency 636system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency 638system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency 639system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency 640system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency 643system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked 644system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.dcache.fast_writes 0 # number of fast writes performed 650system.cpu.dcache.cache_copies 0 # number of cache copies performed 651system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks 652system.cpu.dcache.writebacks::total 2066749 # number of writebacks 653system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits 654system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits 655system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 657system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits 658system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits 659system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits 660system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits 661system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses 662system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses 663system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses 664system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses 665system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses 666system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses 667system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses 668system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses 669system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles 670system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles 671system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles 672system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles 673system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles 674system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles 675system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles 676system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles 677system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses 678system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses 679system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses 680system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses 681system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses 682system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses 683system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses 684system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency 686system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency 688system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency 690system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency 693system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 694system.cpu.icache.tags.replacements 58 # number of replacements 695system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use 696system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks. 697system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks. 698system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks. 699system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 700system.cpu.icache.tags.occ_blocks::cpu.inst 832.593358 # Average occupied blocks per requestor 701system.cpu.icache.tags.occ_percent::cpu.inst 0.406540 # Average percentage of cache occupancy 702system.cpu.icache.tags.occ_percent::total 0.406540 # Average percentage of cache occupancy 703system.cpu.icache.tags.occ_task_id_blocks::1024 970 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 707system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id 708system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id 709system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses 710system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses 711system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits 712system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits 713system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits 714system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits 715system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits 716system.cpu.icache.overall_hits::total 27843840 # number of overall hits 717system.cpu.icache.ReadReq_misses::cpu.inst 1337 # number of ReadReq misses 718system.cpu.icache.ReadReq_misses::total 1337 # number of ReadReq misses 719system.cpu.icache.demand_misses::cpu.inst 1337 # number of demand (read+write) misses 720system.cpu.icache.demand_misses::total 1337 # number of demand (read+write) misses 721system.cpu.icache.overall_misses::cpu.inst 1337 # number of overall misses 722system.cpu.icache.overall_misses::total 1337 # number of overall misses 723system.cpu.icache.ReadReq_miss_latency::cpu.inst 100311747 # number of ReadReq miss cycles 724system.cpu.icache.ReadReq_miss_latency::total 100311747 # number of ReadReq miss cycles 725system.cpu.icache.demand_miss_latency::cpu.inst 100311747 # number of demand (read+write) miss cycles 726system.cpu.icache.demand_miss_latency::total 100311747 # number of demand (read+write) miss cycles 727system.cpu.icache.overall_miss_latency::cpu.inst 100311747 # number of overall miss cycles 728system.cpu.icache.overall_miss_latency::total 100311747 # number of overall miss cycles 729system.cpu.icache.ReadReq_accesses::cpu.inst 27845177 # number of ReadReq accesses(hits+misses) 730system.cpu.icache.ReadReq_accesses::total 27845177 # number of ReadReq accesses(hits+misses) 731system.cpu.icache.demand_accesses::cpu.inst 27845177 # number of demand (read+write) accesses 732system.cpu.icache.demand_accesses::total 27845177 # number of demand (read+write) accesses 733system.cpu.icache.overall_accesses::cpu.inst 27845177 # number of overall (read+write) accesses 734system.cpu.icache.overall_accesses::total 27845177 # number of overall (read+write) accesses 735system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 736system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 737system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 738system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 739system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 740system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses 741system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75027.484667 # average ReadReq miss latency 742system.cpu.icache.ReadReq_avg_miss_latency::total 75027.484667 # average ReadReq miss latency 743system.cpu.icache.demand_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency 744system.cpu.icache.demand_avg_miss_latency::total 75027.484667 # average overall miss latency 745system.cpu.icache.overall_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency 746system.cpu.icache.overall_avg_miss_latency::total 75027.484667 # average overall miss latency 747system.cpu.icache.blocked_cycles::no_mshrs 601 # number of cycles access was blocked 748system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 749system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 750system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 751system.cpu.icache.avg_blocked_cycles::no_mshrs 100.166667 # average number of cycles each access was blocked 752system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 753system.cpu.icache.fast_writes 0 # number of fast writes performed 754system.cpu.icache.cache_copies 0 # number of cache copies performed 755system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits 756system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits 757system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits 758system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits 759system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits 760system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits 761system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1028 # number of ReadReq MSHR misses 762system.cpu.icache.ReadReq_mshr_misses::total 1028 # number of ReadReq MSHR misses 763system.cpu.icache.demand_mshr_misses::cpu.inst 1028 # number of demand (read+write) MSHR misses 764system.cpu.icache.demand_mshr_misses::total 1028 # number of demand (read+write) MSHR misses 765system.cpu.icache.overall_mshr_misses::cpu.inst 1028 # number of overall MSHR misses 766system.cpu.icache.overall_mshr_misses::total 1028 # number of overall MSHR misses 767system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79616501 # number of ReadReq MSHR miss cycles 768system.cpu.icache.ReadReq_mshr_miss_latency::total 79616501 # number of ReadReq MSHR miss cycles 769system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79616501 # number of demand (read+write) MSHR miss cycles 770system.cpu.icache.demand_mshr_miss_latency::total 79616501 # number of demand (read+write) MSHR miss cycles 771system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79616501 # number of overall MSHR miss cycles 772system.cpu.icache.overall_mshr_miss_latency::total 79616501 # number of overall MSHR miss cycles 773system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 774system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 775system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 776system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 777system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 778system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 779system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77447.958171 # average ReadReq mshr miss latency 780system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77447.958171 # average ReadReq mshr miss latency 781system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency 782system.cpu.icache.demand_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency 783system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency 784system.cpu.icache.overall_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency 785system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 786system.cpu.l2cache.tags.replacements 480 # number of replacements 787system.cpu.l2cache.tags.tagsinuse 20677.307711 # Cycle average of tags in use 788system.cpu.l2cache.tags.total_refs 4029650 # Total number of references to valid blocks. 789system.cpu.l2cache.tags.sampled_refs 30419 # Sample count of references to valid blocks. 790system.cpu.l2cache.tags.avg_refs 132.471482 # Average number of references to valid blocks. 791system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu.l2cache.tags.occ_blocks::writebacks 19740.626067 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.inst 685.734645 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_blocks::cpu.data 250.946999 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_percent::writebacks 0.602436 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020927 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.data 0.007658 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::total 0.631021 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_task_id_blocks::1024 29939 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id 805system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id 806system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses 807system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses 808system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits 810system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits 811system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits 812system.cpu.l2cache.Writeback_hits::total 2066749 # number of Writeback hits 813system.cpu.l2cache.ReadExReq_hits::cpu.data 53083 # number of ReadExReq hits 814system.cpu.l2cache.ReadExReq_hits::total 53083 # number of ReadExReq hits 815system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits 816system.cpu.l2cache.demand_hits::cpu.data 2047126 # number of demand (read+write) hits 817system.cpu.l2cache.demand_hits::total 2047140 # number of demand (read+write) hits 818system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits 819system.cpu.l2cache.overall_hits::cpu.data 2047126 # number of overall hits 820system.cpu.l2cache.overall_hits::total 2047140 # number of overall hits 821system.cpu.l2cache.ReadReq_misses::cpu.inst 1014 # number of ReadReq misses 822system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses 823system.cpu.l2cache.ReadReq_misses::total 1440 # number of ReadReq misses 824system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses 825system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses 826system.cpu.l2cache.demand_misses::cpu.inst 1014 # number of demand (read+write) misses 827system.cpu.l2cache.demand_misses::cpu.data 29422 # number of demand (read+write) misses 828system.cpu.l2cache.demand_misses::total 30436 # number of demand (read+write) misses 829system.cpu.l2cache.overall_misses::cpu.inst 1014 # number of overall misses 830system.cpu.l2cache.overall_misses::cpu.data 29422 # number of overall misses 831system.cpu.l2cache.overall_misses::total 30436 # number of overall misses 832system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78434000 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32404750 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::total 110838750 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2126346500 # number of ReadExReq miss cycles 836system.cpu.l2cache.ReadExReq_miss_latency::total 2126346500 # number of ReadExReq miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.inst 78434000 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles 839system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles 840system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles 841system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles 842system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles 843system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses) 844system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses) 845system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses) 846system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses) 847system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses) 848system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses) 849system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses) 850system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses 851system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses 852system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses 853system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses 854system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses 855system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses 856system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses 858system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses 859system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses 860system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses 861system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses 862system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses 863system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses 864system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses 865system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses 866system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses 867system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency 868system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency 869system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency 870system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency 871system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency 872system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency 873system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency 874system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency 875system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency 878system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 879system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 882system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 884system.cpu.l2cache.fast_writes 0 # number of fast writes performed 885system.cpu.l2cache.cache_copies 0 # number of cache copies performed 886system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks 887system.cpu.l2cache.writebacks::total 166 # number of writebacks 888system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses 889system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses 890system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses 891system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses 892system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses 893system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses 894system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses 895system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses 896system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses 897system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses 898system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses 899system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles 900system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles 901system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles 902system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles 903system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles 909system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles 910system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses 917system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses 920system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses 921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency 922system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency 923system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency 924system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency 925system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency 932system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 933system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution 938system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes) 944system.cpu.toL2Bus.snoops 0 # Total snoops (count) 945system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram 946system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram 958system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks) 959system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 960system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks) 961system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 962system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks) 963system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) 964system.membus.trans_dist::ReadReq 1440 # Transaction distribution 965system.membus.trans_dist::ReadResp 1439 # Transaction distribution 966system.membus.trans_dist::Writeback 166 # Transaction distribution 967system.membus.trans_dist::ReadExReq 28996 # Transaction distribution 968system.membus.trans_dist::ReadExResp 28996 # Transaction distribution 969system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes) 970system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes) 971system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes) 972system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes) 973system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes) 974system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes) 975system.membus.snoops 0 # Total snoops (count) 976system.membus.snoop_fanout::samples 30602 # Request fanout histogram 977system.membus.snoop_fanout::mean 0 # Request fanout histogram 978system.membus.snoop_fanout::stdev 0 # Request fanout histogram 979system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 980system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram 981system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 982system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 983system.membus.snoop_fanout::min_value 0 # Request fanout histogram 984system.membus.snoop_fanout::max_value 0 # Request fanout histogram 985system.membus.snoop_fanout::total 30602 # Request fanout histogram 986system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks) 987system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 988system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks) 989system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 990 991---------- End Simulation Statistics ----------	560system.cpu.rob.rob_reads 419820689 # The number of ROB reads 561system.cpu.rob.rob_writes 657620446 # The number of ROB writes 562system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling 564system.cpu.committedInsts 157988547 # Number of Instructions Simulated 565system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 566system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads 568system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle 569system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads 570system.cpu.int_regfile_reads 493661924 # number of integer regfile reads 571system.cpu.int_regfile_writes 240899982 # number of integer regfile writes 572system.cpu.fp_regfile_reads 121 # number of floating regfile reads 573system.cpu.fp_regfile_writes 99 # number of floating regfile writes 574system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads 575system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes 576system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads 577system.cpu.misc_regfile_writes 1 # number of misc regfile writes 578system.cpu.dcache.tags.replacements 2072451 # number of replacements 579system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit. 584system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id 591system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 592system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses 593system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses 594system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits 598system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits 599system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits 600system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits 601system.cpu.dcache.overall_hits::total 68431233 # number of overall hits 602system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses 603system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses 604system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses 605system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses 606system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses 607system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses 608system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses 609system.cpu.dcache.overall_misses::total 2779048 # number of overall misses 610system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles 611system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles 612system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles 614system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles 615system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles 616system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles 617system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles 618system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses) 619system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses 623system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses 624system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses 625system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses 626system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses 627system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses 628system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses 629system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses 630system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses 631system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses 632system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses 633system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses 634system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency 635system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency 636system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency 638system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency 639system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency 640system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency 642system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked 643system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked 647system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.dcache.fast_writes 0 # number of fast writes performed 649system.cpu.dcache.cache_copies 0 # number of cache copies performed 650system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks 651system.cpu.dcache.writebacks::total 2066749 # number of writebacks 652system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits 653system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits 654system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 655system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 656system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits 657system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits 658system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits 659system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits 660system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses 661system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses 662system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses 663system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses 664system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses 665system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses 666system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses 667system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses 668system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles 669system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles 670system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles 671system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles 672system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles 673system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles 674system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles 675system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles 676system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses 677system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses 678system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses 679system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses 680system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses 681system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses 682system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses 683system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses 684system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency 692system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 693system.cpu.icache.tags.replacements 58 # number of replacements 694system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use 695system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks. 696system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks. 697system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks. 698system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 699system.cpu.icache.tags.occ_blocks::cpu.inst 832.593358 # Average occupied blocks per requestor 700system.cpu.icache.tags.occ_percent::cpu.inst 0.406540 # Average percentage of cache occupancy 701system.cpu.icache.tags.occ_percent::total 0.406540 # Average percentage of cache occupancy 702system.cpu.icache.tags.occ_task_id_blocks::1024 970 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id 707system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id 708system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses 709system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses 710system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits 711system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits 712system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits 713system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits 714system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits 715system.cpu.icache.overall_hits::total 27843840 # number of overall hits 716system.cpu.icache.ReadReq_misses::cpu.inst 1337 # number of ReadReq misses 717system.cpu.icache.ReadReq_misses::total 1337 # number of ReadReq misses 718system.cpu.icache.demand_misses::cpu.inst 1337 # number of demand (read+write) misses 719system.cpu.icache.demand_misses::total 1337 # number of demand (read+write) misses 720system.cpu.icache.overall_misses::cpu.inst 1337 # number of overall misses 721system.cpu.icache.overall_misses::total 1337 # number of overall misses 722system.cpu.icache.ReadReq_miss_latency::cpu.inst 100311747 # number of ReadReq miss cycles 723system.cpu.icache.ReadReq_miss_latency::total 100311747 # number of ReadReq miss cycles 724system.cpu.icache.demand_miss_latency::cpu.inst 100311747 # number of demand (read+write) miss cycles 725system.cpu.icache.demand_miss_latency::total 100311747 # number of demand (read+write) miss cycles 726system.cpu.icache.overall_miss_latency::cpu.inst 100311747 # number of overall miss cycles 727system.cpu.icache.overall_miss_latency::total 100311747 # number of overall miss cycles 728system.cpu.icache.ReadReq_accesses::cpu.inst 27845177 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.ReadReq_accesses::total 27845177 # number of ReadReq accesses(hits+misses) 730system.cpu.icache.demand_accesses::cpu.inst 27845177 # number of demand (read+write) accesses 731system.cpu.icache.demand_accesses::total 27845177 # number of demand (read+write) accesses 732system.cpu.icache.overall_accesses::cpu.inst 27845177 # number of overall (read+write) accesses 733system.cpu.icache.overall_accesses::total 27845177 # number of overall (read+write) accesses 734system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 736system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 737system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 738system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 739system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75027.484667 # average ReadReq miss latency 741system.cpu.icache.ReadReq_avg_miss_latency::total 75027.484667 # average ReadReq miss latency 742system.cpu.icache.demand_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency 743system.cpu.icache.demand_avg_miss_latency::total 75027.484667 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency 745system.cpu.icache.overall_avg_miss_latency::total 75027.484667 # average overall miss latency 746system.cpu.icache.blocked_cycles::no_mshrs 601 # number of cycles access was blocked 747system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 748system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 749system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 750system.cpu.icache.avg_blocked_cycles::no_mshrs 100.166667 # average number of cycles each access was blocked 751system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 752system.cpu.icache.fast_writes 0 # number of fast writes performed 753system.cpu.icache.cache_copies 0 # number of cache copies performed 754system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits 755system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits 756system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits 757system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits 758system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits 759system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits 760system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1028 # number of ReadReq MSHR misses 761system.cpu.icache.ReadReq_mshr_misses::total 1028 # number of ReadReq MSHR misses 762system.cpu.icache.demand_mshr_misses::cpu.inst 1028 # number of demand (read+write) MSHR misses 763system.cpu.icache.demand_mshr_misses::total 1028 # number of demand (read+write) MSHR misses 764system.cpu.icache.overall_mshr_misses::cpu.inst 1028 # number of overall MSHR misses 765system.cpu.icache.overall_mshr_misses::total 1028 # number of overall MSHR misses 766system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79616501 # number of ReadReq MSHR miss cycles 767system.cpu.icache.ReadReq_mshr_miss_latency::total 79616501 # number of ReadReq MSHR miss cycles 768system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79616501 # number of demand (read+write) MSHR miss cycles 769system.cpu.icache.demand_mshr_miss_latency::total 79616501 # number of demand (read+write) MSHR miss cycles 770system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79616501 # number of overall MSHR miss cycles 771system.cpu.icache.overall_mshr_miss_latency::total 79616501 # number of overall MSHR miss cycles 772system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 773system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 774system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 775system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 776system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 777system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 778system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77447.958171 # average ReadReq mshr miss latency 779system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77447.958171 # average ReadReq mshr miss latency 780system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency 781system.cpu.icache.demand_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency 782system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency 783system.cpu.icache.overall_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency 784system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cpu.l2cache.tags.replacements 480 # number of replacements 786system.cpu.l2cache.tags.tagsinuse 20677.307711 # Cycle average of tags in use 787system.cpu.l2cache.tags.total_refs 4029650 # Total number of references to valid blocks. 788system.cpu.l2cache.tags.sampled_refs 30419 # Sample count of references to valid blocks. 789system.cpu.l2cache.tags.avg_refs 132.471482 # Average number of references to valid blocks. 790system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 791system.cpu.l2cache.tags.occ_blocks::writebacks 19740.626067 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 685.734645 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.data 250.946999 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_percent::writebacks 0.602436 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020927 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::cpu.data 0.007658 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::total 0.631021 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_task_id_blocks::1024 29939 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id 804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id 805system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses 806system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses 807system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits 808system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits 810system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits 811system.cpu.l2cache.Writeback_hits::total 2066749 # number of Writeback hits 812system.cpu.l2cache.ReadExReq_hits::cpu.data 53083 # number of ReadExReq hits 813system.cpu.l2cache.ReadExReq_hits::total 53083 # number of ReadExReq hits 814system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits 815system.cpu.l2cache.demand_hits::cpu.data 2047126 # number of demand (read+write) hits 816system.cpu.l2cache.demand_hits::total 2047140 # number of demand (read+write) hits 817system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits 818system.cpu.l2cache.overall_hits::cpu.data 2047126 # number of overall hits 819system.cpu.l2cache.overall_hits::total 2047140 # number of overall hits 820system.cpu.l2cache.ReadReq_misses::cpu.inst 1014 # number of ReadReq misses 821system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses 822system.cpu.l2cache.ReadReq_misses::total 1440 # number of ReadReq misses 823system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses 824system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses 825system.cpu.l2cache.demand_misses::cpu.inst 1014 # number of demand (read+write) misses 826system.cpu.l2cache.demand_misses::cpu.data 29422 # number of demand (read+write) misses 827system.cpu.l2cache.demand_misses::total 30436 # number of demand (read+write) misses 828system.cpu.l2cache.overall_misses::cpu.inst 1014 # number of overall misses 829system.cpu.l2cache.overall_misses::cpu.data 29422 # number of overall misses 830system.cpu.l2cache.overall_misses::total 30436 # number of overall misses 831system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78434000 # number of ReadReq miss cycles 832system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32404750 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadReq_miss_latency::total 110838750 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2126346500 # number of ReadExReq miss cycles 835system.cpu.l2cache.ReadExReq_miss_latency::total 2126346500 # number of ReadExReq miss cycles 836system.cpu.l2cache.demand_miss_latency::cpu.inst 78434000 # number of demand (read+write) miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles 839system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles 840system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles 841system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles 842system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses) 843system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses) 844system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses) 845system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses) 846system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses) 847system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses) 848system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses) 849system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses 850system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses 851system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses 852system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses 853system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses 854system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses 855system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses 858system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses 859system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses 860system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses 861system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses 862system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses 863system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses 864system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses 865system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses 866system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency 867system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency 868system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency 869system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency 870system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency 871system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency 872system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency 873system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency 874system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency 875system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency 877system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 878system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 879system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 881system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 882system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 883system.cpu.l2cache.fast_writes 0 # number of fast writes performed 884system.cpu.l2cache.cache_copies 0 # number of cache copies performed 885system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks 886system.cpu.l2cache.writebacks::total 166 # number of writebacks 887system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses 888system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses 889system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses 890system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses 891system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses 892system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses 893system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses 894system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses 895system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses 896system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses 897system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses 898system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles 899system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles 900system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles 901system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles 902system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles 909system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses 910system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses 920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency 921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency 922system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency 923system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency 924system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency 931system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 932system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution 937system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.snoops 0 # Total snoops (count) 944system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram 945system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 946system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram 957system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks) 958system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 959system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks) 960system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 961system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks) 962system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) 963system.membus.trans_dist::ReadReq 1440 # Transaction distribution 964system.membus.trans_dist::ReadResp 1439 # Transaction distribution 965system.membus.trans_dist::Writeback 166 # Transaction distribution 966system.membus.trans_dist::ReadExReq 28996 # Transaction distribution 967system.membus.trans_dist::ReadExResp 28996 # Transaction distribution 968system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes) 969system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes) 970system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes) 971system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes) 972system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes) 973system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes) 974system.membus.snoops 0 # Total snoops (count) 975system.membus.snoop_fanout::samples 30602 # Request fanout histogram 976system.membus.snoop_fanout::mean 0 # Request fanout histogram 977system.membus.snoop_fanout::stdev 0 # Request fanout histogram 978system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 979system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram 980system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 981system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 982system.membus.snoop_fanout::min_value 0 # Request fanout histogram 983system.membus.snoop_fanout::max_value 0 # Request fanout histogram 984system.membus.snoop_fanout::total 30602 # Request fanout histogram 985system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks) 986system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 987system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks) 988system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 989 990---------- End Simulation Statistics ----------