Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10352:5f1f92bf76ee ) new ( 10409:8c80b91944c5 )

full compact

stats.txt (10352:5f1f92bf76ee)	stats.txt (10409:8c80b91944c5)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061857 # Number of seconds simulated 4sim_ticks 61857343500 # Number of ticks simulated 5final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061857 # Number of seconds simulated 4sim_ticks 61857343500 # Number of ticks simulated 5final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 85967 # Simulator instruction rate (inst/s) 8host_op_rate 151374 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33658728 # Simulator tick rate (ticks/s) 10host_mem_usage 393056 # Number of bytes of host memory used 11host_seconds 1837.78 # Real time elapsed on the host	7host_inst_rate 115241 # Simulator instruction rate (inst/s) 8host_op_rate 202921 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45120347 # Simulator tick rate (ticks/s) 10host_mem_usage 449832 # Number of bytes of host memory used 11host_seconds 1370.94 # Real time elapsed on the host
12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory 22system.physmem.bytes_written::total 12608 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 197 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30463 # Number of read requests accepted 40system.physmem.writeReqs 197 # Number of write requests accepted 41system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue 45system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1927 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2067 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2027 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1932 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2026 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1903 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1964 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1863 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1937 # Per bank write bursts 60system.physmem.perBankRdBursts::9 1937 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1804 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1796 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 67system.physmem.perBankWrBursts::0 15 # Per bank write bursts 68system.physmem.perBankWrBursts::1 94 # Per bank write bursts 69system.physmem.perBankWrBursts::2 13 # Per bank write bursts 70system.physmem.perBankWrBursts::3 21 # Per bank write bursts 71system.physmem.perBankWrBursts::4 7 # Per bank write bursts 72system.physmem.perBankWrBursts::5 7 # Per bank write bursts 73system.physmem.perBankWrBursts::6 12 # Per bank write bursts 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5 # Per bank write bursts 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 61857329000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 30463 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 197 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads	12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory 22system.physmem.bytes_written::total 12608 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 197 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30463 # Number of read requests accepted 40system.physmem.writeReqs 197 # Number of write requests accepted 41system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue 45system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1927 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2067 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2027 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1932 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2026 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1903 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1964 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1863 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1937 # Per bank write bursts 60system.physmem.perBankRdBursts::9 1937 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1804 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1796 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1818 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 67system.physmem.perBankWrBursts::0 15 # Per bank write bursts 68system.physmem.perBankWrBursts::1 94 # Per bank write bursts 69system.physmem.perBankWrBursts::2 13 # Per bank write bursts 70system.physmem.perBankWrBursts::3 21 # Per bank write bursts 71system.physmem.perBankWrBursts::4 7 # Per bank write bursts 72system.physmem.perBankWrBursts::5 7 # Per bank write bursts 73system.physmem.perBankWrBursts::6 12 # Per bank write bursts 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5 # Per bank write bursts 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 61857329000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 30463 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 197 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads
225system.physmem.totQLat 130872750 # Total ticks spent queuing 226system.physmem.totMemAccLat 700329000 # Total ticks spent from burst creation until serviced by the DRAM	225system.physmem.totQLat 131010750 # Total ticks spent queuing 226system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM
227system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers	227system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers
228system.physmem.avgQLat 4309.14 # Average queueing delay per DRAM burst	228system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst
229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst	229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
230system.physmem.avgMemAccLat 23059.14 # Average memory access latency per DRAM burst	230system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst
231system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.25 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing 241system.physmem.readRowHits 27696 # Number of row buffer hits during reads 242system.physmem.writeRowHits 119 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes 245system.physmem.avgGap 2017525.41 # Average gap between requests 246system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined 247system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states 248system.physmem.memoryStateTime::REF 2065440000 # Time in different power states 249system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states 251system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states	231system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.25 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing 241system.physmem.readRowHits 27696 # Number of row buffer hits during reads 242system.physmem.writeRowHits 119 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes 245system.physmem.avgGap 2017525.41 # Average gap between requests 246system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined 247system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states 248system.physmem.memoryStateTime::REF 2065440000 # Time in different power states 249system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states 251system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
252system.membus.throughput 31718918 # Throughput (bytes/s)
253system.membus.trans_dist::ReadReq 1465 # Transaction distribution 254system.membus.trans_dist::ReadResp 1462 # Transaction distribution 255system.membus.trans_dist::Writeback 197 # Transaction distribution 256system.membus.trans_dist::ReadExReq 28998 # Transaction distribution 257system.membus.trans_dist::ReadExResp 28998 # Transaction distribution 258system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) 259system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) 260system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes)	252system.membus.trans_dist::ReadReq 1465 # Transaction distribution 253system.membus.trans_dist::ReadResp 1462 # Transaction distribution 254system.membus.trans_dist::Writeback 197 # Transaction distribution 255system.membus.trans_dist::ReadExReq 28998 # Transaction distribution 256system.membus.trans_dist::ReadExResp 28998 # Transaction distribution 257system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) 258system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) 259system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes)
261system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) 262system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) 263system.membus.tot_pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) 264system.membus.data_through_bus 1962048 # Total data (bytes) 265system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)	260system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) 261system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) 262system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) 263system.membus.snoops 0 # Total snoops (count) 264system.membus.snoop_fanout::samples 30660 # Request fanout histogram 265system.membus.snoop_fanout::mean 0 # Request fanout histogram 266system.membus.snoop_fanout::stdev 0 # Request fanout histogram 267system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 268system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram 269system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 270system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 271system.membus.snoop_fanout::min_value 0 # Request fanout histogram 272system.membus.snoop_fanout::max_value 0 # Request fanout histogram 273system.membus.snoop_fanout::total 30660 # Request fanout histogram
266system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) 267system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 268system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) 269system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 270system.cpu_clk_domain.clock 500 # Clock period in ticks 271system.cpu.branchPred.lookups 37414357 # Number of BP lookups 272system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted 273system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect 274system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups 275system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits 276system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 277system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage 278system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. 279system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 281system.cpu.workload.num_syscalls 444 # Number of system calls 282system.cpu.numCycles 123714688 # number of cpu cycles simulated 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 1664994 # Number of cycles fetch has spent squashing 291system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 292system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps 293system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions 294system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR 295system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched 296system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed 297system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle 315system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle 316system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle 317system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked 318system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running 319system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking 320system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing 321system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode 322system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing 323system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle 324system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking 325system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst 326system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running 327system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking 328system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename 329system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full 330system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full 331system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full 332system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full 333system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed 334system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made 335system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups 336system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups 337system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 338system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing 339system.cpu.rename.serializingInsts 475 # count of serializing insts renamed 340system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed 341system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer 342system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit. 343system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit. 344system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads. 345system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores. 346system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec) 347system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ 348system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued 349system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued 350system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling 351system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph 352system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed 353system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle 370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 371system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued 405system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued 406system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued 407system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued 434system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued 435system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued 436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued 439system.cpu.iq.rate 2.489411 # Inst issue rate 440system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested 441system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) 442system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads 443system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes 444system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses 445system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads 446system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes 447system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses 448system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses 449system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses 450system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores 451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 452system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed 453system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed 454system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations 455system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed 456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 458system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled 459system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked 460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 461system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing 462system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking 463system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking 464system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ 465system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch 466system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions 467system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions 468system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions 469system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall 470system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall 471system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations 472system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly 473system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly 474system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute 475system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions 476system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed 477system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute 478system.cpu.iew.exec_swp 0 # number of swp insts executed 479system.cpu.iew.exec_nop 0 # number of nop insts executed 480system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed 481system.cpu.iew.exec_branches 31536734 # Number of branches executed 482system.cpu.iew.exec_stores 33824606 # Number of stores executed 483system.cpu.iew.exec_rate 2.480687 # Inst execution rate 484system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit 485system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back 486system.cpu.iew.wb_producers 231632885 # num instructions producing a value 487system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value 488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 489system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle 490system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back 491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 492system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit 493system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 494system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 117208009 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::0 52857681 45.10% 45.10% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::total 117208009 # Number of insts commited each cycle 512system.cpu.commit.committedInsts 157988547 # Number of instructions committed 513system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 515system.cpu.commit.refs 122219137 # Number of memory references committed 516system.cpu.commit.loads 90779385 # Number of loads committed 517system.cpu.commit.membars 0 # Number of memory barriers committed 518system.cpu.commit.branches 29309705 # Number of branches committed 519system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 520system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 521system.cpu.commit.function_calls 4237596 # Number of function calls committed. 522system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 523system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 524system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 525system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 526system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 527system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 531system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 557system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached 558system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 559system.cpu.rob.rob_reads 419324214 # The number of ROB reads 560system.cpu.rob.rob_writes 657627212 # The number of ROB writes 561system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself 562system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling 563system.cpu.committedInsts 157988547 # Number of Instructions Simulated 564system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 565system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads 567system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads 569system.cpu.int_regfile_reads 493625450 # number of integer regfile reads 570system.cpu.int_regfile_writes 240898259 # number of integer regfile writes 571system.cpu.fp_regfile_reads 178 # number of floating regfile reads 572system.cpu.fp_regfile_writes 135 # number of floating regfile writes 573system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads 574system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes 575system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads 576system.cpu.misc_regfile_writes 1 # number of misc regfile writes	274system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) 275system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 276system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) 277system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.branchPred.lookups 37414357 # Number of BP lookups 280system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted 281system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect 282system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups 283system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits 284system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 285system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage 286system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. 287system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. 288system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 289system.cpu.workload.num_syscalls 444 # Number of system calls 290system.cpu.numCycles 123714688 # number of cpu cycles simulated 291system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 292system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 293system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss 294system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed 295system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered 296system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken 297system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked 298system.cpu.fetch.SquashCycles 1664994 # Number of cycles fetch has spent squashing 299system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 300system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps 301system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions 302system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR 303system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched 304system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed 305system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle 323system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle 324system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle 325system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked 326system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running 327system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking 328system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing 329system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode 330system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing 331system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle 332system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking 333system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst 334system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running 335system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking 336system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename 337system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full 338system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full 339system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full 340system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full 341system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed 342system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made 343system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups 344system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups 345system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 346system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing 347system.cpu.rename.serializingInsts 475 # count of serializing insts renamed 348system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed 349system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer 350system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit. 351system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit. 352system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads. 353system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores. 354system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec) 355system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ 356system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued 357system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued 358system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling 359system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph 360system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed 361system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle 378system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available 381system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available 387system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available 409system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued 413system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued 414system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued 415system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued 442system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued 443system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 445system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 446system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued 447system.cpu.iq.rate 2.489411 # Inst issue rate 448system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested 449system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) 450system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads 451system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes 452system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses 453system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads 454system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes 455system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses 456system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses 457system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses 458system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores 459system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 460system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed 461system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed 462system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations 463system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed 464system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 465system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 466system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled 467system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked 468system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 469system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing 470system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking 471system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking 472system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ 473system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch 474system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions 475system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions 476system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions 477system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall 478system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall 479system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations 480system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly 481system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly 482system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute 483system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions 484system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed 485system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute 486system.cpu.iew.exec_swp 0 # number of swp insts executed 487system.cpu.iew.exec_nop 0 # number of nop insts executed 488system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed 489system.cpu.iew.exec_branches 31536734 # Number of branches executed 490system.cpu.iew.exec_stores 33824606 # Number of stores executed 491system.cpu.iew.exec_rate 2.480687 # Inst execution rate 492system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit 493system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back 494system.cpu.iew.wb_producers 231632885 # num instructions producing a value 495system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value 496system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 497system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle 498system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back 499system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 500system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit 501system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 502system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted 503system.cpu.commit.committed_per_cycle::samples 117208009 # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::0 52857681 45.10% 45.10% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::total 117208009 # Number of insts commited each cycle 520system.cpu.commit.committedInsts 157988547 # Number of instructions committed 521system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 522system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 523system.cpu.commit.refs 122219137 # Number of memory references committed 524system.cpu.commit.loads 90779385 # Number of loads committed 525system.cpu.commit.membars 0 # Number of memory barriers committed 526system.cpu.commit.branches 29309705 # Number of branches committed 527system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 528system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 529system.cpu.commit.function_calls 4237596 # Number of function calls committed. 530system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 531system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 532system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 533system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 534system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 535system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 536system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 537system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 538system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 539system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 560system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 561system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 562system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 563system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 564system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 565system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached 566system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 567system.cpu.rob.rob_reads 419324214 # The number of ROB reads 568system.cpu.rob.rob_writes 657627212 # The number of ROB writes 569system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself 570system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling 571system.cpu.committedInsts 157988547 # Number of Instructions Simulated 572system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 573system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction 574system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads 575system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle 576system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads 577system.cpu.int_regfile_reads 493625450 # number of integer regfile reads 578system.cpu.int_regfile_writes 240898259 # number of integer regfile writes 579system.cpu.fp_regfile_reads 178 # number of floating regfile reads 580system.cpu.fp_regfile_writes 135 # number of floating regfile writes 581system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads 582system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes 583system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads 584system.cpu.misc_regfile_writes 1 # number of misc regfile writes
577system.cpu.toL2Bus.throughput 4287758914 # Throughput (bytes/s)
578system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution 580system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution 583system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) 584system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) 585system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes)	585system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution 588system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution 590system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes)
586system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) 587system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) 588system.cpu.toL2Bus.tot_pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) 589system.cpu.toL2Bus.data_through_bus 265229376 # Total data (bytes) 590system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)	593system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) 595system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) 596system.cpu.toL2Bus.snoops 0 # Total snoops (count) 597system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 600system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram
591system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) 592system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 593system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) 594system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 595system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks) 596system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) 597system.cpu.icache.tags.replacements 62 # number of replacements 598system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use 599system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. 600system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. 601system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. 602system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 603system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor 604system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy 605system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy 606system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id 607system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 608system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 609system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id 611system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id 612system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses 613system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses 614system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits 615system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits 616system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits 617system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits 618system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits 619system.cpu.icache.overall_hits::total 27848273 # number of overall hits 620system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses 621system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses 622system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses 623system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses 624system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses 625system.cpu.icache.overall_misses::total 1347 # number of overall misses 626system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles 627system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles 628system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles 629system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles 630system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles 631system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles 632system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) 633system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) 634system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses 635system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses 636system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses 637system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses 638system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 640system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 641system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 642system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 643system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency 645system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency 646system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency 647system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency 648system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency 649system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency 650system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked 651system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 653system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked 655system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.icache.fast_writes 0 # number of fast writes performed 657system.cpu.icache.cache_copies 0 # number of cache copies performed 658system.cpu.icache.ReadReq_mshr_hits::cpu.inst 321 # number of ReadReq MSHR hits 659system.cpu.icache.ReadReq_mshr_hits::total 321 # number of ReadReq MSHR hits 660system.cpu.icache.demand_mshr_hits::cpu.inst 321 # number of demand (read+write) MSHR hits 661system.cpu.icache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits 662system.cpu.icache.overall_mshr_hits::cpu.inst 321 # number of overall MSHR hits 663system.cpu.icache.overall_mshr_hits::total 321 # number of overall MSHR hits 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 1026 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72336999 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 72336999 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72336999 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 72336999 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72336999 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 72336999 # number of overall MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency 688system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 689system.cpu.l2cache.tags.replacements 515 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 20693.420536 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020813 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.007602 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.631513 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 29929 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 784 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1397 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27627 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913361 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 33266205 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 33266205 # Number of data accesses 711system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 712system.cpu.l2cache.ReadReq_hits::cpu.data 1994012 # number of ReadReq hits 713system.cpu.l2cache.ReadReq_hits::total 1994028 # number of ReadReq hits 714system.cpu.l2cache.Writeback_hits::writebacks 2066654 # number of Writeback hits 715system.cpu.l2cache.Writeback_hits::total 2066654 # number of Writeback hits 716system.cpu.l2cache.ReadExReq_hits::cpu.data 53067 # number of ReadExReq hits 717system.cpu.l2cache.ReadExReq_hits::total 53067 # number of ReadExReq hits 718system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 719system.cpu.l2cache.demand_hits::cpu.data 2047079 # number of demand (read+write) hits 720system.cpu.l2cache.demand_hits::total 2047095 # number of demand (read+write) hits 721system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 722system.cpu.l2cache.overall_hits::cpu.data 2047079 # number of overall hits 723system.cpu.l2cache.overall_hits::total 2047095 # number of overall hits 724system.cpu.l2cache.ReadReq_misses::cpu.inst 1010 # number of ReadReq misses 725system.cpu.l2cache.ReadReq_misses::cpu.data 455 # number of ReadReq misses 726system.cpu.l2cache.ReadReq_misses::total 1465 # number of ReadReq misses 727system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses 728system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses 729system.cpu.l2cache.demand_misses::cpu.inst 1010 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::cpu.data 29453 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::total 30463 # number of demand (read+write) misses 732system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses 733system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses 734system.cpu.l2cache.overall_misses::total 30463 # number of overall misses 735system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71141750 # number of ReadReq miss cycles 736system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31680000 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::total 102821750 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914500 # number of ReadExReq miss cycles 739system.cpu.l2cache.ReadExReq_miss_latency::total 1901914500 # number of ReadExReq miss cycles 740system.cpu.l2cache.demand_miss_latency::cpu.inst 71141750 # number of demand (read+write) miss cycles 741system.cpu.l2cache.demand_miss_latency::cpu.data 1933594500 # number of demand (read+write) miss cycles 742system.cpu.l2cache.demand_miss_latency::total 2004736250 # number of demand (read+write) miss cycles 743system.cpu.l2cache.overall_miss_latency::cpu.inst 71141750 # number of overall miss cycles 744system.cpu.l2cache.overall_miss_latency::cpu.data 1933594500 # number of overall miss cycles 745system.cpu.l2cache.overall_miss_latency::total 2004736250 # number of overall miss cycles 746system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses) 747system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses) 748system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses) 749system.cpu.l2cache.Writeback_accesses::writebacks 2066654 # number of Writeback accesses(hits+misses) 750system.cpu.l2cache.Writeback_accesses::total 2066654 # number of Writeback accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::cpu.data 82065 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.ReadExReq_accesses::total 82065 # number of ReadExReq accesses(hits+misses) 753system.cpu.l2cache.demand_accesses::cpu.inst 1026 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::cpu.data 2076532 # number of demand (read+write) accesses 755system.cpu.l2cache.demand_accesses::total 2077558 # number of demand (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.inst 1026 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::cpu.data 2076532 # number of overall (read+write) accesses 758system.cpu.l2cache.overall_accesses::total 2077558 # number of overall (read+write) accesses 759system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984405 # miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000228 # miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_miss_rate::total 0.000734 # miss rate for ReadReq accesses 762system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353354 # miss rate for ReadExReq accesses 763system.cpu.l2cache.ReadExReq_miss_rate::total 0.353354 # miss rate for ReadExReq accesses 764system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984405 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::cpu.data 0.014184 # miss rate for demand accesses 766system.cpu.l2cache.demand_miss_rate::total 0.014663 # miss rate for demand accesses 767system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses 769system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses 770system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238 # average ReadReq miss latency 771system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626 # average ReadReq miss latency 772system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881 # average ReadReq miss latency 773system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916 # average ReadExReq miss latency 774system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916 # average ReadExReq miss latency 775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114 # average overall miss latency 781system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu.l2cache.fast_writes 0 # number of fast writes performed 788system.cpu.l2cache.cache_copies 0 # number of cache copies performed 789system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks 790system.cpu.l2cache.writebacks::total 197 # number of writebacks 791system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses 792system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses 793system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses 795system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses 796system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses 797system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses 798system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses 799system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses 800system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses 801system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses 802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles 803system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles 804system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles 805system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles 810system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles 812system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles 813system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses 814system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses 815system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses 816system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses 818system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses 819system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses 820system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses 821system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses 822system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses 823system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses 824system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency 825system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency 826system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency 827system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency 828system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency 829system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency 830system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency 831system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency 832system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency 833system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency 834system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency 835system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 836system.cpu.dcache.tags.replacements 2072433 # number of replacements 837system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use 838system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks. 839system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. 840system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks. 841system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. 842system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor 843system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy 844system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy 845system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 846system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id 847system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id 848system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 849system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 850system.cpu.dcache.tags.tag_accesses 144502463 # Number of tag accesses 851system.cpu.dcache.tags.data_accesses 144502463 # Number of data accesses 852system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits 853system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits 854system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits 855system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits 856system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits 857system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits 858system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits 859system.cpu.dcache.overall_hits::total 68459744 # number of overall hits 860system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses 861system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses 862system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses 863system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses 864system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses 865system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses 866system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses 867system.cpu.dcache.overall_misses::total 2753223 # number of overall misses 868system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles 869system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles 870system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles 871system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles 872system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles 873system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles 874system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles 875system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles 876system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses) 877system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses) 878system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 879system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 880system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses 881system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses 882system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses 883system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses 884system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses 885system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses 886system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses 887system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses 888system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses 889system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses 890system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses 891system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses 892system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency 893system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency 894system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency 895system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency 896system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency 897system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency 898system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency 899system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency 900system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked 901system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked 903system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked 905system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.dcache.fast_writes 0 # number of fast writes performed 907system.cpu.dcache.cache_copies 0 # number of cache copies performed 908system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks 909system.cpu.dcache.writebacks::total 2066654 # number of writebacks 910system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits 911system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits 912system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits 913system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits 914system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits 915system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits 916system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits 917system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits 918system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses 919system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses 920system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses 921system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses 922system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses 923system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses 924system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses 925system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses 926system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles 927system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles 928system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles 929system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles 930system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles 931system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles 932system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles 933system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles 934system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses 935system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses 936system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses 937system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses 938system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses 939system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses 940system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses 941system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses 942system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency 943system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency 944system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency 945system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency 946system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency 947system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency 948system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency 949system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency 950system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 951 952---------- End Simulation Statistics ----------	610system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) 611system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) 612system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) 613system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 614system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks) 615system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) 616system.cpu.icache.tags.replacements 62 # number of replacements 617system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use 618system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. 619system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. 620system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. 621system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 622system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor 623system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy 624system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy 625system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 627system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 628system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 629system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id 630system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id 631system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses 632system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses 633system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits 634system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits 635system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits 636system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits 637system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits 638system.cpu.icache.overall_hits::total 27848273 # number of overall hits 639system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses 640system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses 641system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses 642system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses 643system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses 644system.cpu.icache.overall_misses::total 1347 # number of overall misses 645system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles 646system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles 647system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles 648system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles 649system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles 650system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles 651system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) 652system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) 653system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses 654system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses 655system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses 656system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses 657system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 658system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 659system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 660system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 661system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 662system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses 663system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency 664system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency 665system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency 666system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency 667system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency 668system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency 669system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked 670system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 672system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked 674system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.icache.fast_writes 0 # number of fast writes performed 676system.cpu.icache.cache_copies 0 # number of cache copies performed 677system.cpu.icache.ReadReq_mshr_hits::cpu.inst 321 # number of ReadReq MSHR hits 678system.cpu.icache.ReadReq_mshr_hits::total 321 # number of ReadReq MSHR hits 679system.cpu.icache.demand_mshr_hits::cpu.inst 321 # number of demand (read+write) MSHR hits 680system.cpu.icache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits 681system.cpu.icache.overall_mshr_hits::cpu.inst 321 # number of overall MSHR hits 682system.cpu.icache.overall_mshr_hits::total 321 # number of overall MSHR hits 683system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026 # number of ReadReq MSHR misses 684system.cpu.icache.ReadReq_mshr_misses::total 1026 # number of ReadReq MSHR misses 685system.cpu.icache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses 686system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses 687system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses 688system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses 689system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72336999 # number of ReadReq MSHR miss cycles 690system.cpu.icache.ReadReq_mshr_miss_latency::total 72336999 # number of ReadReq MSHR miss cycles 691system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72336999 # number of demand (read+write) MSHR miss cycles 692system.cpu.icache.demand_mshr_miss_latency::total 72336999 # number of demand (read+write) MSHR miss cycles 693system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72336999 # number of overall MSHR miss cycles 694system.cpu.icache.overall_mshr_miss_latency::total 72336999 # number of overall MSHR miss cycles 695system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 696system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 697system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 698system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 699system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 700system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 701system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661 # average ReadReq mshr miss latency 702system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661 # average ReadReq mshr miss latency 703system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency 704system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency 705system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency 706system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency 707system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 708system.cpu.l2cache.tags.replacements 515 # number of replacements 709system.cpu.l2cache.tags.tagsinuse 20693.420536 # Cycle average of tags in use 710system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. 711system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. 712system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. 713system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 714system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871 # Average occupied blocks per requestor 715system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor 716system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy 718system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020813 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.data 0.007602 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::total 0.631513 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_task_id_blocks::1024 29929 # Occupied blocks per task id 722system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 723system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 724system.cpu.l2cache.tags.age_task_id_blocks_1024::2 784 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1397 # Occupied blocks per task id 726system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27627 # Occupied blocks per task id 727system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913361 # Percentage of cache occupancy per task id 728system.cpu.l2cache.tags.tag_accesses 33266205 # Number of tag accesses 729system.cpu.l2cache.tags.data_accesses 33266205 # Number of data accesses 730system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 731system.cpu.l2cache.ReadReq_hits::cpu.data 1994012 # number of ReadReq hits 732system.cpu.l2cache.ReadReq_hits::total 1994028 # number of ReadReq hits 733system.cpu.l2cache.Writeback_hits::writebacks 2066654 # number of Writeback hits 734system.cpu.l2cache.Writeback_hits::total 2066654 # number of Writeback hits 735system.cpu.l2cache.ReadExReq_hits::cpu.data 53067 # number of ReadExReq hits 736system.cpu.l2cache.ReadExReq_hits::total 53067 # number of ReadExReq hits 737system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 738system.cpu.l2cache.demand_hits::cpu.data 2047079 # number of demand (read+write) hits 739system.cpu.l2cache.demand_hits::total 2047095 # number of demand (read+write) hits 740system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 741system.cpu.l2cache.overall_hits::cpu.data 2047079 # number of overall hits 742system.cpu.l2cache.overall_hits::total 2047095 # number of overall hits 743system.cpu.l2cache.ReadReq_misses::cpu.inst 1010 # number of ReadReq misses 744system.cpu.l2cache.ReadReq_misses::cpu.data 455 # number of ReadReq misses 745system.cpu.l2cache.ReadReq_misses::total 1465 # number of ReadReq misses 746system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses 747system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses 748system.cpu.l2cache.demand_misses::cpu.inst 1010 # number of demand (read+write) misses 749system.cpu.l2cache.demand_misses::cpu.data 29453 # number of demand (read+write) misses 750system.cpu.l2cache.demand_misses::total 30463 # number of demand (read+write) misses 751system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses 752system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses 753system.cpu.l2cache.overall_misses::total 30463 # number of overall misses 754system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71141750 # number of ReadReq miss cycles 755system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31680000 # number of ReadReq miss cycles 756system.cpu.l2cache.ReadReq_miss_latency::total 102821750 # number of ReadReq miss cycles 757system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914500 # number of ReadExReq miss cycles 758system.cpu.l2cache.ReadExReq_miss_latency::total 1901914500 # number of ReadExReq miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.inst 71141750 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.data 1933594500 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::total 2004736250 # number of demand (read+write) miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.inst 71141750 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.data 1933594500 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::total 2004736250 # number of overall miss cycles 765system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses) 767system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses) 768system.cpu.l2cache.Writeback_accesses::writebacks 2066654 # number of Writeback accesses(hits+misses) 769system.cpu.l2cache.Writeback_accesses::total 2066654 # number of Writeback accesses(hits+misses) 770system.cpu.l2cache.ReadExReq_accesses::cpu.data 82065 # number of ReadExReq accesses(hits+misses) 771system.cpu.l2cache.ReadExReq_accesses::total 82065 # number of ReadExReq accesses(hits+misses) 772system.cpu.l2cache.demand_accesses::cpu.inst 1026 # number of demand (read+write) accesses 773system.cpu.l2cache.demand_accesses::cpu.data 2076532 # number of demand (read+write) accesses 774system.cpu.l2cache.demand_accesses::total 2077558 # number of demand (read+write) accesses 775system.cpu.l2cache.overall_accesses::cpu.inst 1026 # number of overall (read+write) accesses 776system.cpu.l2cache.overall_accesses::cpu.data 2076532 # number of overall (read+write) accesses 777system.cpu.l2cache.overall_accesses::total 2077558 # number of overall (read+write) accesses 778system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984405 # miss rate for ReadReq accesses 779system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000228 # miss rate for ReadReq accesses 780system.cpu.l2cache.ReadReq_miss_rate::total 0.000734 # miss rate for ReadReq accesses 781system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353354 # miss rate for ReadExReq accesses 782system.cpu.l2cache.ReadExReq_miss_rate::total 0.353354 # miss rate for ReadExReq accesses 783system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984405 # miss rate for demand accesses 784system.cpu.l2cache.demand_miss_rate::cpu.data 0.014184 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::total 0.014663 # miss rate for demand accesses 786system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses 789system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238 # average ReadReq miss latency 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881 # average ReadReq miss latency 792system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916 # average ReadExReq miss latency 793system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916 # average ReadExReq miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency 796system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114 # average overall miss latency 800system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 806system.cpu.l2cache.fast_writes 0 # number of fast writes performed 807system.cpu.l2cache.cache_copies 0 # number of cache copies performed 808system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks 809system.cpu.l2cache.writebacks::total 197 # number of writebacks 810system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses 811system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses 812system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses 813system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses 814system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses 815system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses 817system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses 818system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses 819system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses 820system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses 821system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles 822system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles 823system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles 824system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles 825system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles 826system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles 827system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles 828system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles 829system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles 830system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles 831system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles 832system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses 833system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses 834system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses 835system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses 836system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses 837system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses 838system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses 839system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses 840system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses 841system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses 842system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses 843system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency 844system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency 845system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency 846system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency 847system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency 849system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency 850system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency 852system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency 853system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency 854system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu.dcache.tags.replacements 2072433 # number of replacements 856system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use 857system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks. 858system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. 859system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks. 860system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. 861system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor 862system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy 863system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy 864system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 865system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id 866system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id 867system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 868system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 869system.cpu.dcache.tags.tag_accesses 144502463 # Number of tag accesses 870system.cpu.dcache.tags.data_accesses 144502463 # Number of data accesses 871system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits 872system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits 873system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits 874system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits 875system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits 876system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits 877system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits 878system.cpu.dcache.overall_hits::total 68459744 # number of overall hits 879system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses 880system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses 881system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses 882system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses 883system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses 884system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses 885system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses 886system.cpu.dcache.overall_misses::total 2753223 # number of overall misses 887system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles 888system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles 889system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles 890system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles 891system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles 892system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles 893system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles 894system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles 895system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses) 896system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses) 897system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 898system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 899system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses 900system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses 901system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses 902system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses 903system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses 904system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses 905system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses 906system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses 907system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses 908system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses 909system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses 910system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses 911system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency 912system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency 913system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency 914system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency 915system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency 916system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency 917system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency 918system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency 919system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked 920system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 921system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked 922system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 923system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked 924system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 925system.cpu.dcache.fast_writes 0 # number of fast writes performed 926system.cpu.dcache.cache_copies 0 # number of cache copies performed 927system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks 928system.cpu.dcache.writebacks::total 2066654 # number of writebacks 929system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits 930system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits 931system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits 932system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits 933system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits 934system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits 935system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits 936system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits 937system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses 938system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses 939system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses 940system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses 941system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses 942system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses 943system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses 944system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses 945system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles 946system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles 947system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles 948system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles 949system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles 950system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles 951system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles 952system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles 953system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses 954system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses 955system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses 956system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses 957system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses 958system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses 959system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses 960system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses 961system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency 962system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency 963system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency 964system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency 965system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency 966system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency 967system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency 968system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency 969system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 970 971---------- End Simulation Statistics ----------