1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.065497 # Number of seconds simulated
4sim_ticks 65497052500 # Number of ticks simulated
5final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 99498 # Simulator instruction rate (inst/s)
8host_op_rate 175200 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 41248682 # Simulator tick rate (ticks/s)
10host_mem_usage 388584 # Number of bytes of host memory used
11host_seconds 1587.86 # Real time elapsed on the host
12sim_insts 157988547 # Number of instructions simulated
13sim_ops 278192464 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory
16system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory
20system.physmem.bytes_written::total 9984 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 156 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller
38system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller
39system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41system.physmem.bytesRead 1945536 # Total number of bytes read from memory
42system.physmem.bytesWritten 9984 # Total number of bytes written to memory
43system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize()
44system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize()
45system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q
46system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
47system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis
63system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
81system.physmem.totGap 65497035500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Categorize read packet sizes
83system.physmem.readPktSize::1 0 # Categorize read packet sizes
84system.physmem.readPktSize::2 0 # Categorize read packet sizes
85system.physmem.readPktSize::3 0 # Categorize read packet sizes
86system.physmem.readPktSize::4 0 # Categorize read packet sizes
87system.physmem.readPktSize::5 0 # Categorize read packet sizes
88system.physmem.readPktSize::6 30400 # Categorize read packet sizes
89system.physmem.writePktSize::0 0 # Categorize write packet sizes
90system.physmem.writePktSize::1 0 # Categorize write packet sizes
91system.physmem.writePktSize::2 0 # Categorize write packet sizes
92system.physmem.writePktSize::3 0 # Categorize write packet sizes
93system.physmem.writePktSize::4 0 # Categorize write packet sizes
94system.physmem.writePktSize::5 0 # Categorize write packet sizes
95system.physmem.writePktSize::6 156 # Categorize write packet sizes
96system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 12 unchanged lines hidden (view full) ---

120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
160system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation
161system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation
162system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation
207system.physmem.totQLat 5969250 # Total cycles spent in queuing delays
208system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests
209system.physmem.totBusLat 151785000 # Total cycles spent in databus access
210system.physmem.totBankLat 423720000 # Total cycles spent in bank access
211system.physmem.avgQLat 196.64 # Average queueing delay per request
212system.physmem.avgBankLat 13957.90 # Average bank access latency per request
213system.physmem.avgBusLat 5000.00 # Average bus latency per request
214system.physmem.avgMemAccLat 19154.54 # Average memory access latency
215system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s
216system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s
217system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s
218system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s
219system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
220system.physmem.busUtil 0.23 # Data bus utilization in percentage
221system.physmem.avgRdQLen 0.01 # Average read queue length over time
222system.physmem.avgWrQLen 12.39 # Average write queue length over time
223system.physmem.readRowHits 29864 # Number of row buffer hits during reads
224system.physmem.writeRowHits 96 # Number of row buffer hits during writes
225system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads
226system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes
227system.physmem.avgGap 2143508.17 # Average gap between requests
228system.membus.throughput 29855634 # Throughput (bytes/s)
229system.membus.trans_dist::ReadReq 1399 # Transaction distribution
230system.membus.trans_dist::ReadResp 1397 # Transaction distribution
231system.membus.trans_dist::Writeback 156 # Transaction distribution
232system.membus.trans_dist::ReadExReq 29001 # Transaction distribution
233system.membus.trans_dist::ReadExResp 29001 # Transaction distribution
234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes)
235system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes)
236system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes)
237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes)
238system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes)
239system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes)
240system.membus.data_through_bus 1955456 # Total data (bytes)
241system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
242system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks)
243system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
244system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks)
245system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
246system.cpu.branchPred.lookups 33858224 # Number of BP lookups
247system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted
248system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect
249system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups
250system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits
251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
252system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage
253system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target.
254system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions.
255system.cpu.workload.num_syscalls 444 # Number of system calls
256system.cpu.numCycles 130994109 # number of cpu cycles simulated
257system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
258system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
259system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss
260system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed
261system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered
262system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken
263system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked
264system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing
265system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked
266system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
267system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps
268system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR
269system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched
270system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed
271system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total)
272system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total)
273system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total)
274system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
275system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total)
276system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total)
277system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total)
279system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total)
280system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total)
281system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle
289system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle
290system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle
291system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked
292system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running
293system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking
294system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing
295system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode
296system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing
297system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle
298system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking
299system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst
300system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running
301system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking
302system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename
303system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full
304system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full
305system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full
306system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed
307system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made
308system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups
309system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups
310system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
311system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing
312system.cpu.rename.serializingInsts 483 # count of serializing insts renamed
313system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed
314system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer
315system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit.
316system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit.
317system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads.
318system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores.
319system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec)
320system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ
321system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued
322system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued
323system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling
324system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph
325system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed
326system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle
329system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle
332system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle
343system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
344system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available
345system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available
346system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available
347system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available
348system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available
349system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available
350system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available
351system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available
352system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
353system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available
354system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available
355system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
373system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available
374system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available
375system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
376system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
377system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued
378system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued
379system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued
380system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued
381system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued
382system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued
383system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued
384system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued
385system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued
386system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued
407system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued
408system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued
409system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
410system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
411system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued
412system.cpu.iq.rate 2.292178 # Inst issue rate
413system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested
414system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst)
415system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads
416system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes
417system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses
418system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads
419system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes
420system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses
421system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses
422system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses
423system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores
424system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
425system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed
426system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed
427system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations
428system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed
429system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
430system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
431system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled
432system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked
433system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
434system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing
435system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking
436system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking
437system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ
438system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch
439system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions
440system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions
441system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions
442system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall
443system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall
444system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations
445system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly
446system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly
447system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute
448system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions
449system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed
450system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute
451system.cpu.iew.exec_swp 0 # number of swp insts executed
452system.cpu.iew.exec_nop 0 # number of nop insts executed
453system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed
454system.cpu.iew.exec_branches 30818444 # Number of branches executed
455system.cpu.iew.exec_stores 32924311 # Number of stores executed
456system.cpu.iew.exec_rate 2.281453 # Inst execution rate
457system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit
458system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back
459system.cpu.iew.wb_producers 218253384 # num instructions producing a value
460system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value
461system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
462system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle
463system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back
464system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
465system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit
466system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
467system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted
468system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle
474system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle
485system.cpu.commit.committedInsts 157988547 # Number of instructions committed
486system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
487system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
488system.cpu.commit.refs 122219137 # Number of memory references committed
489system.cpu.commit.loads 90779385 # Number of loads committed
490system.cpu.commit.membars 0 # Number of memory barriers committed
491system.cpu.commit.branches 29309705 # Number of branches committed
492system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
493system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
494system.cpu.commit.function_calls 4237596 # Number of function calls committed.
495system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached
496system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
497system.cpu.rob.rob_reads 415712868 # The number of ROB reads
498system.cpu.rob.rob_writes 627529396 # The number of ROB writes
499system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself
500system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling
501system.cpu.committedInsts 157988547 # Number of Instructions Simulated
502system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
503system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
504system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction
505system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads
506system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle
507system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads
508system.cpu.int_regfile_reads 483722109 # number of integer regfile reads
509system.cpu.int_regfile_writes 234582139 # number of integer regfile writes
510system.cpu.fp_regfile_reads 117 # number of floating regfile reads
511system.cpu.fp_regfile_writes 75 # number of floating regfile writes
512system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads
513system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes
514system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads
515system.cpu.misc_regfile_writes 1 # number of misc regfile writes
516system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s)
517system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution
518system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution
519system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution
520system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution
521system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution
522system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes)
523system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes)
524system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes)
525system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes)
526system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes)
527system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes)
528system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes)
529system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
530system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks)
531system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
532system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks)
533system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
534system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks)
535system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%)
536system.cpu.icache.tags.replacements 55 # number of replacements
537system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use
538system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks.
539system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks.
540system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks.
541system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
542system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor
543system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy
544system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy
545system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits
546system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits
547system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits
548system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits
549system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits
550system.cpu.icache.overall_hits::total 25573067 # number of overall hits
551system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses
552system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses
553system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses
554system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses
555system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses
556system.cpu.icache.overall_misses::total 1295 # number of overall misses
557system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles
558system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles
559system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles
560system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles
561system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles
562system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles
563system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses)
564system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses)
565system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses
566system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses
567system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses
568system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses
569system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses
570system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
571system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses
572system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
573system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
574system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
575system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency
576system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency
577system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency
578system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency
579system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency
580system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency
581system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked
582system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
583system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
584system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
585system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked
586system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
587system.cpu.icache.fast_writes 0 # number of fast writes performed
588system.cpu.icache.cache_copies 0 # number of cache copies performed
589system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits
590system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits
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594system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits
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606system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles
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617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency
618system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency
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627system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.283783 # Average occupied blocks per requestor
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744system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for overall accesses
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754system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency
755system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency
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839system.cpu.dcache.overall_mshr_misses::cpu.data 2076591 # number of overall MSHR misses
840system.cpu.dcache.overall_mshr_misses::total 2076591 # number of overall MSHR misses
841system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994515250 # number of ReadReq MSHR miss cycles
842system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994515250 # number of ReadReq MSHR miss cycles
843system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397679498 # number of WriteReq MSHR miss cycles
844system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397679498 # number of WriteReq MSHR miss cycles
845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392194748 # number of demand (read+write) MSHR miss cycles
846system.cpu.dcache.demand_mshr_miss_latency::total 24392194748 # number of demand (read+write) MSHR miss cycles
847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392194748 # number of overall MSHR miss cycles
848system.cpu.dcache.overall_mshr_miss_latency::total 24392194748 # number of overall MSHR miss cycles
849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046755 # mshr miss rate for ReadReq accesses
850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046755 # mshr miss rate for ReadReq accesses
851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses
852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses
853system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for demand accesses
854system.cpu.dcache.demand_mshr_miss_rate::total 0.028026 # mshr miss rate for demand accesses
855system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for overall accesses
856system.cpu.dcache.overall_mshr_miss_rate::total 0.028026 # mshr miss rate for overall accesses
857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.136407 # average ReadReq mshr miss latency
858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.136407 # average ReadReq mshr miss latency
859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29172.044360 # average WriteReq mshr miss latency
860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29172.044360 # average WriteReq mshr miss latency
861system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency
863system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency
865system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
866
867---------- End Simulation Statistics ----------