1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.065987 # Number of seconds simulated
4sim_ticks 65986743500 # Number of ticks simulated
5final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 84238 # Simulator instruction rate (inst/s)
8host_op_rate 148330 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 35183666 # Simulator tick rate (ticks/s)
10host_mem_usage 410392 # Number of bytes of host memory used
11host_seconds 1875.49 # Real time elapsed on the host
12sim_insts 157988547 # Number of instructions simulated
13sim_ops 278192464 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory
18system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory
22system.physmem.bytes_written::total 17920 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory
--- 243 unchanged lines hidden (view full) ---
267system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ)
268system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ)
269system.physmem_1.averagePower 673.182663 # Core power per rank (mW)
270system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states
271system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states
272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
273system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states
274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
275system.cpu.branchPred.lookups 40828848 # Number of BP lookups
276system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted
277system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect
278system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups
279system.cpu.branchPred.BTBHits 0 # Number of BTB hits
280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
281system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
282system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target.
283system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions.
284system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups.
285system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits.
286system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses.
287system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches.
288system.cpu_clk_domain.clock 500 # Clock period in ticks
289system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
290system.cpu.workload.num_syscalls 444 # Number of system calls
291system.cpu.numCycles 131973488 # number of cpu cycles simulated
292system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
293system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
294system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss
295system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed
296system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered
297system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken
298system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked
--- 278 unchanged lines hidden (view full) ---
577system.cpu.int_regfile_reads 504041942 # number of integer regfile reads
578system.cpu.int_regfile_writes 248656420 # number of integer regfile writes
579system.cpu.fp_regfile_reads 4180 # number of floating regfile reads
580system.cpu.fp_regfile_writes 782 # number of floating regfile writes
581system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads
582system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes
583system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads
584system.cpu.misc_regfile_writes 1 # number of misc regfile writes
585system.cpu.dcache.tags.replacements 2073508 # number of replacements
586system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use
587system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks.
588system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks.
589system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks.
590system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit.
591system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor
592system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy
593system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy
594system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
595system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id
596system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id
597system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
598system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
599system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses
600system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses
601system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits
602system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits
603system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits
604system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits
605system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits
606system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits
607system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits
608system.cpu.dcache.overall_hits::total 71894591 # number of overall hits
--- 80 unchanged lines hidden (view full) ---
689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency
690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency
691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency
692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency
693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
694system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
696system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
697system.cpu.icache.tags.replacements 93 # number of replacements
698system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use
699system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks.
700system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks.
701system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks.
702system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
703system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor
704system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy
705system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy
706system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id
707system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
708system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
709system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
710system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id
711system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id
712system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
713system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses
714system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses
715system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits
716system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits
717system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits
718system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits
719system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits
720system.cpu.icache.overall_hits::total 29996478 # number of overall hits
721system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses
722system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
782system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency
784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency
785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
786system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
788system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
789system.cpu.l2cache.tags.replacements 650 # number of replacements
790system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use
791system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks.
792system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks.
793system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks.
794system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
795system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor
796system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor
--- 6 unchanged lines hidden (view full) ---
803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
804system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
805system.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id
806system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id
807system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id
808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id
809system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses
810system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses
811system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits
812system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits
813system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits
814system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits
815system.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits
816system.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits
817system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits
818system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits
--- 126 unchanged lines hidden (view full) ---
945system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency
946system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency
947system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter.
948system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data.
949system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
950system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter.
951system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
952system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
953system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution
954system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution
955system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution
956system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution
957system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution
958system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution
959system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution
960system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution
--- 16 unchanged lines hidden (view full) ---
977system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
978system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram
979system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks)
980system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
981system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks)
982system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
983system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks)
984system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%)
985system.membus.trans_dist::ReadResp 1640 # Transaction distribution
986system.membus.trans_dist::WritebackDirty 280 # Transaction distribution
987system.membus.trans_dist::CleanEvict 45 # Transaction distribution
988system.membus.trans_dist::ReadExReq 28982 # Transaction distribution
989system.membus.trans_dist::ReadExResp 28982 # Transaction distribution
990system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution
991system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes)
992system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes)
--- 21 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.065987 # Number of seconds simulated
4sim_ticks 65986743500 # Number of ticks simulated
5final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 84238 # Simulator instruction rate (inst/s)
8host_op_rate 148330 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 35183666 # Simulator tick rate (ticks/s)
10host_mem_usage 410392 # Number of bytes of host memory used
11host_seconds 1875.49 # Real time elapsed on the host
12sim_insts 157988547 # Number of instructions simulated
13sim_ops 278192464 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory
18system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory
22system.physmem.bytes_written::total 17920 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory
--- 243 unchanged lines hidden (view full) ---
267system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ)
268system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ)
269system.physmem_1.averagePower 673.182663 # Core power per rank (mW)
270system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states
271system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states
272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
273system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states
274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
275system.cpu.branchPred.lookups 40828848 # Number of BP lookups
276system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted
277system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect
278system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups
279system.cpu.branchPred.BTBHits 0 # Number of BTB hits
280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
281system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
282system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target.
283system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions.
284system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups.
285system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits.
286system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses.
287system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches.
288system.cpu_clk_domain.clock 500 # Clock period in ticks
289system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
290system.cpu.workload.num_syscalls 444 # Number of system calls
291system.cpu.numCycles 131973488 # number of cpu cycles simulated
292system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
293system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
294system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss
295system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed
296system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered
297system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken
298system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked
--- 278 unchanged lines hidden (view full) ---
577system.cpu.int_regfile_reads 504041942 # number of integer regfile reads
578system.cpu.int_regfile_writes 248656420 # number of integer regfile writes
579system.cpu.fp_regfile_reads 4180 # number of floating regfile reads
580system.cpu.fp_regfile_writes 782 # number of floating regfile writes
581system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads
582system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes
583system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads
584system.cpu.misc_regfile_writes 1 # number of misc regfile writes
585system.cpu.dcache.tags.replacements 2073508 # number of replacements
586system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use
587system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks.
588system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks.
589system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks.
590system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit.
591system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor
592system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy
593system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy
594system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
595system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id
596system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id
597system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
598system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
599system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses
600system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses
601system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits
602system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits
603system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits
604system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits
605system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits
606system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits
607system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits
608system.cpu.dcache.overall_hits::total 71894591 # number of overall hits
--- 80 unchanged lines hidden (view full) ---
689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency
690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency
691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency
692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency
693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
694system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
696system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
697system.cpu.icache.tags.replacements 93 # number of replacements
698system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use
699system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks.
700system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks.
701system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks.
702system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
703system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor
704system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy
705system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy
706system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id
707system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
708system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
709system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
710system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id
711system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id
712system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
713system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses
714system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses
715system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits
716system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits
717system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits
718system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits
719system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits
720system.cpu.icache.overall_hits::total 29996478 # number of overall hits
721system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses
722system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
782system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency
784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency
785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
786system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
788system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
789system.cpu.l2cache.tags.replacements 650 # number of replacements
790system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use
791system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks.
792system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks.
793system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks.
794system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
795system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor
796system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor
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803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
804system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
805system.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id
806system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id
807system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id
808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id
809system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses
810system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses
811system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits
812system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits
813system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits
814system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits
815system.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits
816system.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits
817system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits
818system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits
--- 126 unchanged lines hidden (view full) ---
945system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency
946system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency
947system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter.
948system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data.
949system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
950system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter.
951system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
952system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
953system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution
954system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution
955system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution
956system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution
957system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution
958system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution
959system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution
960system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution
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977system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
978system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram
979system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks)
980system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
981system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks)
982system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
983system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks)
984system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%)
985system.membus.trans_dist::ReadResp 1640 # Transaction distribution
986system.membus.trans_dist::WritebackDirty 280 # Transaction distribution
987system.membus.trans_dist::CleanEvict 45 # Transaction distribution
988system.membus.trans_dist::ReadExReq 28982 # Transaction distribution
989system.membus.trans_dist::ReadExResp 28982 # Transaction distribution
990system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution
991system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes)
992system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes)
--- 21 unchanged lines hidden ---