1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.065614 # Number of seconds simulated
4sim_ticks 65613727000 # Number of ticks simulated
5final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 90206 # Simulator instruction rate (inst/s)
8host_op_rate 158838 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 37463203 # Simulator tick rate (ticks/s)
10host_mem_usage 416624 # Number of bytes of host memory used
11host_seconds 1751.42 # Real time elapsed on the host
12sim_insts 157988547 # Number of instructions simulated
13sim_ops 278192464 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory
16system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory
20system.physmem.bytes_written::total 10688 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 167 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 30419 # Number of read requests accepted
38system.physmem.writeReqs 167 # Number of write requests accepted
39system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue
40system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue
41system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM
42system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue
43system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM
44system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side
45system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side
46system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue
47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
49system.physmem.perBankRdBursts::0 1928 # Per bank write bursts
50system.physmem.perBankRdBursts::1 2077 # Per bank write bursts
51system.physmem.perBankRdBursts::2 2029 # Per bank write bursts
52system.physmem.perBankRdBursts::3 1927 # Per bank write bursts
53system.physmem.perBankRdBursts::4 2026 # Per bank write bursts
54system.physmem.perBankRdBursts::5 1899 # Per bank write bursts
55system.physmem.perBankRdBursts::6 1963 # Per bank write bursts
56system.physmem.perBankRdBursts::7 1862 # Per bank write bursts
57system.physmem.perBankRdBursts::8 1939 # Per bank write bursts
58system.physmem.perBankRdBursts::9 1933 # Per bank write bursts
59system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
60system.physmem.perBankRdBursts::11 1795 # Per bank write bursts
61system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
62system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
63system.physmem.perBankRdBursts::14 1821 # Per bank write bursts
64system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
65system.physmem.perBankWrBursts::0 15 # Per bank write bursts
66system.physmem.perBankWrBursts::1 95 # Per bank write bursts
67system.physmem.perBankWrBursts::2 7 # Per bank write bursts
68system.physmem.perBankWrBursts::3 11 # Per bank write bursts
69system.physmem.perBankWrBursts::4 6 # Per bank write bursts
70system.physmem.perBankWrBursts::5 0 # Per bank write bursts
71system.physmem.perBankWrBursts::6 12 # Per bank write bursts
72system.physmem.perBankWrBursts::7 0 # Per bank write bursts
73system.physmem.perBankWrBursts::8 0 # Per bank write bursts
74system.physmem.perBankWrBursts::9 5 # Per bank write bursts
75system.physmem.perBankWrBursts::10 3 # Per bank write bursts
76system.physmem.perBankWrBursts::11 0 # Per bank write bursts
77system.physmem.perBankWrBursts::12 0 # Per bank write bursts
78system.physmem.perBankWrBursts::13 0 # Per bank write bursts
79system.physmem.perBankWrBursts::14 0 # Per bank write bursts
80system.physmem.perBankWrBursts::15 0 # Per bank write bursts
81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
83system.physmem.totGap 65613689500 # Total gap between requests
84system.physmem.readPktSize::0 0 # Read request sizes (log2)
85system.physmem.readPktSize::1 0 # Read request sizes (log2)
86system.physmem.readPktSize::2 0 # Read request sizes (log2)
87system.physmem.readPktSize::3 0 # Read request sizes (log2)
88system.physmem.readPktSize::4 0 # Read request sizes (log2)
89system.physmem.readPktSize::5 0 # Read request sizes (log2)
90system.physmem.readPktSize::6 30419 # Read request sizes (log2)
91system.physmem.writePktSize::0 0 # Write request sizes (log2)
92system.physmem.writePktSize::1 0 # Write request sizes (log2)
93system.physmem.writePktSize::2 0 # Write request sizes (log2)
94system.physmem.writePktSize::3 0 # Write request sizes (log2)
95system.physmem.writePktSize::4 0 # Write request sizes (log2)
96system.physmem.writePktSize::5 0 # Write request sizes (log2)
97system.physmem.writePktSize::6 167 # Write request sizes (log2)
98system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 12 unchanged lines hidden (view full) ---

122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
130system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
162system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation
165system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation
166system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation
260system.physmem.totQLat 92483500 # Total ticks spent queuing
261system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM
262system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers
263system.physmem.totBankLat 434417500 # Total ticks spent accessing banks
264system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst
265system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst
266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
267system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst
268system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s
269system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s
270system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s
271system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s
272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
273system.physmem.busUtil 0.23 # Data bus utilization in percentage
274system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads
275system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
276system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
277system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing
278system.physmem.readRowHits 29156 # Number of row buffer hits during reads
279system.physmem.writeRowHits 97 # Number of row buffer hits during writes
280system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads
281system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes
282system.physmem.avgGap 2145219.69 # Average gap between requests
283system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined
284system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state
285system.membus.throughput 29832782 # Throughput (bytes/s)
286system.membus.trans_dist::ReadReq 1416 # Transaction distribution
287system.membus.trans_dist::ReadResp 1415 # Transaction distribution
288system.membus.trans_dist::Writeback 167 # Transaction distribution
289system.membus.trans_dist::ReadExReq 29003 # Transaction distribution
290system.membus.trans_dist::ReadExResp 29003 # Transaction distribution
291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes)
292system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes)
293system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes)
294system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes)
295system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes)
296system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes)
297system.membus.data_through_bus 1957440 # Total data (bytes)
298system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
299system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks)
300system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
301system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks)
302system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
303system.cpu.branchPred.lookups 33859770 # Number of BP lookups
304system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted
305system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect
306system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups
307system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits
308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
309system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage
310system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target.
311system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions.
312system.cpu.workload.num_syscalls 444 # Number of system calls
313system.cpu.numCycles 131227460 # number of cpu cycles simulated
314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
316system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss
317system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed
318system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered
319system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken
320system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked
321system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing
322system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked
323system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
324system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps
325system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR
326system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched
327system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed
328system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
344system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle
346system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle
347system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle
348system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked
349system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running
350system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking
351system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing
352system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode
353system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing
354system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle
355system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking
356system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst
357system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running
358system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking
359system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename
360system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full
361system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full
362system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full
363system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed
364system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made
365system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups
366system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups
367system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
368system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing
369system.cpu.rename.serializingInsts 483 # count of serializing insts renamed
370system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed
371system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer
372system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit.
373system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit.
374system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads.
375system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores.
376system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec)
377system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ
378system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued
379system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued
380system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling
381system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph
382system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed
383system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle
384system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle
385system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle
386system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
387system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle
388system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle
400system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
401system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available
402system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
403system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
404system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
405system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
406system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
407system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
408system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
409system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
410system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
413system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
414system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
415system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
416system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
417system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
430system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available
431system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available
432system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
433system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
434system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued
435system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued
436system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued
437system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued
438system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued
439system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued
440system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued
441system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued
442system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued
443system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued
444system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued
445system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued
446system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued
447system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued
451system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued
452system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued
453system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued
454system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued
464system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued
465system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued
466system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
467system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
468system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued
469system.cpu.iq.rate 2.288206 # Inst issue rate
470system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested
471system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst)
472system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads
473system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes
474system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses
475system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads
476system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes
477system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses
478system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses
479system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses
480system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores
481system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
482system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed
483system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed
484system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations
485system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed
486system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
487system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
488system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled
489system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked
490system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
491system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing
492system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking
493system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking
494system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ
495system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch
496system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions
497system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions
498system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions
499system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall
500system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall
501system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations
502system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly
503system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly
504system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute
505system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions
506system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed
507system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute
508system.cpu.iew.exec_swp 0 # number of swp insts executed
509system.cpu.iew.exec_nop 0 # number of nop insts executed
510system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed
511system.cpu.iew.exec_branches 30820824 # Number of branches executed
512system.cpu.iew.exec_stores 32925944 # Number of stores executed
513system.cpu.iew.exec_rate 2.277516 # Inst execution rate
514system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit
515system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back
516system.cpu.iew.wb_producers 218260008 # num instructions producing a value
517system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value
518system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
519system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle
520system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back
521system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
522system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit
523system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
524system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted
525system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle
526system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle
527system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle
528system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
529system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle
530system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle
531system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle
532system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle
533system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle
534system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle
535system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle
536system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle
538system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
539system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle
542system.cpu.commit.committedInsts 157988547 # Number of instructions committed
543system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
544system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
545system.cpu.commit.refs 122219137 # Number of memory references committed
546system.cpu.commit.loads 90779385 # Number of loads committed
547system.cpu.commit.membars 0 # Number of memory barriers committed
548system.cpu.commit.branches 29309705 # Number of branches committed
549system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
550system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
551system.cpu.commit.function_calls 4237596 # Number of function calls committed.
552system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached
553system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
554system.cpu.rob.rob_reads 415950983 # The number of ROB reads
555system.cpu.rob.rob_writes 627545403 # The number of ROB writes
556system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself
557system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling
558system.cpu.committedInsts 157988547 # Number of Instructions Simulated
559system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
560system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
561system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction
562system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads
563system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle
564system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads
565system.cpu.int_regfile_reads 483744134 # number of integer regfile reads
566system.cpu.int_regfile_writes 234595253 # number of integer regfile writes
567system.cpu.fp_regfile_reads 141 # number of floating regfile reads
568system.cpu.fp_regfile_writes 77 # number of floating regfile writes
569system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads
570system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes
571system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads
572system.cpu.misc_regfile_writes 1 # number of misc regfile writes
573system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s)
574system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution
577system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution
578system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution
579system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes)
580system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes)
582system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes)
583system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes)
584system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes)
585system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes)
586system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
587system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks)
588system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
589system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks)
590system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
591system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks)
592system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%)
593system.cpu.icache.tags.replacements 57 # number of replacements
594system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use
595system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks.
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615system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles
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634system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
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636system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
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659system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles
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662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles
663system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles
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669system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
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671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency
672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
673system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
675system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
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680system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks.
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683system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618 # Average occupied blocks per requestor
684system.cpu.l2cache.tags.occ_blocks::cpu.inst 670.515764 # Average occupied blocks per requestor
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693system.cpu.l2cache.Writeback_hits::writebacks 2066887 # number of Writeback hits
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728system.cpu.l2cache.Writeback_accesses::writebacks 2066887 # number of Writeback accesses(hits+misses)
729system.cpu.l2cache.Writeback_accesses::total 2066887 # number of Writeback accesses(hits+misses)
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731system.cpu.l2cache.ReadExReq_accesses::total 82323 # number of ReadExReq accesses(hits+misses)
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736system.cpu.l2cache.overall_accesses::cpu.data 2076611 # number of overall (read+write) accesses
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757system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
758system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency
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762system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
763system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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765system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
766system.cpu.l2cache.fast_writes 0 # number of fast writes performed
767system.cpu.l2cache.cache_copies 0 # number of cache copies performed
768system.cpu.l2cache.writebacks::writebacks 167 # number of writebacks
769system.cpu.l2cache.writebacks::total 167 # number of writebacks
770system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses
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804system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303 # average ReadReq mshr miss latency
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811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency
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813system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency
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837system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses
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847system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles
848system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses)
849system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses)
850system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
851system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
852system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses
853system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses
854system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses
855system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses
856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses
857system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses
858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses
859system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses
860system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses
861system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses
862system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses
863system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses
864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613 # average ReadReq miss latency
865system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency
866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency
867system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency
868system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency
869system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency
870system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency
871system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency
872system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked
873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
874system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked
875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
876system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443930 # average number of cycles each access was blocked
877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
878system.cpu.dcache.fast_writes 0 # number of fast writes performed
879system.cpu.dcache.cache_copies 0 # number of cache copies performed
880system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks
881system.cpu.dcache.writebacks::total 2066887 # number of writebacks
882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits
883system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits
884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits
885system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits
886system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits
887system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits
888system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits
889system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits
890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses
891system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses
892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses
893system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses
894system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses
895system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses
896system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses
897system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses
898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles
899system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles
900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles
901system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles
902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles
903system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles
904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles
905system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles
906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses
907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses
908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses
909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses
910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses
911system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses
912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses
913system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses
914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency
915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency
916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency
917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency
918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency
919system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency
920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency
921system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency
922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
923
924---------- End Simulation Statistics ----------