1[root] 2type=Root 3children=system |
4eventq_index=0 |
5full_system=false |
6sim_quantum=0 |
7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
17eventq_index=0 |
18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= --- 5 unchanged lines hidden (view full) --- 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 |
39eventq_index=0 |
40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb |
71eventq_index=0 72fetchBufferSize=64 |
73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 --- 45 unchanged lines hidden (view full) --- 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.apic_clk_domain] 131type=DerivedClockDomain 132clk_divider=16 133clk_domain=system.cpu_clk_domain |
134eventq_index=0 |
135 136[system.cpu.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 |
143eventq_index=0 |
144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain |
159eventq_index=0 |
160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 --- 6 unchanged lines hidden (view full) --- 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain |
182eventq_index=0 |
183hit_latency=2 184size=262144 185 186[system.cpu.dtb] 187type=X86TLB 188children=walker |
189eventq_index=0 |
190size=64 191walker=system.cpu.dtb.walker 192 193[system.cpu.dtb.walker] 194type=X86PagetableWalker 195clk_domain=system.cpu_clk_domain |
196eventq_index=0 |
197num_squash_per_cycle=4 198system=system 199port=system.cpu.toL2Bus.slave[3] 200 201[system.cpu.fuPool] 202type=FUPool 203children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 204FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 |
205eventq_index=0 |
206 207[system.cpu.fuPool.FUList0] 208type=FUDesc 209children=opList 210count=6 |
211eventq_index=0 |
212opList=system.cpu.fuPool.FUList0.opList 213 214[system.cpu.fuPool.FUList0.opList] 215type=OpDesc |
216eventq_index=0 |
217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2 |
225eventq_index=0 |
226opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 227 228[system.cpu.fuPool.FUList1.opList0] 229type=OpDesc |
230eventq_index=0 |
231issueLat=1 232opClass=IntMult 233opLat=3 234 235[system.cpu.fuPool.FUList1.opList1] 236type=OpDesc |
237eventq_index=0 |
238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 |
246eventq_index=0 |
247opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 248 249[system.cpu.fuPool.FUList2.opList0] 250type=OpDesc |
251eventq_index=0 |
252issueLat=1 253opClass=FloatAdd 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList1] 257type=OpDesc |
258eventq_index=0 |
259issueLat=1 260opClass=FloatCmp 261opLat=2 262 263[system.cpu.fuPool.FUList2.opList2] 264type=OpDesc |
265eventq_index=0 |
266issueLat=1 267opClass=FloatCvt 268opLat=2 269 270[system.cpu.fuPool.FUList3] 271type=FUDesc 272children=opList0 opList1 opList2 273count=2 |
274eventq_index=0 |
275opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 276 277[system.cpu.fuPool.FUList3.opList0] 278type=OpDesc |
279eventq_index=0 |
280issueLat=1 281opClass=FloatMult 282opLat=4 283 284[system.cpu.fuPool.FUList3.opList1] 285type=OpDesc |
286eventq_index=0 |
287issueLat=12 288opClass=FloatDiv 289opLat=12 290 291[system.cpu.fuPool.FUList3.opList2] 292type=OpDesc |
293eventq_index=0 |
294issueLat=24 295opClass=FloatSqrt 296opLat=24 297 298[system.cpu.fuPool.FUList4] 299type=FUDesc 300children=opList 301count=0 |
302eventq_index=0 |
303opList=system.cpu.fuPool.FUList4.opList 304 305[system.cpu.fuPool.FUList4.opList] 306type=OpDesc |
307eventq_index=0 |
308issueLat=1 309opClass=MemRead 310opLat=1 311 312[system.cpu.fuPool.FUList5] 313type=FUDesc 314children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 315count=4 |
316eventq_index=0 |
317opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 318 319[system.cpu.fuPool.FUList5.opList00] 320type=OpDesc |
321eventq_index=0 |
322issueLat=1 323opClass=SimdAdd 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList01] 327type=OpDesc |
328eventq_index=0 |
329issueLat=1 330opClass=SimdAddAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList02] 334type=OpDesc |
335eventq_index=0 |
336issueLat=1 337opClass=SimdAlu 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList03] 341type=OpDesc |
342eventq_index=0 |
343issueLat=1 344opClass=SimdCmp 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList04] 348type=OpDesc |
349eventq_index=0 |
350issueLat=1 351opClass=SimdCvt 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList05] 355type=OpDesc |
356eventq_index=0 |
357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList06] 362type=OpDesc |
363eventq_index=0 |
364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList07] 369type=OpDesc |
370eventq_index=0 |
371issueLat=1 372opClass=SimdMultAcc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList08] 376type=OpDesc |
377eventq_index=0 |
378issueLat=1 379opClass=SimdShift 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList09] 383type=OpDesc |
384eventq_index=0 |
385issueLat=1 386opClass=SimdShiftAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList10] 390type=OpDesc |
391eventq_index=0 |
392issueLat=1 393opClass=SimdSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList11] 397type=OpDesc |
398eventq_index=0 |
399issueLat=1 400opClass=SimdFloatAdd 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList12] 404type=OpDesc |
405eventq_index=0 |
406issueLat=1 407opClass=SimdFloatAlu 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList13] 411type=OpDesc |
412eventq_index=0 |
413issueLat=1 414opClass=SimdFloatCmp 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList14] 418type=OpDesc |
419eventq_index=0 |
420issueLat=1 421opClass=SimdFloatCvt 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList15] 425type=OpDesc |
426eventq_index=0 |
427issueLat=1 428opClass=SimdFloatDiv 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList16] 432type=OpDesc |
433eventq_index=0 |
434issueLat=1 435opClass=SimdFloatMisc 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList17] 439type=OpDesc |
440eventq_index=0 |
441issueLat=1 442opClass=SimdFloatMult 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList18] 446type=OpDesc |
447eventq_index=0 |
448issueLat=1 449opClass=SimdFloatMultAcc 450opLat=1 451 452[system.cpu.fuPool.FUList5.opList19] 453type=OpDesc |
454eventq_index=0 |
455issueLat=1 456opClass=SimdFloatSqrt 457opLat=1 458 459[system.cpu.fuPool.FUList6] 460type=FUDesc 461children=opList 462count=0 |
463eventq_index=0 |
464opList=system.cpu.fuPool.FUList6.opList 465 466[system.cpu.fuPool.FUList6.opList] 467type=OpDesc |
468eventq_index=0 |
469issueLat=1 470opClass=MemWrite 471opLat=1 472 473[system.cpu.fuPool.FUList7] 474type=FUDesc 475children=opList0 opList1 476count=4 |
477eventq_index=0 |
478opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 479 480[system.cpu.fuPool.FUList7.opList0] 481type=OpDesc |
482eventq_index=0 |
483issueLat=1 484opClass=MemRead 485opLat=1 486 487[system.cpu.fuPool.FUList7.opList1] 488type=OpDesc |
489eventq_index=0 |
490issueLat=1 491opClass=MemWrite 492opLat=1 493 494[system.cpu.fuPool.FUList8] 495type=FUDesc 496children=opList 497count=1 |
498eventq_index=0 |
499opList=system.cpu.fuPool.FUList8.opList 500 501[system.cpu.fuPool.FUList8.opList] 502type=OpDesc |
503eventq_index=0 |
504issueLat=3 505opClass=IprAccess 506opLat=3 507 508[system.cpu.icache] 509type=BaseCache 510children=tags 511addr_ranges=0:18446744073709551615 512assoc=2 513clk_domain=system.cpu_clk_domain |
514eventq_index=0 |
515forward_snoops=true 516hit_latency=2 517is_top_level=true 518max_miss_count=0 519mshrs=4 520prefetch_on_access=false 521prefetcher=Null 522response_latency=2 --- 6 unchanged lines hidden (view full) --- 529cpu_side=system.cpu.icache_port 530mem_side=system.cpu.toL2Bus.slave[0] 531 532[system.cpu.icache.tags] 533type=LRU 534assoc=2 535block_size=64 536clk_domain=system.cpu_clk_domain |
537eventq_index=0 |
538hit_latency=2 539size=131072 540 541[system.cpu.interrupts] 542type=X86LocalApic 543clk_domain=system.cpu.apic_clk_domain |
544eventq_index=0 |
545int_latency=1000 546pio_addr=2305843009213693952 547pio_latency=100000 548system=system 549int_master=system.membus.slave[2] 550int_slave=system.membus.master[2] 551pio=system.membus.master[1] 552 553[system.cpu.isa] 554type=X86ISA |
555eventq_index=0 |
556 557[system.cpu.itb] 558type=X86TLB 559children=walker |
560eventq_index=0 |
561size=64 562walker=system.cpu.itb.walker 563 564[system.cpu.itb.walker] 565type=X86PagetableWalker 566clk_domain=system.cpu_clk_domain |
567eventq_index=0 |
568num_squash_per_cycle=4 569system=system 570port=system.cpu.toL2Bus.slave[2] 571 572[system.cpu.l2cache] 573type=BaseCache 574children=tags 575addr_ranges=0:18446744073709551615 576assoc=8 577clk_domain=system.cpu_clk_domain |
578eventq_index=0 |
579forward_snoops=true 580hit_latency=20 581is_top_level=false 582max_miss_count=0 583mshrs=20 584prefetch_on_access=false 585prefetcher=Null 586response_latency=20 --- 6 unchanged lines hidden (view full) --- 593cpu_side=system.cpu.toL2Bus.master[0] 594mem_side=system.membus.slave[1] 595 596[system.cpu.l2cache.tags] 597type=LRU 598assoc=8 599block_size=64 600clk_domain=system.cpu_clk_domain |
601eventq_index=0 |
602hit_latency=20 603size=2097152 604 605[system.cpu.toL2Bus] 606type=CoherentBus 607clk_domain=system.cpu_clk_domain |
608eventq_index=0 |
609header_cycles=1 610system=system 611use_default_range=false 612width=32 613master=system.cpu.l2cache.cpu_side 614slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 615 616[system.cpu.tracer] 617type=ExeTracer |
618eventq_index=0 |
619 620[system.cpu.workload] 621type=LiveProcess 622cmd=mcf mcf.in 623cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 624egid=100 625env= 626errout=cerr 627euid=100 |
628eventq_index=0 629executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf |
630gid=100 |
631input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in |
632max_stack_size=67108864 633output=cout 634pid=100 635ppid=99 636simpoint=55300000000 637system=system 638uid=100 639 640[system.cpu_clk_domain] 641type=SrcClockDomain 642clock=500 |
643eventq_index=0 |
644voltage_domain=system.voltage_domain 645 646[system.membus] 647type=CoherentBus 648clk_domain=system.clk_domain |
649eventq_index=0 |
650header_cycles=1 651system=system 652use_default_range=false 653width=8 654master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 655slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 656 657[system.physmem] 658type=SimpleDRAM 659activation_limit=4 660addr_mapping=RaBaChCo 661banks_per_rank=8 662burst_length=8 663channels=1 664clk_domain=system.clk_domain 665conf_table_reported=true 666device_bus_width=8 667device_rowbuffer_size=1024 668devices_per_rank=8 |
669eventq_index=0 |
670in_addr_map=true 671mem_sched_policy=frfcfs 672null=false 673page_policy=open 674range=0:268435455 675ranks_per_channel=2 676read_buffer_size=32 677static_backend_latency=10000 678static_frontend_latency=10000 679tBURST=5000 680tCL=13750 |
681tRAS=35000 |
682tRCD=13750 683tREFI=7800000 684tRFC=300000 685tRP=13750 |
686tRRD=6250 |
687tWTR=7500 688tXAW=40000 689write_buffer_size=32 |
690write_high_thresh_perc=70 691write_low_thresh_perc=0 |
692port=system.membus.master[0] 693 694[system.voltage_domain] 695type=VoltageDomain |
696eventq_index=0 |
697voltage=1.000000 698 |