Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

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config.ini (9885:afd9ea6101d9)	config.ini (9924:31ef410b6843)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=true 88numIQEntries=64	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=true 88numIQEntries=64
	89numPhysCCRegs=1280
89numPhysFloatRegs=256 90numPhysIntRegs=256 91numROBEntries=192 92numRobs=1 93numThreads=1 94profile=0 95progress_interval=0 96renameToDecodeDelay=1 97renameToFetchDelay=1 98renameToIEWDelay=2 99renameToROBDelay=1 100renameWidth=8 101simpoint_start_insts= 102smtCommitPolicy=RoundRobin 103smtFetchPolicy=SingleThread 104smtIQPolicy=Partitioned 105smtIQThreshold=100 106smtLSQPolicy=Partitioned 107smtLSQThreshold=100 108smtNumFetchingThreads=1 109smtROBPolicy=Partitioned 110smtROBThreshold=100 111squashWidth=8 112store_set_clear_period=250000 113switched_out=false 114system=system 115tracer=system.cpu.tracer 116trapLatency=13 117wbDepth=1 118wbWidth=8 119workload=system.cpu.workload 120dcache_port=system.cpu.dcache.cpu_side 121icache_port=system.cpu.icache.cpu_side 122 123[system.cpu.apic_clk_domain] 124type=DerivedClockDomain 125clk_divider=16 126clk_domain=system.cpu_clk_domain 127 128[system.cpu.branchPred] 129type=BranchPredictor 130BTBEntries=4096 131BTBTagSize=16 132RASSize=16 133choiceCtrBits=2 134choicePredictorSize=8192 135globalCtrBits=2 136globalPredictorSize=8192 137instShiftAmt=2 138localCtrBits=2 139localHistoryTableSize=2048 140localPredictorSize=2048 141numThreads=1 142predType=tournament 143 144[system.cpu.dcache] 145type=BaseCache 146children=tags 147addr_ranges=0:18446744073709551615 148assoc=2 149clk_domain=system.cpu_clk_domain 150forward_snoops=true 151hit_latency=2 152is_top_level=true 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null 157response_latency=2 158size=262144 159system=system 160tags=system.cpu.dcache.tags 161tgts_per_mshr=20 162two_queue=false 163write_buffers=8 164cpu_side=system.cpu.dcache_port 165mem_side=system.cpu.toL2Bus.slave[1] 166 167[system.cpu.dcache.tags] 168type=LRU 169assoc=2 170block_size=64 171clk_domain=system.cpu_clk_domain 172hit_latency=2 173size=262144 174 175[system.cpu.dtb] 176type=X86TLB 177children=walker 178size=64 179walker=system.cpu.dtb.walker 180 181[system.cpu.dtb.walker] 182type=X86PagetableWalker 183clk_domain=system.cpu_clk_domain 184num_squash_per_cycle=4 185system=system 186port=system.cpu.toL2Bus.slave[3] 187 188[system.cpu.fuPool] 189type=FUPool 190children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 191FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 192 193[system.cpu.fuPool.FUList0] 194type=FUDesc 195children=opList 196count=6 197opList=system.cpu.fuPool.FUList0.opList 198 199[system.cpu.fuPool.FUList0.opList] 200type=OpDesc 201issueLat=1 202opClass=IntAlu 203opLat=1 204 205[system.cpu.fuPool.FUList1] 206type=FUDesc 207children=opList0 opList1 208count=2 209opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 210 211[system.cpu.fuPool.FUList1.opList0] 212type=OpDesc 213issueLat=1 214opClass=IntMult 215opLat=3 216 217[system.cpu.fuPool.FUList1.opList1] 218type=OpDesc 219issueLat=19 220opClass=IntDiv 221opLat=20 222 223[system.cpu.fuPool.FUList2] 224type=FUDesc 225children=opList0 opList1 opList2 226count=4 227opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 228 229[system.cpu.fuPool.FUList2.opList0] 230type=OpDesc 231issueLat=1 232opClass=FloatAdd 233opLat=2 234 235[system.cpu.fuPool.FUList2.opList1] 236type=OpDesc 237issueLat=1 238opClass=FloatCmp 239opLat=2 240 241[system.cpu.fuPool.FUList2.opList2] 242type=OpDesc 243issueLat=1 244opClass=FloatCvt 245opLat=2 246 247[system.cpu.fuPool.FUList3] 248type=FUDesc 249children=opList0 opList1 opList2 250count=2 251opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 252 253[system.cpu.fuPool.FUList3.opList0] 254type=OpDesc 255issueLat=1 256opClass=FloatMult 257opLat=4 258 259[system.cpu.fuPool.FUList3.opList1] 260type=OpDesc 261issueLat=12 262opClass=FloatDiv 263opLat=12 264 265[system.cpu.fuPool.FUList3.opList2] 266type=OpDesc 267issueLat=24 268opClass=FloatSqrt 269opLat=24 270 271[system.cpu.fuPool.FUList4] 272type=FUDesc 273children=opList 274count=0 275opList=system.cpu.fuPool.FUList4.opList 276 277[system.cpu.fuPool.FUList4.opList] 278type=OpDesc 279issueLat=1 280opClass=MemRead 281opLat=1 282 283[system.cpu.fuPool.FUList5] 284type=FUDesc 285children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 286count=4 287opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 288 289[system.cpu.fuPool.FUList5.opList00] 290type=OpDesc 291issueLat=1 292opClass=SimdAdd 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList01] 296type=OpDesc 297issueLat=1 298opClass=SimdAddAcc 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList02] 302type=OpDesc 303issueLat=1 304opClass=SimdAlu 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList03] 308type=OpDesc 309issueLat=1 310opClass=SimdCmp 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList04] 314type=OpDesc 315issueLat=1 316opClass=SimdCvt 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList05] 320type=OpDesc 321issueLat=1 322opClass=SimdMisc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList06] 326type=OpDesc 327issueLat=1 328opClass=SimdMult 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList07] 332type=OpDesc 333issueLat=1 334opClass=SimdMultAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList08] 338type=OpDesc 339issueLat=1 340opClass=SimdShift 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList09] 344type=OpDesc 345issueLat=1 346opClass=SimdShiftAcc 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList10] 350type=OpDesc 351issueLat=1 352opClass=SimdSqrt 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList11] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatAdd 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList12] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatAlu 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList13] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatCmp 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList14] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatCvt 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList15] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatDiv 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList16] 386type=OpDesc 387issueLat=1 388opClass=SimdFloatMisc 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList17] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatMult 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList18] 398type=OpDesc 399issueLat=1 400opClass=SimdFloatMultAcc 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList19] 404type=OpDesc 405issueLat=1 406opClass=SimdFloatSqrt 407opLat=1 408 409[system.cpu.fuPool.FUList6] 410type=FUDesc 411children=opList 412count=0 413opList=system.cpu.fuPool.FUList6.opList 414 415[system.cpu.fuPool.FUList6.opList] 416type=OpDesc 417issueLat=1 418opClass=MemWrite 419opLat=1 420 421[system.cpu.fuPool.FUList7] 422type=FUDesc 423children=opList0 opList1 424count=4 425opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 426 427[system.cpu.fuPool.FUList7.opList0] 428type=OpDesc 429issueLat=1 430opClass=MemRead 431opLat=1 432 433[system.cpu.fuPool.FUList7.opList1] 434type=OpDesc 435issueLat=1 436opClass=MemWrite 437opLat=1 438 439[system.cpu.fuPool.FUList8] 440type=FUDesc 441children=opList 442count=1 443opList=system.cpu.fuPool.FUList8.opList 444 445[system.cpu.fuPool.FUList8.opList] 446type=OpDesc 447issueLat=3 448opClass=IprAccess 449opLat=3 450 451[system.cpu.icache] 452type=BaseCache 453children=tags 454addr_ranges=0:18446744073709551615 455assoc=2 456clk_domain=system.cpu_clk_domain 457forward_snoops=true 458hit_latency=2 459is_top_level=true 460max_miss_count=0 461mshrs=4 462prefetch_on_access=false 463prefetcher=Null 464response_latency=2 465size=131072 466system=system 467tags=system.cpu.icache.tags 468tgts_per_mshr=20 469two_queue=false 470write_buffers=8 471cpu_side=system.cpu.icache_port 472mem_side=system.cpu.toL2Bus.slave[0] 473 474[system.cpu.icache.tags] 475type=LRU 476assoc=2 477block_size=64 478clk_domain=system.cpu_clk_domain 479hit_latency=2 480size=131072 481 482[system.cpu.interrupts] 483type=X86LocalApic 484clk_domain=system.cpu.apic_clk_domain 485int_latency=1000 486pio_addr=2305843009213693952 487pio_latency=100000 488system=system 489int_master=system.membus.slave[2] 490int_slave=system.membus.master[2] 491pio=system.membus.master[1] 492 493[system.cpu.isa] 494type=X86ISA 495 496[system.cpu.itb] 497type=X86TLB 498children=walker 499size=64 500walker=system.cpu.itb.walker 501 502[system.cpu.itb.walker] 503type=X86PagetableWalker 504clk_domain=system.cpu_clk_domain 505num_squash_per_cycle=4 506system=system 507port=system.cpu.toL2Bus.slave[2] 508 509[system.cpu.l2cache] 510type=BaseCache 511children=tags 512addr_ranges=0:18446744073709551615 513assoc=8 514clk_domain=system.cpu_clk_domain 515forward_snoops=true 516hit_latency=20 517is_top_level=false 518max_miss_count=0 519mshrs=20 520prefetch_on_access=false 521prefetcher=Null 522response_latency=20 523size=2097152 524system=system 525tags=system.cpu.l2cache.tags 526tgts_per_mshr=12 527two_queue=false 528write_buffers=8 529cpu_side=system.cpu.toL2Bus.master[0] 530mem_side=system.membus.slave[1] 531 532[system.cpu.l2cache.tags] 533type=LRU 534assoc=8 535block_size=64 536clk_domain=system.cpu_clk_domain 537hit_latency=20 538size=2097152 539 540[system.cpu.toL2Bus] 541type=CoherentBus 542clk_domain=system.cpu_clk_domain 543header_cycles=1 544system=system 545use_default_range=false 546width=32 547master=system.cpu.l2cache.cpu_side 548slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 549 550[system.cpu.tracer] 551type=ExeTracer 552 553[system.cpu.workload] 554type=LiveProcess 555cmd=mcf mcf.in 556cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 557egid=100 558env= 559errout=cerr 560euid=100 561executable=/dist/m5/cpu2000/binaries/x86/linux/mcf 562gid=100 563input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in 564max_stack_size=67108864 565output=cout 566pid=100 567ppid=99 568simpoint=55300000000 569system=system 570uid=100 571 572[system.cpu_clk_domain] 573type=SrcClockDomain 574clock=500 575voltage_domain=system.voltage_domain 576 577[system.membus] 578type=CoherentBus 579clk_domain=system.clk_domain 580header_cycles=1 581system=system 582use_default_range=false 583width=8 584master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 585slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 586 587[system.physmem] 588type=SimpleDRAM 589activation_limit=4 590addr_mapping=RaBaChCo 591banks_per_rank=8 592burst_length=8 593channels=1 594clk_domain=system.clk_domain 595conf_table_reported=true 596device_bus_width=8 597device_rowbuffer_size=1024 598devices_per_rank=8 599in_addr_map=true 600mem_sched_policy=frfcfs 601null=false 602page_policy=open 603range=0:268435455 604ranks_per_channel=2 605read_buffer_size=32 606static_backend_latency=10000 607static_frontend_latency=10000 608tBURST=5000 609tCL=13750 610tRCD=13750 611tREFI=7800000 612tRFC=300000 613tRP=13750 614tWTR=7500 615tXAW=40000 616write_buffer_size=32 617write_thresh_perc=70 618port=system.membus.master[0] 619 620[system.voltage_domain] 621type=VoltageDomain 622voltage=1.000000 623	90numPhysFloatRegs=256 91numPhysIntRegs=256 92numROBEntries=192 93numRobs=1 94numThreads=1 95profile=0 96progress_interval=0 97renameToDecodeDelay=1 98renameToFetchDelay=1 99renameToIEWDelay=2 100renameToROBDelay=1 101renameWidth=8 102simpoint_start_insts= 103smtCommitPolicy=RoundRobin 104smtFetchPolicy=SingleThread 105smtIQPolicy=Partitioned 106smtIQThreshold=100 107smtLSQPolicy=Partitioned 108smtLSQThreshold=100 109smtNumFetchingThreads=1 110smtROBPolicy=Partitioned 111smtROBThreshold=100 112squashWidth=8 113store_set_clear_period=250000 114switched_out=false 115system=system 116tracer=system.cpu.tracer 117trapLatency=13 118wbDepth=1 119wbWidth=8 120workload=system.cpu.workload 121dcache_port=system.cpu.dcache.cpu_side 122icache_port=system.cpu.icache.cpu_side 123 124[system.cpu.apic_clk_domain] 125type=DerivedClockDomain 126clk_divider=16 127clk_domain=system.cpu_clk_domain 128 129[system.cpu.branchPred] 130type=BranchPredictor 131BTBEntries=4096 132BTBTagSize=16 133RASSize=16 134choiceCtrBits=2 135choicePredictorSize=8192 136globalCtrBits=2 137globalPredictorSize=8192 138instShiftAmt=2 139localCtrBits=2 140localHistoryTableSize=2048 141localPredictorSize=2048 142numThreads=1 143predType=tournament 144 145[system.cpu.dcache] 146type=BaseCache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain 151forward_snoops=true 152hit_latency=2 153is_top_level=true 154max_miss_count=0 155mshrs=4 156prefetch_on_access=false 157prefetcher=Null 158response_latency=2 159size=262144 160system=system 161tags=system.cpu.dcache.tags 162tgts_per_mshr=20 163two_queue=false 164write_buffers=8 165cpu_side=system.cpu.dcache_port 166mem_side=system.cpu.toL2Bus.slave[1] 167 168[system.cpu.dcache.tags] 169type=LRU 170assoc=2 171block_size=64 172clk_domain=system.cpu_clk_domain 173hit_latency=2 174size=262144 175 176[system.cpu.dtb] 177type=X86TLB 178children=walker 179size=64 180walker=system.cpu.dtb.walker 181 182[system.cpu.dtb.walker] 183type=X86PagetableWalker 184clk_domain=system.cpu_clk_domain 185num_squash_per_cycle=4 186system=system 187port=system.cpu.toL2Bus.slave[3] 188 189[system.cpu.fuPool] 190type=FUPool 191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 192FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 193 194[system.cpu.fuPool.FUList0] 195type=FUDesc 196children=opList 197count=6 198opList=system.cpu.fuPool.FUList0.opList 199 200[system.cpu.fuPool.FUList0.opList] 201type=OpDesc 202issueLat=1 203opClass=IntAlu 204opLat=1 205 206[system.cpu.fuPool.FUList1] 207type=FUDesc 208children=opList0 opList1 209count=2 210opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 211 212[system.cpu.fuPool.FUList1.opList0] 213type=OpDesc 214issueLat=1 215opClass=IntMult 216opLat=3 217 218[system.cpu.fuPool.FUList1.opList1] 219type=OpDesc 220issueLat=19 221opClass=IntDiv 222opLat=20 223 224[system.cpu.fuPool.FUList2] 225type=FUDesc 226children=opList0 opList1 opList2 227count=4 228opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 229 230[system.cpu.fuPool.FUList2.opList0] 231type=OpDesc 232issueLat=1 233opClass=FloatAdd 234opLat=2 235 236[system.cpu.fuPool.FUList2.opList1] 237type=OpDesc 238issueLat=1 239opClass=FloatCmp 240opLat=2 241 242[system.cpu.fuPool.FUList2.opList2] 243type=OpDesc 244issueLat=1 245opClass=FloatCvt 246opLat=2 247 248[system.cpu.fuPool.FUList3] 249type=FUDesc 250children=opList0 opList1 opList2 251count=2 252opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 253 254[system.cpu.fuPool.FUList3.opList0] 255type=OpDesc 256issueLat=1 257opClass=FloatMult 258opLat=4 259 260[system.cpu.fuPool.FUList3.opList1] 261type=OpDesc 262issueLat=12 263opClass=FloatDiv 264opLat=12 265 266[system.cpu.fuPool.FUList3.opList2] 267type=OpDesc 268issueLat=24 269opClass=FloatSqrt 270opLat=24 271 272[system.cpu.fuPool.FUList4] 273type=FUDesc 274children=opList 275count=0 276opList=system.cpu.fuPool.FUList4.opList 277 278[system.cpu.fuPool.FUList4.opList] 279type=OpDesc 280issueLat=1 281opClass=MemRead 282opLat=1 283 284[system.cpu.fuPool.FUList5] 285type=FUDesc 286children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 287count=4 288opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 289 290[system.cpu.fuPool.FUList5.opList00] 291type=OpDesc 292issueLat=1 293opClass=SimdAdd 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList01] 297type=OpDesc 298issueLat=1 299opClass=SimdAddAcc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList02] 303type=OpDesc 304issueLat=1 305opClass=SimdAlu 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList03] 309type=OpDesc 310issueLat=1 311opClass=SimdCmp 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList04] 315type=OpDesc 316issueLat=1 317opClass=SimdCvt 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList05] 321type=OpDesc 322issueLat=1 323opClass=SimdMisc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList06] 327type=OpDesc 328issueLat=1 329opClass=SimdMult 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList07] 333type=OpDesc 334issueLat=1 335opClass=SimdMultAcc 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList08] 339type=OpDesc 340issueLat=1 341opClass=SimdShift 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList09] 345type=OpDesc 346issueLat=1 347opClass=SimdShiftAcc 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList10] 351type=OpDesc 352issueLat=1 353opClass=SimdSqrt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList11] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatAdd 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList12] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatAlu 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList13] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatCmp 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList14] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatCvt 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList15] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatDiv 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList16] 387type=OpDesc 388issueLat=1 389opClass=SimdFloatMisc 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList17] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatMult 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList18] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatMultAcc 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList19] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatSqrt 408opLat=1 409 410[system.cpu.fuPool.FUList6] 411type=FUDesc 412children=opList 413count=0 414opList=system.cpu.fuPool.FUList6.opList 415 416[system.cpu.fuPool.FUList6.opList] 417type=OpDesc 418issueLat=1 419opClass=MemWrite 420opLat=1 421 422[system.cpu.fuPool.FUList7] 423type=FUDesc 424children=opList0 opList1 425count=4 426opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 427 428[system.cpu.fuPool.FUList7.opList0] 429type=OpDesc 430issueLat=1 431opClass=MemRead 432opLat=1 433 434[system.cpu.fuPool.FUList7.opList1] 435type=OpDesc 436issueLat=1 437opClass=MemWrite 438opLat=1 439 440[system.cpu.fuPool.FUList8] 441type=FUDesc 442children=opList 443count=1 444opList=system.cpu.fuPool.FUList8.opList 445 446[system.cpu.fuPool.FUList8.opList] 447type=OpDesc 448issueLat=3 449opClass=IprAccess 450opLat=3 451 452[system.cpu.icache] 453type=BaseCache 454children=tags 455addr_ranges=0:18446744073709551615 456assoc=2 457clk_domain=system.cpu_clk_domain 458forward_snoops=true 459hit_latency=2 460is_top_level=true 461max_miss_count=0 462mshrs=4 463prefetch_on_access=false 464prefetcher=Null 465response_latency=2 466size=131072 467system=system 468tags=system.cpu.icache.tags 469tgts_per_mshr=20 470two_queue=false 471write_buffers=8 472cpu_side=system.cpu.icache_port 473mem_side=system.cpu.toL2Bus.slave[0] 474 475[system.cpu.icache.tags] 476type=LRU 477assoc=2 478block_size=64 479clk_domain=system.cpu_clk_domain 480hit_latency=2 481size=131072 482 483[system.cpu.interrupts] 484type=X86LocalApic 485clk_domain=system.cpu.apic_clk_domain 486int_latency=1000 487pio_addr=2305843009213693952 488pio_latency=100000 489system=system 490int_master=system.membus.slave[2] 491int_slave=system.membus.master[2] 492pio=system.membus.master[1] 493 494[system.cpu.isa] 495type=X86ISA 496 497[system.cpu.itb] 498type=X86TLB 499children=walker 500size=64 501walker=system.cpu.itb.walker 502 503[system.cpu.itb.walker] 504type=X86PagetableWalker 505clk_domain=system.cpu_clk_domain 506num_squash_per_cycle=4 507system=system 508port=system.cpu.toL2Bus.slave[2] 509 510[system.cpu.l2cache] 511type=BaseCache 512children=tags 513addr_ranges=0:18446744073709551615 514assoc=8 515clk_domain=system.cpu_clk_domain 516forward_snoops=true 517hit_latency=20 518is_top_level=false 519max_miss_count=0 520mshrs=20 521prefetch_on_access=false 522prefetcher=Null 523response_latency=20 524size=2097152 525system=system 526tags=system.cpu.l2cache.tags 527tgts_per_mshr=12 528two_queue=false 529write_buffers=8 530cpu_side=system.cpu.toL2Bus.master[0] 531mem_side=system.membus.slave[1] 532 533[system.cpu.l2cache.tags] 534type=LRU 535assoc=8 536block_size=64 537clk_domain=system.cpu_clk_domain 538hit_latency=20 539size=2097152 540 541[system.cpu.toL2Bus] 542type=CoherentBus 543clk_domain=system.cpu_clk_domain 544header_cycles=1 545system=system 546use_default_range=false 547width=32 548master=system.cpu.l2cache.cpu_side 549slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 550 551[system.cpu.tracer] 552type=ExeTracer 553 554[system.cpu.workload] 555type=LiveProcess 556cmd=mcf mcf.in 557cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 558egid=100 559env= 560errout=cerr 561euid=100 562executable=/dist/m5/cpu2000/binaries/x86/linux/mcf 563gid=100 564input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in 565max_stack_size=67108864 566output=cout 567pid=100 568ppid=99 569simpoint=55300000000 570system=system 571uid=100 572 573[system.cpu_clk_domain] 574type=SrcClockDomain 575clock=500 576voltage_domain=system.voltage_domain 577 578[system.membus] 579type=CoherentBus 580clk_domain=system.clk_domain 581header_cycles=1 582system=system 583use_default_range=false 584width=8 585master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 586slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 587 588[system.physmem] 589type=SimpleDRAM 590activation_limit=4 591addr_mapping=RaBaChCo 592banks_per_rank=8 593burst_length=8 594channels=1 595clk_domain=system.clk_domain 596conf_table_reported=true 597device_bus_width=8 598device_rowbuffer_size=1024 599devices_per_rank=8 600in_addr_map=true 601mem_sched_policy=frfcfs 602null=false 603page_policy=open 604range=0:268435455 605ranks_per_channel=2 606read_buffer_size=32 607static_backend_latency=10000 608static_frontend_latency=10000 609tBURST=5000 610tCL=13750 611tRCD=13750 612tREFI=7800000 613tRFC=300000 614tRP=13750 615tWTR=7500 616tXAW=40000 617write_buffer_size=32 618write_thresh_perc=70 619port=system.membus.master[0] 620 621[system.voltage_domain] 622type=VoltageDomain 623voltage=1.000000 624