Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

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config.ini (9213:5cab5448909c)	config.ini (9348:44d31345e360)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a
13clock=1	13clock=1000
14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU	14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload	33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts	34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts
	81isa=system.cpu.isa
81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=true 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64	82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=true 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64
132clock=1	133clock=500
133forward_snoops=true 134hash_delay=1	134forward_snoops=true 135hash_delay=1
	136hit_latency=2
135is_top_level=true	137is_top_level=true
136latency=1000
137max_miss_count=0	138max_miss_count=0
138mshrs=10	139mshrs=4
139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null	140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null
	144response_latency=2
143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port 151mem_side=system.cpu.toL2Bus.slave[1] 152 153[system.cpu.dtb] 154type=X86TLB 155children=walker 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=X86PagetableWalker	145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port 153mem_side=system.cpu.toL2Bus.slave[1] 154 155[system.cpu.dtb] 156type=X86TLB 157children=walker 158size=64 159walker=system.cpu.dtb.walker 160 161[system.cpu.dtb.walker] 162type=X86PagetableWalker
161clock=1	163clock=500
162system=system 163port=system.cpu.toL2Bus.slave[3] 164 165[system.cpu.fuPool] 166type=FUPool 167children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 168FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 169 170[system.cpu.fuPool.FUList0] 171type=FUDesc 172children=opList 173count=6 174opList=system.cpu.fuPool.FUList0.opList 175 176[system.cpu.fuPool.FUList0.opList] 177type=OpDesc 178issueLat=1 179opClass=IntAlu 180opLat=1 181 182[system.cpu.fuPool.FUList1] 183type=FUDesc 184children=opList0 opList1 185count=2 186opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 187 188[system.cpu.fuPool.FUList1.opList0] 189type=OpDesc 190issueLat=1 191opClass=IntMult 192opLat=3 193 194[system.cpu.fuPool.FUList1.opList1] 195type=OpDesc 196issueLat=19 197opClass=IntDiv 198opLat=20 199 200[system.cpu.fuPool.FUList2] 201type=FUDesc 202children=opList0 opList1 opList2 203count=4 204opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 205 206[system.cpu.fuPool.FUList2.opList0] 207type=OpDesc 208issueLat=1 209opClass=FloatAdd 210opLat=2 211 212[system.cpu.fuPool.FUList2.opList1] 213type=OpDesc 214issueLat=1 215opClass=FloatCmp 216opLat=2 217 218[system.cpu.fuPool.FUList2.opList2] 219type=OpDesc 220issueLat=1 221opClass=FloatCvt 222opLat=2 223 224[system.cpu.fuPool.FUList3] 225type=FUDesc 226children=opList0 opList1 opList2 227count=2 228opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 229 230[system.cpu.fuPool.FUList3.opList0] 231type=OpDesc 232issueLat=1 233opClass=FloatMult 234opLat=4 235 236[system.cpu.fuPool.FUList3.opList1] 237type=OpDesc 238issueLat=12 239opClass=FloatDiv 240opLat=12 241 242[system.cpu.fuPool.FUList3.opList2] 243type=OpDesc 244issueLat=24 245opClass=FloatSqrt 246opLat=24 247 248[system.cpu.fuPool.FUList4] 249type=FUDesc 250children=opList 251count=0 252opList=system.cpu.fuPool.FUList4.opList 253 254[system.cpu.fuPool.FUList4.opList] 255type=OpDesc 256issueLat=1 257opClass=MemRead 258opLat=1 259 260[system.cpu.fuPool.FUList5] 261type=FUDesc 262children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 263count=4 264opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 265 266[system.cpu.fuPool.FUList5.opList00] 267type=OpDesc 268issueLat=1 269opClass=SimdAdd 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList01] 273type=OpDesc 274issueLat=1 275opClass=SimdAddAcc 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList02] 279type=OpDesc 280issueLat=1 281opClass=SimdAlu 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList03] 285type=OpDesc 286issueLat=1 287opClass=SimdCmp 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList04] 291type=OpDesc 292issueLat=1 293opClass=SimdCvt 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList05] 297type=OpDesc 298issueLat=1 299opClass=SimdMisc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList06] 303type=OpDesc 304issueLat=1 305opClass=SimdMult 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList07] 309type=OpDesc 310issueLat=1 311opClass=SimdMultAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList08] 315type=OpDesc 316issueLat=1 317opClass=SimdShift 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList09] 321type=OpDesc 322issueLat=1 323opClass=SimdShiftAcc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList10] 327type=OpDesc 328issueLat=1 329opClass=SimdSqrt 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList11] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatAdd 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList12] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList13] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList14] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList15] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatDiv 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList16] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMisc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList17] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatMult 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList18] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatMultAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList19] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatSqrt 384opLat=1 385 386[system.cpu.fuPool.FUList6] 387type=FUDesc 388children=opList 389count=0 390opList=system.cpu.fuPool.FUList6.opList 391 392[system.cpu.fuPool.FUList6.opList] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu.fuPool.FUList7] 399type=FUDesc 400children=opList0 opList1 401count=4 402opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 403 404[system.cpu.fuPool.FUList7.opList0] 405type=OpDesc 406issueLat=1 407opClass=MemRead 408opLat=1 409 410[system.cpu.fuPool.FUList7.opList1] 411type=OpDesc 412issueLat=1 413opClass=MemWrite 414opLat=1 415 416[system.cpu.fuPool.FUList8] 417type=FUDesc 418children=opList 419count=1 420opList=system.cpu.fuPool.FUList8.opList 421 422[system.cpu.fuPool.FUList8.opList] 423type=OpDesc 424issueLat=3 425opClass=IprAccess 426opLat=3 427 428[system.cpu.icache] 429type=BaseCache 430addr_ranges=0:18446744073709551615 431assoc=2 432block_size=64	164system=system 165port=system.cpu.toL2Bus.slave[3] 166 167[system.cpu.fuPool] 168type=FUPool 169children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 170FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 171 172[system.cpu.fuPool.FUList0] 173type=FUDesc 174children=opList 175count=6 176opList=system.cpu.fuPool.FUList0.opList 177 178[system.cpu.fuPool.FUList0.opList] 179type=OpDesc 180issueLat=1 181opClass=IntAlu 182opLat=1 183 184[system.cpu.fuPool.FUList1] 185type=FUDesc 186children=opList0 opList1 187count=2 188opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 189 190[system.cpu.fuPool.FUList1.opList0] 191type=OpDesc 192issueLat=1 193opClass=IntMult 194opLat=3 195 196[system.cpu.fuPool.FUList1.opList1] 197type=OpDesc 198issueLat=19 199opClass=IntDiv 200opLat=20 201 202[system.cpu.fuPool.FUList2] 203type=FUDesc 204children=opList0 opList1 opList2 205count=4 206opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 207 208[system.cpu.fuPool.FUList2.opList0] 209type=OpDesc 210issueLat=1 211opClass=FloatAdd 212opLat=2 213 214[system.cpu.fuPool.FUList2.opList1] 215type=OpDesc 216issueLat=1 217opClass=FloatCmp 218opLat=2 219 220[system.cpu.fuPool.FUList2.opList2] 221type=OpDesc 222issueLat=1 223opClass=FloatCvt 224opLat=2 225 226[system.cpu.fuPool.FUList3] 227type=FUDesc 228children=opList0 opList1 opList2 229count=2 230opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 231 232[system.cpu.fuPool.FUList3.opList0] 233type=OpDesc 234issueLat=1 235opClass=FloatMult 236opLat=4 237 238[system.cpu.fuPool.FUList3.opList1] 239type=OpDesc 240issueLat=12 241opClass=FloatDiv 242opLat=12 243 244[system.cpu.fuPool.FUList3.opList2] 245type=OpDesc 246issueLat=24 247opClass=FloatSqrt 248opLat=24 249 250[system.cpu.fuPool.FUList4] 251type=FUDesc 252children=opList 253count=0 254opList=system.cpu.fuPool.FUList4.opList 255 256[system.cpu.fuPool.FUList4.opList] 257type=OpDesc 258issueLat=1 259opClass=MemRead 260opLat=1 261 262[system.cpu.fuPool.FUList5] 263type=FUDesc 264children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 265count=4 266opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 267 268[system.cpu.fuPool.FUList5.opList00] 269type=OpDesc 270issueLat=1 271opClass=SimdAdd 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList01] 275type=OpDesc 276issueLat=1 277opClass=SimdAddAcc 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList02] 281type=OpDesc 282issueLat=1 283opClass=SimdAlu 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList03] 287type=OpDesc 288issueLat=1 289opClass=SimdCmp 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList04] 293type=OpDesc 294issueLat=1 295opClass=SimdCvt 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList05] 299type=OpDesc 300issueLat=1 301opClass=SimdMisc 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList06] 305type=OpDesc 306issueLat=1 307opClass=SimdMult 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList07] 311type=OpDesc 312issueLat=1 313opClass=SimdMultAcc 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList08] 317type=OpDesc 318issueLat=1 319opClass=SimdShift 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList09] 323type=OpDesc 324issueLat=1 325opClass=SimdShiftAcc 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList10] 329type=OpDesc 330issueLat=1 331opClass=SimdSqrt 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList11] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatAdd 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList12] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatAlu 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList13] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatCmp 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList14] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatCvt 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList15] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatDiv 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList16] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatMisc 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList17] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatMult 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList18] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatMultAcc 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList19] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatSqrt 386opLat=1 387 388[system.cpu.fuPool.FUList6] 389type=FUDesc 390children=opList 391count=0 392opList=system.cpu.fuPool.FUList6.opList 393 394[system.cpu.fuPool.FUList6.opList] 395type=OpDesc 396issueLat=1 397opClass=MemWrite 398opLat=1 399 400[system.cpu.fuPool.FUList7] 401type=FUDesc 402children=opList0 opList1 403count=4 404opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 405 406[system.cpu.fuPool.FUList7.opList0] 407type=OpDesc 408issueLat=1 409opClass=MemRead 410opLat=1 411 412[system.cpu.fuPool.FUList7.opList1] 413type=OpDesc 414issueLat=1 415opClass=MemWrite 416opLat=1 417 418[system.cpu.fuPool.FUList8] 419type=FUDesc 420children=opList 421count=1 422opList=system.cpu.fuPool.FUList8.opList 423 424[system.cpu.fuPool.FUList8.opList] 425type=OpDesc 426issueLat=3 427opClass=IprAccess 428opLat=3 429 430[system.cpu.icache] 431type=BaseCache 432addr_ranges=0:18446744073709551615 433assoc=2 434block_size=64
433clock=1	435clock=500
434forward_snoops=true 435hash_delay=1	436forward_snoops=true 437hash_delay=1
	438hit_latency=2
436is_top_level=true	439is_top_level=true
437latency=1000
438max_miss_count=0	440max_miss_count=0
439mshrs=10	441mshrs=4
440prefetch_on_access=false 441prefetcher=Null 442prioritizeRequests=false 443repl=Null	442prefetch_on_access=false 443prefetcher=Null 444prioritizeRequests=false 445repl=Null
	446response_latency=2
444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port 452mem_side=system.cpu.toL2Bus.slave[0] 453 454[system.cpu.interrupts] 455type=X86LocalApic	447size=131072 448subblock_size=0 449system=system 450tgts_per_mshr=20 451trace_addr=0 452two_queue=false 453write_buffers=8 454cpu_side=system.cpu.icache_port 455mem_side=system.cpu.toL2Bus.slave[0] 456 457[system.cpu.interrupts] 458type=X86LocalApic
456clock=1	459clock=500
457int_latency=1000 458pio_addr=2305843009213693952 459pio_latency=100000 460system=system 461int_master=system.membus.slave[2] 462int_slave=system.membus.master[2] 463pio=system.membus.master[1] 464	460int_latency=1000 461pio_addr=2305843009213693952 462pio_latency=100000 463system=system 464int_master=system.membus.slave[2] 465int_slave=system.membus.master[2] 466pio=system.membus.master[1] 467
	468[system.cpu.isa] 469type=X86ISA 470
465[system.cpu.itb] 466type=X86TLB 467children=walker 468size=64 469walker=system.cpu.itb.walker 470 471[system.cpu.itb.walker] 472type=X86PagetableWalker	471[system.cpu.itb] 472type=X86TLB 473children=walker 474size=64 475walker=system.cpu.itb.walker 476 477[system.cpu.itb.walker] 478type=X86PagetableWalker
473clock=1	479clock=500
474system=system 475port=system.cpu.toL2Bus.slave[2] 476 477[system.cpu.l2cache] 478type=BaseCache 479addr_ranges=0:18446744073709551615	480system=system 481port=system.cpu.toL2Bus.slave[2] 482 483[system.cpu.l2cache] 484type=BaseCache 485addr_ranges=0:18446744073709551615
480assoc=2	486assoc=8
481block_size=64	487block_size=64
482clock=1	488clock=500
483forward_snoops=true 484hash_delay=1	489forward_snoops=true 490hash_delay=1
	491hit_latency=20
485is_top_level=false	492is_top_level=false
486latency=1000
487max_miss_count=0	493max_miss_count=0
488mshrs=10	494mshrs=20
489prefetch_on_access=false 490prefetcher=Null 491prioritizeRequests=false 492repl=Null	495prefetch_on_access=false 496prefetcher=Null 497prioritizeRequests=false 498repl=Null
	499response_latency=20
493size=2097152 494subblock_size=0 495system=system	500size=2097152 501subblock_size=0 502system=system
496tgts_per_mshr=5	503tgts_per_mshr=12
497trace_addr=0 498two_queue=false 499write_buffers=8 500cpu_side=system.cpu.toL2Bus.master[0] 501mem_side=system.membus.slave[1] 502 503[system.cpu.toL2Bus] 504type=CoherentBus 505block_size=64	504trace_addr=0 505two_queue=false 506write_buffers=8 507cpu_side=system.cpu.toL2Bus.master[0] 508mem_side=system.membus.slave[1] 509 510[system.cpu.toL2Bus] 511type=CoherentBus 512block_size=64
506clock=1000	513clock=500
507header_cycles=1 508use_default_range=false	514header_cycles=1 515use_default_range=false
509width=8	516width=32
510master=system.cpu.l2cache.cpu_side 511slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 512 513[system.cpu.tracer] 514type=ExeTracer 515 516[system.cpu.workload] 517type=LiveProcess 518cmd=mcf mcf.in 519cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 520egid=100 521env= 522errout=cerr 523euid=100	517master=system.cpu.l2cache.cpu_side 518slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 519 520[system.cpu.tracer] 521type=ExeTracer 522 523[system.cpu.workload] 524type=LiveProcess 525cmd=mcf mcf.in 526cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 527egid=100 528env= 529errout=cerr 530euid=100
524executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf	531executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf
525gid=100	532gid=100
526input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in	533input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
527max_stack_size=67108864 528output=cout 529pid=100 530ppid=99 531simpoint=55300000000 532system=system 533uid=100 534 535[system.membus] 536type=CoherentBus 537block_size=64 538clock=1000 539header_cycles=1 540use_default_range=false 541width=8 542master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 543slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 544 545[system.physmem]	534max_stack_size=67108864 535output=cout 536pid=100 537ppid=99 538simpoint=55300000000 539system=system 540uid=100 541 542[system.membus] 543type=CoherentBus 544block_size=64 545clock=1000 546header_cycles=1 547use_default_range=false 548width=8 549master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 550slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 551 552[system.physmem]
546type=SimpleMemory 547clock=1	553type=SimpleDRAM 554addr_mapping=openmap 555banks_per_rank=8 556clock=1000
548conf_table_reported=false	557conf_table_reported=false
549file=
550in_addr_map=true	558in_addr_map=true
551latency=30000 552latency_var=0	559lines_per_rowbuffer=64 560mem_sched_policy=fcfs
553null=false	561null=false
	562page_policy=open
554range=0:268435455	563range=0:268435455
	564ranks_per_channel=2 565read_buffer_size=32 566tBURST=4000 567tCL=14000 568tRCD=14000 569tREFI=7800000 570tRFC=300000 571tRP=14000 572tWTR=1000 573write_buffer_size=32 574write_thresh_perc=70
555zero=false 556port=system.membus.master[0] 557	575zero=false 576port=system.membus.master[0] 577