Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

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config.ini (11103:38f6188421e0)	config.ini (11384:e3cbd2823210)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0
	18exit_on_work_items=false
18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false	19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false
	28multi_thread=false
27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=true 100numIQEntries=64 101numPhysCCRegs=1280 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.apic_clk_domain] 137type=DerivedClockDomain 138clk_divider=16 139clk_domain=system.cpu_clk_domain 140eventq_index=0 141 142[system.cpu.branchPred] 143type=TournamentBP 144BTBEntries=4096 145BTBTagSize=16 146RASSize=16 147choiceCtrBits=2 148choicePredictorSize=8192 149eventq_index=0 150globalCtrBits=2 151globalPredictorSize=8192 152instShiftAmt=2 153localCtrBits=2 154localHistoryTableSize=2048 155localPredictorSize=2048 156numThreads=1 157 158[system.cpu.dcache] 159type=Cache 160children=tags 161addr_ranges=0:18446744073709551615 162assoc=2 163clk_domain=system.cpu_clk_domain	29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=true 102numIQEntries=64 103numPhysCCRegs=1280 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.apic_clk_domain] 139type=DerivedClockDomain 140clk_divider=16 141clk_domain=system.cpu_clk_domain 142eventq_index=0 143 144[system.cpu.branchPred] 145type=TournamentBP 146BTBEntries=4096 147BTBTagSize=16 148RASSize=16 149choiceCtrBits=2 150choicePredictorSize=8192 151eventq_index=0 152globalCtrBits=2 153globalPredictorSize=8192 154instShiftAmt=2 155localCtrBits=2 156localHistoryTableSize=2048 157localPredictorSize=2048 158numThreads=1 159 160[system.cpu.dcache] 161type=Cache 162children=tags 163addr_ranges=0:18446744073709551615 164assoc=2 165clk_domain=system.cpu_clk_domain
	166clusivity=mostly_incl
164demand_mshr_reserve=1 165eventq_index=0	167demand_mshr_reserve=1 168eventq_index=0
166forward_snoops=true
167hit_latency=2 168is_read_only=false 169max_miss_count=0 170mshrs=4 171prefetch_on_access=false 172prefetcher=Null 173response_latency=2 174sequential_access=false 175size=262144 176system=system 177tags=system.cpu.dcache.tags 178tgts_per_mshr=20 179write_buffers=8	169hit_latency=2 170is_read_only=false 171max_miss_count=0 172mshrs=4 173prefetch_on_access=false 174prefetcher=Null 175response_latency=2 176sequential_access=false 177size=262144 178system=system 179tags=system.cpu.dcache.tags 180tgts_per_mshr=20 181write_buffers=8
	182writeback_clean=false
180cpu_side=system.cpu.dcache_port 181mem_side=system.cpu.toL2Bus.slave[1] 182 183[system.cpu.dcache.tags] 184type=LRU 185assoc=2 186block_size=64 187clk_domain=system.cpu_clk_domain 188eventq_index=0 189hit_latency=2 190sequential_access=false 191size=262144 192 193[system.cpu.dtb] 194type=X86TLB 195children=walker 196eventq_index=0 197size=64 198walker=system.cpu.dtb.walker 199 200[system.cpu.dtb.walker] 201type=X86PagetableWalker 202clk_domain=system.cpu_clk_domain 203eventq_index=0 204num_squash_per_cycle=4 205system=system 206port=system.cpu.toL2Bus.slave[3] 207 208[system.cpu.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 212eventq_index=0 213 214[system.cpu.fuPool.FUList0] 215type=FUDesc 216children=opList 217count=6 218eventq_index=0 219opList=system.cpu.fuPool.FUList0.opList 220 221[system.cpu.fuPool.FUList0.opList] 222type=OpDesc 223eventq_index=0 224opClass=IntAlu 225opLat=1 226pipelined=true 227 228[system.cpu.fuPool.FUList1] 229type=FUDesc 230children=opList0 opList1 231count=2 232eventq_index=0 233opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 234 235[system.cpu.fuPool.FUList1.opList0] 236type=OpDesc 237eventq_index=0 238opClass=IntMult 239opLat=3 240pipelined=true 241 242[system.cpu.fuPool.FUList1.opList1] 243type=OpDesc 244eventq_index=0 245opClass=IntDiv 246opLat=1 247pipelined=false 248 249[system.cpu.fuPool.FUList2] 250type=FUDesc 251children=opList0 opList1 opList2 252count=4 253eventq_index=0 254opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 255 256[system.cpu.fuPool.FUList2.opList0] 257type=OpDesc 258eventq_index=0 259opClass=FloatAdd 260opLat=2 261pipelined=true 262 263[system.cpu.fuPool.FUList2.opList1] 264type=OpDesc 265eventq_index=0 266opClass=FloatCmp 267opLat=2 268pipelined=true 269 270[system.cpu.fuPool.FUList2.opList2] 271type=OpDesc 272eventq_index=0 273opClass=FloatCvt 274opLat=2 275pipelined=true 276 277[system.cpu.fuPool.FUList3] 278type=FUDesc 279children=opList0 opList1 opList2 280count=2 281eventq_index=0 282opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 283 284[system.cpu.fuPool.FUList3.opList0] 285type=OpDesc 286eventq_index=0 287opClass=FloatMult 288opLat=4 289pipelined=true 290 291[system.cpu.fuPool.FUList3.opList1] 292type=OpDesc 293eventq_index=0 294opClass=FloatDiv 295opLat=12 296pipelined=false 297 298[system.cpu.fuPool.FUList3.opList2] 299type=OpDesc 300eventq_index=0 301opClass=FloatSqrt 302opLat=24 303pipelined=false 304 305[system.cpu.fuPool.FUList4] 306type=FUDesc 307children=opList 308count=0 309eventq_index=0 310opList=system.cpu.fuPool.FUList4.opList 311 312[system.cpu.fuPool.FUList4.opList] 313type=OpDesc 314eventq_index=0 315opClass=MemRead 316opLat=1 317pipelined=true 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323eventq_index=0 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc 328eventq_index=0 329opClass=SimdAdd 330opLat=1 331pipelined=true 332 333[system.cpu.fuPool.FUList5.opList01] 334type=OpDesc 335eventq_index=0 336opClass=SimdAddAcc 337opLat=1 338pipelined=true 339 340[system.cpu.fuPool.FUList5.opList02] 341type=OpDesc 342eventq_index=0 343opClass=SimdAlu 344opLat=1 345pipelined=true 346 347[system.cpu.fuPool.FUList5.opList03] 348type=OpDesc 349eventq_index=0 350opClass=SimdCmp 351opLat=1 352pipelined=true 353 354[system.cpu.fuPool.FUList5.opList04] 355type=OpDesc 356eventq_index=0 357opClass=SimdCvt 358opLat=1 359pipelined=true 360 361[system.cpu.fuPool.FUList5.opList05] 362type=OpDesc 363eventq_index=0 364opClass=SimdMisc 365opLat=1 366pipelined=true 367 368[system.cpu.fuPool.FUList5.opList06] 369type=OpDesc 370eventq_index=0 371opClass=SimdMult 372opLat=1 373pipelined=true 374 375[system.cpu.fuPool.FUList5.opList07] 376type=OpDesc 377eventq_index=0 378opClass=SimdMultAcc 379opLat=1 380pipelined=true 381 382[system.cpu.fuPool.FUList5.opList08] 383type=OpDesc 384eventq_index=0 385opClass=SimdShift 386opLat=1 387pipelined=true 388 389[system.cpu.fuPool.FUList5.opList09] 390type=OpDesc 391eventq_index=0 392opClass=SimdShiftAcc 393opLat=1 394pipelined=true 395 396[system.cpu.fuPool.FUList5.opList10] 397type=OpDesc 398eventq_index=0 399opClass=SimdSqrt 400opLat=1 401pipelined=true 402 403[system.cpu.fuPool.FUList5.opList11] 404type=OpDesc 405eventq_index=0 406opClass=SimdFloatAdd 407opLat=1 408pipelined=true 409 410[system.cpu.fuPool.FUList5.opList12] 411type=OpDesc 412eventq_index=0 413opClass=SimdFloatAlu 414opLat=1 415pipelined=true 416 417[system.cpu.fuPool.FUList5.opList13] 418type=OpDesc 419eventq_index=0 420opClass=SimdFloatCmp 421opLat=1 422pipelined=true 423 424[system.cpu.fuPool.FUList5.opList14] 425type=OpDesc 426eventq_index=0 427opClass=SimdFloatCvt 428opLat=1 429pipelined=true 430 431[system.cpu.fuPool.FUList5.opList15] 432type=OpDesc 433eventq_index=0 434opClass=SimdFloatDiv 435opLat=1 436pipelined=true 437 438[system.cpu.fuPool.FUList5.opList16] 439type=OpDesc 440eventq_index=0 441opClass=SimdFloatMisc 442opLat=1 443pipelined=true 444 445[system.cpu.fuPool.FUList5.opList17] 446type=OpDesc 447eventq_index=0 448opClass=SimdFloatMult 449opLat=1 450pipelined=true 451 452[system.cpu.fuPool.FUList5.opList18] 453type=OpDesc 454eventq_index=0 455opClass=SimdFloatMultAcc 456opLat=1 457pipelined=true 458 459[system.cpu.fuPool.FUList5.opList19] 460type=OpDesc 461eventq_index=0 462opClass=SimdFloatSqrt 463opLat=1 464pipelined=true 465 466[system.cpu.fuPool.FUList6] 467type=FUDesc 468children=opList 469count=0 470eventq_index=0 471opList=system.cpu.fuPool.FUList6.opList 472 473[system.cpu.fuPool.FUList6.opList] 474type=OpDesc 475eventq_index=0 476opClass=MemWrite 477opLat=1 478pipelined=true 479 480[system.cpu.fuPool.FUList7] 481type=FUDesc 482children=opList0 opList1 483count=4 484eventq_index=0 485opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 486 487[system.cpu.fuPool.FUList7.opList0] 488type=OpDesc 489eventq_index=0 490opClass=MemRead 491opLat=1 492pipelined=true 493 494[system.cpu.fuPool.FUList7.opList1] 495type=OpDesc 496eventq_index=0 497opClass=MemWrite 498opLat=1 499pipelined=true 500 501[system.cpu.fuPool.FUList8] 502type=FUDesc 503children=opList 504count=1 505eventq_index=0 506opList=system.cpu.fuPool.FUList8.opList 507 508[system.cpu.fuPool.FUList8.opList] 509type=OpDesc 510eventq_index=0 511opClass=IprAccess 512opLat=3 513pipelined=false 514 515[system.cpu.icache] 516type=Cache 517children=tags 518addr_ranges=0:18446744073709551615 519assoc=2 520clk_domain=system.cpu_clk_domain	183cpu_side=system.cpu.dcache_port 184mem_side=system.cpu.toL2Bus.slave[1] 185 186[system.cpu.dcache.tags] 187type=LRU 188assoc=2 189block_size=64 190clk_domain=system.cpu_clk_domain 191eventq_index=0 192hit_latency=2 193sequential_access=false 194size=262144 195 196[system.cpu.dtb] 197type=X86TLB 198children=walker 199eventq_index=0 200size=64 201walker=system.cpu.dtb.walker 202 203[system.cpu.dtb.walker] 204type=X86PagetableWalker 205clk_domain=system.cpu_clk_domain 206eventq_index=0 207num_squash_per_cycle=4 208system=system 209port=system.cpu.toL2Bus.slave[3] 210 211[system.cpu.fuPool] 212type=FUPool 213children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 214FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 215eventq_index=0 216 217[system.cpu.fuPool.FUList0] 218type=FUDesc 219children=opList 220count=6 221eventq_index=0 222opList=system.cpu.fuPool.FUList0.opList 223 224[system.cpu.fuPool.FUList0.opList] 225type=OpDesc 226eventq_index=0 227opClass=IntAlu 228opLat=1 229pipelined=true 230 231[system.cpu.fuPool.FUList1] 232type=FUDesc 233children=opList0 opList1 234count=2 235eventq_index=0 236opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 237 238[system.cpu.fuPool.FUList1.opList0] 239type=OpDesc 240eventq_index=0 241opClass=IntMult 242opLat=3 243pipelined=true 244 245[system.cpu.fuPool.FUList1.opList1] 246type=OpDesc 247eventq_index=0 248opClass=IntDiv 249opLat=1 250pipelined=false 251 252[system.cpu.fuPool.FUList2] 253type=FUDesc 254children=opList0 opList1 opList2 255count=4 256eventq_index=0 257opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 258 259[system.cpu.fuPool.FUList2.opList0] 260type=OpDesc 261eventq_index=0 262opClass=FloatAdd 263opLat=2 264pipelined=true 265 266[system.cpu.fuPool.FUList2.opList1] 267type=OpDesc 268eventq_index=0 269opClass=FloatCmp 270opLat=2 271pipelined=true 272 273[system.cpu.fuPool.FUList2.opList2] 274type=OpDesc 275eventq_index=0 276opClass=FloatCvt 277opLat=2 278pipelined=true 279 280[system.cpu.fuPool.FUList3] 281type=FUDesc 282children=opList0 opList1 opList2 283count=2 284eventq_index=0 285opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 286 287[system.cpu.fuPool.FUList3.opList0] 288type=OpDesc 289eventq_index=0 290opClass=FloatMult 291opLat=4 292pipelined=true 293 294[system.cpu.fuPool.FUList3.opList1] 295type=OpDesc 296eventq_index=0 297opClass=FloatDiv 298opLat=12 299pipelined=false 300 301[system.cpu.fuPool.FUList3.opList2] 302type=OpDesc 303eventq_index=0 304opClass=FloatSqrt 305opLat=24 306pipelined=false 307 308[system.cpu.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312eventq_index=0 313opList=system.cpu.fuPool.FUList4.opList 314 315[system.cpu.fuPool.FUList4.opList] 316type=OpDesc 317eventq_index=0 318opClass=MemRead 319opLat=1 320pipelined=true 321 322[system.cpu.fuPool.FUList5] 323type=FUDesc 324children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 325count=4 326eventq_index=0 327opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 328 329[system.cpu.fuPool.FUList5.opList00] 330type=OpDesc 331eventq_index=0 332opClass=SimdAdd 333opLat=1 334pipelined=true 335 336[system.cpu.fuPool.FUList5.opList01] 337type=OpDesc 338eventq_index=0 339opClass=SimdAddAcc 340opLat=1 341pipelined=true 342 343[system.cpu.fuPool.FUList5.opList02] 344type=OpDesc 345eventq_index=0 346opClass=SimdAlu 347opLat=1 348pipelined=true 349 350[system.cpu.fuPool.FUList5.opList03] 351type=OpDesc 352eventq_index=0 353opClass=SimdCmp 354opLat=1 355pipelined=true 356 357[system.cpu.fuPool.FUList5.opList04] 358type=OpDesc 359eventq_index=0 360opClass=SimdCvt 361opLat=1 362pipelined=true 363 364[system.cpu.fuPool.FUList5.opList05] 365type=OpDesc 366eventq_index=0 367opClass=SimdMisc 368opLat=1 369pipelined=true 370 371[system.cpu.fuPool.FUList5.opList06] 372type=OpDesc 373eventq_index=0 374opClass=SimdMult 375opLat=1 376pipelined=true 377 378[system.cpu.fuPool.FUList5.opList07] 379type=OpDesc 380eventq_index=0 381opClass=SimdMultAcc 382opLat=1 383pipelined=true 384 385[system.cpu.fuPool.FUList5.opList08] 386type=OpDesc 387eventq_index=0 388opClass=SimdShift 389opLat=1 390pipelined=true 391 392[system.cpu.fuPool.FUList5.opList09] 393type=OpDesc 394eventq_index=0 395opClass=SimdShiftAcc 396opLat=1 397pipelined=true 398 399[system.cpu.fuPool.FUList5.opList10] 400type=OpDesc 401eventq_index=0 402opClass=SimdSqrt 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList5.opList11] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAdd 410opLat=1 411pipelined=true 412 413[system.cpu.fuPool.FUList5.opList12] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatAlu 417opLat=1 418pipelined=true 419 420[system.cpu.fuPool.FUList5.opList13] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCmp 424opLat=1 425pipelined=true 426 427[system.cpu.fuPool.FUList5.opList14] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatCvt 431opLat=1 432pipelined=true 433 434[system.cpu.fuPool.FUList5.opList15] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatDiv 438opLat=1 439pipelined=true 440 441[system.cpu.fuPool.FUList5.opList16] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMisc 445opLat=1 446pipelined=true 447 448[system.cpu.fuPool.FUList5.opList17] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMult 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList5.opList18] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatMultAcc 459opLat=1 460pipelined=true 461 462[system.cpu.fuPool.FUList5.opList19] 463type=OpDesc 464eventq_index=0 465opClass=SimdFloatSqrt 466opLat=1 467pipelined=true 468 469[system.cpu.fuPool.FUList6] 470type=FUDesc 471children=opList 472count=0 473eventq_index=0 474opList=system.cpu.fuPool.FUList6.opList 475 476[system.cpu.fuPool.FUList6.opList] 477type=OpDesc 478eventq_index=0 479opClass=MemWrite 480opLat=1 481pipelined=true 482 483[system.cpu.fuPool.FUList7] 484type=FUDesc 485children=opList0 opList1 486count=4 487eventq_index=0 488opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 489 490[system.cpu.fuPool.FUList7.opList0] 491type=OpDesc 492eventq_index=0 493opClass=MemRead 494opLat=1 495pipelined=true 496 497[system.cpu.fuPool.FUList7.opList1] 498type=OpDesc 499eventq_index=0 500opClass=MemWrite 501opLat=1 502pipelined=true 503 504[system.cpu.fuPool.FUList8] 505type=FUDesc 506children=opList 507count=1 508eventq_index=0 509opList=system.cpu.fuPool.FUList8.opList 510 511[system.cpu.fuPool.FUList8.opList] 512type=OpDesc 513eventq_index=0 514opClass=IprAccess 515opLat=3 516pipelined=false 517 518[system.cpu.icache] 519type=Cache 520children=tags 521addr_ranges=0:18446744073709551615 522assoc=2 523clk_domain=system.cpu_clk_domain
	524clusivity=mostly_incl
521demand_mshr_reserve=1 522eventq_index=0	525demand_mshr_reserve=1 526eventq_index=0
523forward_snoops=true
524hit_latency=2 525is_read_only=true 526max_miss_count=0 527mshrs=4 528prefetch_on_access=false 529prefetcher=Null 530response_latency=2 531sequential_access=false 532size=131072 533system=system 534tags=system.cpu.icache.tags 535tgts_per_mshr=20 536write_buffers=8	527hit_latency=2 528is_read_only=true 529max_miss_count=0 530mshrs=4 531prefetch_on_access=false 532prefetcher=Null 533response_latency=2 534sequential_access=false 535size=131072 536system=system 537tags=system.cpu.icache.tags 538tgts_per_mshr=20 539write_buffers=8
	540writeback_clean=true
537cpu_side=system.cpu.icache_port 538mem_side=system.cpu.toL2Bus.slave[0] 539 540[system.cpu.icache.tags] 541type=LRU 542assoc=2 543block_size=64 544clk_domain=system.cpu_clk_domain 545eventq_index=0 546hit_latency=2 547sequential_access=false 548size=131072 549 550[system.cpu.interrupts] 551type=X86LocalApic 552clk_domain=system.cpu.apic_clk_domain 553eventq_index=0 554int_latency=1000 555pio_addr=2305843009213693952 556pio_latency=100000 557system=system 558int_master=system.membus.slave[2] 559int_slave=system.membus.master[2] 560pio=system.membus.master[1] 561 562[system.cpu.isa] 563type=X86ISA 564eventq_index=0 565 566[system.cpu.itb] 567type=X86TLB 568children=walker 569eventq_index=0 570size=64 571walker=system.cpu.itb.walker 572 573[system.cpu.itb.walker] 574type=X86PagetableWalker 575clk_domain=system.cpu_clk_domain 576eventq_index=0 577num_squash_per_cycle=4 578system=system 579port=system.cpu.toL2Bus.slave[2] 580 581[system.cpu.l2cache] 582type=Cache 583children=tags 584addr_ranges=0:18446744073709551615 585assoc=8 586clk_domain=system.cpu_clk_domain	541cpu_side=system.cpu.icache_port 542mem_side=system.cpu.toL2Bus.slave[0] 543 544[system.cpu.icache.tags] 545type=LRU 546assoc=2 547block_size=64 548clk_domain=system.cpu_clk_domain 549eventq_index=0 550hit_latency=2 551sequential_access=false 552size=131072 553 554[system.cpu.interrupts] 555type=X86LocalApic 556clk_domain=system.cpu.apic_clk_domain 557eventq_index=0 558int_latency=1000 559pio_addr=2305843009213693952 560pio_latency=100000 561system=system 562int_master=system.membus.slave[2] 563int_slave=system.membus.master[2] 564pio=system.membus.master[1] 565 566[system.cpu.isa] 567type=X86ISA 568eventq_index=0 569 570[system.cpu.itb] 571type=X86TLB 572children=walker 573eventq_index=0 574size=64 575walker=system.cpu.itb.walker 576 577[system.cpu.itb.walker] 578type=X86PagetableWalker 579clk_domain=system.cpu_clk_domain 580eventq_index=0 581num_squash_per_cycle=4 582system=system 583port=system.cpu.toL2Bus.slave[2] 584 585[system.cpu.l2cache] 586type=Cache 587children=tags 588addr_ranges=0:18446744073709551615 589assoc=8 590clk_domain=system.cpu_clk_domain
	591clusivity=mostly_incl
587demand_mshr_reserve=1 588eventq_index=0	592demand_mshr_reserve=1 593eventq_index=0
589forward_snoops=true
590hit_latency=20 591is_read_only=false 592max_miss_count=0 593mshrs=20 594prefetch_on_access=false 595prefetcher=Null 596response_latency=20 597sequential_access=false 598size=2097152 599system=system 600tags=system.cpu.l2cache.tags 601tgts_per_mshr=12 602write_buffers=8	594hit_latency=20 595is_read_only=false 596max_miss_count=0 597mshrs=20 598prefetch_on_access=false 599prefetcher=Null 600response_latency=20 601sequential_access=false 602size=2097152 603system=system 604tags=system.cpu.l2cache.tags 605tgts_per_mshr=12 606write_buffers=8
	607writeback_clean=false
603cpu_side=system.cpu.toL2Bus.master[0] 604mem_side=system.membus.slave[1] 605 606[system.cpu.l2cache.tags] 607type=LRU 608assoc=8 609block_size=64 610clk_domain=system.cpu_clk_domain 611eventq_index=0 612hit_latency=20 613sequential_access=false 614size=2097152 615 616[system.cpu.toL2Bus] 617type=CoherentXBar	608cpu_side=system.cpu.toL2Bus.master[0] 609mem_side=system.membus.slave[1] 610 611[system.cpu.l2cache.tags] 612type=LRU 613assoc=8 614block_size=64 615clk_domain=system.cpu_clk_domain 616eventq_index=0 617hit_latency=20 618sequential_access=false 619size=2097152 620 621[system.cpu.toL2Bus] 622type=CoherentXBar
	623children=snoop_filter
618clk_domain=system.cpu_clk_domain 619eventq_index=0 620forward_latency=0 621frontend_latency=1	624clk_domain=system.cpu_clk_domain 625eventq_index=0 626forward_latency=0 627frontend_latency=1
	628point_of_coherency=false
622response_latency=1	629response_latency=1
623snoop_filter=Null	630snoop_filter=system.cpu.toL2Bus.snoop_filter
624snoop_response_latency=1 625system=system 626use_default_range=false 627width=32 628master=system.cpu.l2cache.cpu_side 629slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 630	631snoop_response_latency=1 632system=system 633use_default_range=false 634width=32 635master=system.cpu.l2cache.cpu_side 636slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 637
	638[system.cpu.toL2Bus.snoop_filter] 639type=SnoopFilter 640eventq_index=0 641lookup_latency=0 642max_capacity=8388608 643system=system 644
631[system.cpu.tracer] 632type=ExeTracer 633eventq_index=0 634 635[system.cpu.workload] 636type=LiveProcess 637cmd=mcf mcf.in 638cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 639drivers= 640egid=100 641env= 642errout=cerr 643euid=100 644eventq_index=0	645[system.cpu.tracer] 646type=ExeTracer 647eventq_index=0 648 649[system.cpu.workload] 650type=LiveProcess 651cmd=mcf mcf.in 652cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 653drivers= 654egid=100 655env= 656errout=cerr 657euid=100 658eventq_index=0
645executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf	659executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
646gid=100	660gid=100
647input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in	661input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
648kvmInSE=false 649max_stack_size=67108864 650output=cout 651pid=100 652ppid=99 653simpoint=55300000000 654system=system 655uid=100 656useArchPT=false 657 658[system.cpu_clk_domain] 659type=SrcClockDomain 660clock=500 661domain_id=-1 662eventq_index=0 663init_perf_level=0 664voltage_domain=system.voltage_domain 665 666[system.dvfs_handler] 667type=DVFSHandler 668domains= 669enable=false 670eventq_index=0 671sys_clk_domain=system.clk_domain 672transition_latency=100000000 673 674[system.membus] 675type=CoherentXBar 676clk_domain=system.clk_domain 677eventq_index=0 678forward_latency=4 679frontend_latency=3	662kvmInSE=false 663max_stack_size=67108864 664output=cout 665pid=100 666ppid=99 667simpoint=55300000000 668system=system 669uid=100 670useArchPT=false 671 672[system.cpu_clk_domain] 673type=SrcClockDomain 674clock=500 675domain_id=-1 676eventq_index=0 677init_perf_level=0 678voltage_domain=system.voltage_domain 679 680[system.dvfs_handler] 681type=DVFSHandler 682domains= 683enable=false 684eventq_index=0 685sys_clk_domain=system.clk_domain 686transition_latency=100000000 687 688[system.membus] 689type=CoherentXBar 690clk_domain=system.clk_domain 691eventq_index=0 692forward_latency=4 693frontend_latency=3
	694point_of_coherency=true
680response_latency=2 681snoop_filter=Null 682snoop_response_latency=4 683system=system 684use_default_range=false 685width=16 686master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 687slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 688 689[system.physmem] 690type=DRAMCtrl 691IDD0=0.075000 692IDD02=0.000000 693IDD2N=0.050000 694IDD2N2=0.000000 695IDD2P0=0.000000 696IDD2P02=0.000000 697IDD2P1=0.000000 698IDD2P12=0.000000 699IDD3N=0.057000 700IDD3N2=0.000000 701IDD3P0=0.000000 702IDD3P02=0.000000 703IDD3P1=0.000000 704IDD3P12=0.000000 705IDD4R=0.187000 706IDD4R2=0.000000 707IDD4W=0.165000 708IDD4W2=0.000000 709IDD5=0.220000 710IDD52=0.000000 711IDD6=0.000000 712IDD62=0.000000 713VDD=1.500000 714VDD2=0.000000 715activation_limit=4 716addr_mapping=RoRaBaCoCh 717bank_groups_per_rank=0 718banks_per_rank=8 719burst_length=8 720channels=1 721clk_domain=system.clk_domain 722conf_table_reported=true 723device_bus_width=8 724device_rowbuffer_size=1024 725device_size=536870912 726devices_per_rank=8 727dll=true 728eventq_index=0 729in_addr_map=true 730max_accesses_per_row=16 731mem_sched_policy=frfcfs 732min_writes_per_switch=16 733null=false 734page_policy=open_adaptive 735range=0:268435455 736ranks_per_channel=2 737read_buffer_size=32 738static_backend_latency=10000 739static_frontend_latency=10000 740tBURST=5000 741tCCD_L=0 742tCK=1250 743tCL=13750 744tCS=2500 745tRAS=35000 746tRCD=13750 747tREFI=7800000 748tRFC=260000 749tRP=13750 750tRRD=6000 751tRRD_L=0 752tRTP=7500 753tRTW=2500 754tWR=15000 755tWTR=7500 756tXAW=30000 757tXP=0 758tXPDLL=0 759tXS=0 760tXSDLL=0 761write_buffer_size=64 762write_high_thresh_perc=85 763write_low_thresh_perc=50 764port=system.membus.master[0] 765 766[system.voltage_domain] 767type=VoltageDomain 768eventq_index=0 769voltage=1.000000 770	695response_latency=2 696snoop_filter=Null 697snoop_response_latency=4 698system=system 699use_default_range=false 700width=16 701master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 702slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 703 704[system.physmem] 705type=DRAMCtrl 706IDD0=0.075000 707IDD02=0.000000 708IDD2N=0.050000 709IDD2N2=0.000000 710IDD2P0=0.000000 711IDD2P02=0.000000 712IDD2P1=0.000000 713IDD2P12=0.000000 714IDD3N=0.057000 715IDD3N2=0.000000 716IDD3P0=0.000000 717IDD3P02=0.000000 718IDD3P1=0.000000 719IDD3P12=0.000000 720IDD4R=0.187000 721IDD4R2=0.000000 722IDD4W=0.165000 723IDD4W2=0.000000 724IDD5=0.220000 725IDD52=0.000000 726IDD6=0.000000 727IDD62=0.000000 728VDD=1.500000 729VDD2=0.000000 730activation_limit=4 731addr_mapping=RoRaBaCoCh 732bank_groups_per_rank=0 733banks_per_rank=8 734burst_length=8 735channels=1 736clk_domain=system.clk_domain 737conf_table_reported=true 738device_bus_width=8 739device_rowbuffer_size=1024 740device_size=536870912 741devices_per_rank=8 742dll=true 743eventq_index=0 744in_addr_map=true 745max_accesses_per_row=16 746mem_sched_policy=frfcfs 747min_writes_per_switch=16 748null=false 749page_policy=open_adaptive 750range=0:268435455 751ranks_per_channel=2 752read_buffer_size=32 753static_backend_latency=10000 754static_frontend_latency=10000 755tBURST=5000 756tCCD_L=0 757tCK=1250 758tCL=13750 759tCS=2500 760tRAS=35000 761tRCD=13750 762tREFI=7800000 763tRFC=260000 764tRP=13750 765tRRD=6000 766tRRD_L=0 767tRTP=7500 768tRTW=2500 769tWR=15000 770tWTR=7500 771tXAW=30000 772tXP=0 773tXPDLL=0 774tXS=0 775tXSDLL=0 776write_buffer_size=64 777write_high_thresh_perc=85 778write_low_thresh_perc=50 779port=system.membus.master[0] 780 781[system.voltage_domain] 782type=VoltageDomain 783eventq_index=0 784voltage=1.000000 785