1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
12boot_osflags=a
13cache_line_size=64
14clk_domain=system.clk_domain
15init_param=0
16kernel=
17load_addr_mask=1099511627775
18mem_mode=timing
19mem_ranges=
20memories=system.physmem
21num_work_ids=16
22readfile=
--- 5 unchanged lines hidden (view full) ---
28work_end_ckpt_count=0
29work_end_exit_count=0
30work_item_id=-1
31system_port=system.membus.slave[0]
32
33[system.clk_domain]
34type=SrcClockDomain
35clock=1000
36voltage_domain=system.voltage_domain
37
38[system.cpu]
39type=DerivO3CPU
40children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
41LFSTSize=1024
42LQEntries=32
43LSQCheckLoads=true
--- 15 unchanged lines hidden (view full) ---
59decodeToFetchDelay=1
60decodeToRenameDelay=1
61decodeWidth=8
62dispatchWidth=8
63do_checkpoint_insts=true
64do_quiesce=true
65do_statistics_insts=true
66dtb=system.cpu.dtb
67fetchToDecodeDelay=1
68fetchTrapLatency=1
69fetchWidth=8
70forwardComSize=5
71fuPool=system.cpu.fuPool
72function_trace=false
73function_trace_start=0
74iewToCommitDelay=1
--- 45 unchanged lines hidden (view full) ---
120workload=system.cpu.workload
121dcache_port=system.cpu.dcache.cpu_side
122icache_port=system.cpu.icache.cpu_side
123
124[system.cpu.apic_clk_domain]
125type=DerivedClockDomain
126clk_divider=16
127clk_domain=system.cpu_clk_domain
128
129[system.cpu.branchPred]
130type=BranchPredictor
131BTBEntries=4096
132BTBTagSize=16
133RASSize=16
134choiceCtrBits=2
135choicePredictorSize=8192
136globalCtrBits=2
137globalPredictorSize=8192
138instShiftAmt=2
139localCtrBits=2
140localHistoryTableSize=2048
141localPredictorSize=2048
142numThreads=1
143predType=tournament
144
145[system.cpu.dcache]
146type=BaseCache
147children=tags
148addr_ranges=0:18446744073709551615
149assoc=2
150clk_domain=system.cpu_clk_domain
151forward_snoops=true
152hit_latency=2
153is_top_level=true
154max_miss_count=0
155mshrs=4
156prefetch_on_access=false
157prefetcher=Null
158response_latency=2
--- 6 unchanged lines hidden (view full) ---
165cpu_side=system.cpu.dcache_port
166mem_side=system.cpu.toL2Bus.slave[1]
167
168[system.cpu.dcache.tags]
169type=LRU
170assoc=2
171block_size=64
172clk_domain=system.cpu_clk_domain
173hit_latency=2
174size=262144
175
176[system.cpu.dtb]
177type=X86TLB
178children=walker
179size=64
180walker=system.cpu.dtb.walker
181
182[system.cpu.dtb.walker]
183type=X86PagetableWalker
184clk_domain=system.cpu_clk_domain
185num_squash_per_cycle=4
186system=system
187port=system.cpu.toL2Bus.slave[3]
188
189[system.cpu.fuPool]
190type=FUPool
191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
192FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
193
194[system.cpu.fuPool.FUList0]
195type=FUDesc
196children=opList
197count=6
198opList=system.cpu.fuPool.FUList0.opList
199
200[system.cpu.fuPool.FUList0.opList]
201type=OpDesc
202issueLat=1
203opClass=IntAlu
204opLat=1
205
206[system.cpu.fuPool.FUList1]
207type=FUDesc
208children=opList0 opList1
209count=2
210opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
211
212[system.cpu.fuPool.FUList1.opList0]
213type=OpDesc
214issueLat=1
215opClass=IntMult
216opLat=3
217
218[system.cpu.fuPool.FUList1.opList1]
219type=OpDesc
220issueLat=19
221opClass=IntDiv
222opLat=20
223
224[system.cpu.fuPool.FUList2]
225type=FUDesc
226children=opList0 opList1 opList2
227count=4
228opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
229
230[system.cpu.fuPool.FUList2.opList0]
231type=OpDesc
232issueLat=1
233opClass=FloatAdd
234opLat=2
235
236[system.cpu.fuPool.FUList2.opList1]
237type=OpDesc
238issueLat=1
239opClass=FloatCmp
240opLat=2
241
242[system.cpu.fuPool.FUList2.opList2]
243type=OpDesc
244issueLat=1
245opClass=FloatCvt
246opLat=2
247
248[system.cpu.fuPool.FUList3]
249type=FUDesc
250children=opList0 opList1 opList2
251count=2
252opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
253
254[system.cpu.fuPool.FUList3.opList0]
255type=OpDesc
256issueLat=1
257opClass=FloatMult
258opLat=4
259
260[system.cpu.fuPool.FUList3.opList1]
261type=OpDesc
262issueLat=12
263opClass=FloatDiv
264opLat=12
265
266[system.cpu.fuPool.FUList3.opList2]
267type=OpDesc
268issueLat=24
269opClass=FloatSqrt
270opLat=24
271
272[system.cpu.fuPool.FUList4]
273type=FUDesc
274children=opList
275count=0
276opList=system.cpu.fuPool.FUList4.opList
277
278[system.cpu.fuPool.FUList4.opList]
279type=OpDesc
280issueLat=1
281opClass=MemRead
282opLat=1
283
284[system.cpu.fuPool.FUList5]
285type=FUDesc
286children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
287count=4
288opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
289
290[system.cpu.fuPool.FUList5.opList00]
291type=OpDesc
292issueLat=1
293opClass=SimdAdd
294opLat=1
295
296[system.cpu.fuPool.FUList5.opList01]
297type=OpDesc
298issueLat=1
299opClass=SimdAddAcc
300opLat=1
301
302[system.cpu.fuPool.FUList5.opList02]
303type=OpDesc
304issueLat=1
305opClass=SimdAlu
306opLat=1
307
308[system.cpu.fuPool.FUList5.opList03]
309type=OpDesc
310issueLat=1
311opClass=SimdCmp
312opLat=1
313
314[system.cpu.fuPool.FUList5.opList04]
315type=OpDesc
316issueLat=1
317opClass=SimdCvt
318opLat=1
319
320[system.cpu.fuPool.FUList5.opList05]
321type=OpDesc
322issueLat=1
323opClass=SimdMisc
324opLat=1
325
326[system.cpu.fuPool.FUList5.opList06]
327type=OpDesc
328issueLat=1
329opClass=SimdMult
330opLat=1
331
332[system.cpu.fuPool.FUList5.opList07]
333type=OpDesc
334issueLat=1
335opClass=SimdMultAcc
336opLat=1
337
338[system.cpu.fuPool.FUList5.opList08]
339type=OpDesc
340issueLat=1
341opClass=SimdShift
342opLat=1
343
344[system.cpu.fuPool.FUList5.opList09]
345type=OpDesc
346issueLat=1
347opClass=SimdShiftAcc
348opLat=1
349
350[system.cpu.fuPool.FUList5.opList10]
351type=OpDesc
352issueLat=1
353opClass=SimdSqrt
354opLat=1
355
356[system.cpu.fuPool.FUList5.opList11]
357type=OpDesc
358issueLat=1
359opClass=SimdFloatAdd
360opLat=1
361
362[system.cpu.fuPool.FUList5.opList12]
363type=OpDesc
364issueLat=1
365opClass=SimdFloatAlu
366opLat=1
367
368[system.cpu.fuPool.FUList5.opList13]
369type=OpDesc
370issueLat=1
371opClass=SimdFloatCmp
372opLat=1
373
374[system.cpu.fuPool.FUList5.opList14]
375type=OpDesc
376issueLat=1
377opClass=SimdFloatCvt
378opLat=1
379
380[system.cpu.fuPool.FUList5.opList15]
381type=OpDesc
382issueLat=1
383opClass=SimdFloatDiv
384opLat=1
385
386[system.cpu.fuPool.FUList5.opList16]
387type=OpDesc
388issueLat=1
389opClass=SimdFloatMisc
390opLat=1
391
392[system.cpu.fuPool.FUList5.opList17]
393type=OpDesc
394issueLat=1
395opClass=SimdFloatMult
396opLat=1
397
398[system.cpu.fuPool.FUList5.opList18]
399type=OpDesc
400issueLat=1
401opClass=SimdFloatMultAcc
402opLat=1
403
404[system.cpu.fuPool.FUList5.opList19]
405type=OpDesc
406issueLat=1
407opClass=SimdFloatSqrt
408opLat=1
409
410[system.cpu.fuPool.FUList6]
411type=FUDesc
412children=opList
413count=0
414opList=system.cpu.fuPool.FUList6.opList
415
416[system.cpu.fuPool.FUList6.opList]
417type=OpDesc
418issueLat=1
419opClass=MemWrite
420opLat=1
421
422[system.cpu.fuPool.FUList7]
423type=FUDesc
424children=opList0 opList1
425count=4
426opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
427
428[system.cpu.fuPool.FUList7.opList0]
429type=OpDesc
430issueLat=1
431opClass=MemRead
432opLat=1
433
434[system.cpu.fuPool.FUList7.opList1]
435type=OpDesc
436issueLat=1
437opClass=MemWrite
438opLat=1
439
440[system.cpu.fuPool.FUList8]
441type=FUDesc
442children=opList
443count=1
444opList=system.cpu.fuPool.FUList8.opList
445
446[system.cpu.fuPool.FUList8.opList]
447type=OpDesc
448issueLat=3
449opClass=IprAccess
450opLat=3
451
452[system.cpu.icache]
453type=BaseCache
454children=tags
455addr_ranges=0:18446744073709551615
456assoc=2
457clk_domain=system.cpu_clk_domain
458forward_snoops=true
459hit_latency=2
460is_top_level=true
461max_miss_count=0
462mshrs=4
463prefetch_on_access=false
464prefetcher=Null
465response_latency=2
--- 6 unchanged lines hidden (view full) ---
472cpu_side=system.cpu.icache_port
473mem_side=system.cpu.toL2Bus.slave[0]
474
475[system.cpu.icache.tags]
476type=LRU
477assoc=2
478block_size=64
479clk_domain=system.cpu_clk_domain
480hit_latency=2
481size=131072
482
483[system.cpu.interrupts]
484type=X86LocalApic
485clk_domain=system.cpu.apic_clk_domain
486int_latency=1000
487pio_addr=2305843009213693952
488pio_latency=100000
489system=system
490int_master=system.membus.slave[2]
491int_slave=system.membus.master[2]
492pio=system.membus.master[1]
493
494[system.cpu.isa]
495type=X86ISA
496
497[system.cpu.itb]
498type=X86TLB
499children=walker
500size=64
501walker=system.cpu.itb.walker
502
503[system.cpu.itb.walker]
504type=X86PagetableWalker
505clk_domain=system.cpu_clk_domain
506num_squash_per_cycle=4
507system=system
508port=system.cpu.toL2Bus.slave[2]
509
510[system.cpu.l2cache]
511type=BaseCache
512children=tags
513addr_ranges=0:18446744073709551615
514assoc=8
515clk_domain=system.cpu_clk_domain
516forward_snoops=true
517hit_latency=20
518is_top_level=false
519max_miss_count=0
520mshrs=20
521prefetch_on_access=false
522prefetcher=Null
523response_latency=20
--- 6 unchanged lines hidden (view full) ---
530cpu_side=system.cpu.toL2Bus.master[0]
531mem_side=system.membus.slave[1]
532
533[system.cpu.l2cache.tags]
534type=LRU
535assoc=8
536block_size=64
537clk_domain=system.cpu_clk_domain
538hit_latency=20
539size=2097152
540
541[system.cpu.toL2Bus]
542type=CoherentBus
543clk_domain=system.cpu_clk_domain
544header_cycles=1
545system=system
546use_default_range=false
547width=32
548master=system.cpu.l2cache.cpu_side
549slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
550
551[system.cpu.tracer]
552type=ExeTracer
553
554[system.cpu.workload]
555type=LiveProcess
556cmd=mcf mcf.in
557cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
558egid=100
559env=
560errout=cerr
561euid=100
562executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
563gid=100
564input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
565max_stack_size=67108864
566output=cout
567pid=100
568ppid=99
569simpoint=55300000000
570system=system
571uid=100
572
573[system.cpu_clk_domain]
574type=SrcClockDomain
575clock=500
576voltage_domain=system.voltage_domain
577
578[system.membus]
579type=CoherentBus
580clk_domain=system.clk_domain
581header_cycles=1
582system=system
583use_default_range=false
584width=8
585master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
586slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
587
588[system.physmem]
589type=SimpleDRAM
590activation_limit=4
591addr_mapping=RaBaChCo
592banks_per_rank=8
593burst_length=8
594channels=1
595clk_domain=system.clk_domain
596conf_table_reported=true
597device_bus_width=8
598device_rowbuffer_size=1024
599devices_per_rank=8
600in_addr_map=true
601mem_sched_policy=frfcfs
602null=false
603page_policy=open
604range=0:268435455
605ranks_per_channel=2
606read_buffer_size=32
607static_backend_latency=10000
608static_frontend_latency=10000
609tBURST=5000
610tCL=13750
611tRCD=13750
612tREFI=7800000
613tRFC=300000
614tRP=13750
615tWTR=7500
616tXAW=40000
617write_buffer_size=32
618write_thresh_perc=70
619port=system.membus.master[0]
620
621[system.voltage_domain]
622type=VoltageDomain
623voltage=1.000000
624
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
12boot_osflags=a
13cache_line_size=64
14clk_domain=system.clk_domain
15init_param=0
16kernel=
17load_addr_mask=1099511627775
18mem_mode=timing
19mem_ranges=
20memories=system.physmem
21num_work_ids=16
22readfile=
--- 5 unchanged lines hidden (view full) ---
28work_end_ckpt_count=0
29work_end_exit_count=0
30work_item_id=-1
31system_port=system.membus.slave[0]
32
33[system.clk_domain]
34type=SrcClockDomain
35clock=1000
36voltage_domain=system.voltage_domain
37
38[system.cpu]
39type=DerivO3CPU
40children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
41LFSTSize=1024
42LQEntries=32
43LSQCheckLoads=true
--- 15 unchanged lines hidden (view full) ---
59decodeToFetchDelay=1
60decodeToRenameDelay=1
61decodeWidth=8
62dispatchWidth=8
63do_checkpoint_insts=true
64do_quiesce=true
65do_statistics_insts=true
66dtb=system.cpu.dtb
67fetchToDecodeDelay=1
68fetchTrapLatency=1
69fetchWidth=8
70forwardComSize=5
71fuPool=system.cpu.fuPool
72function_trace=false
73function_trace_start=0
74iewToCommitDelay=1
--- 45 unchanged lines hidden (view full) ---
120workload=system.cpu.workload
121dcache_port=system.cpu.dcache.cpu_side
122icache_port=system.cpu.icache.cpu_side
123
124[system.cpu.apic_clk_domain]
125type=DerivedClockDomain
126clk_divider=16
127clk_domain=system.cpu_clk_domain
128
129[system.cpu.branchPred]
130type=BranchPredictor
131BTBEntries=4096
132BTBTagSize=16
133RASSize=16
134choiceCtrBits=2
135choicePredictorSize=8192
136globalCtrBits=2
137globalPredictorSize=8192
138instShiftAmt=2
139localCtrBits=2
140localHistoryTableSize=2048
141localPredictorSize=2048
142numThreads=1
143predType=tournament
144
145[system.cpu.dcache]
146type=BaseCache
147children=tags
148addr_ranges=0:18446744073709551615
149assoc=2
150clk_domain=system.cpu_clk_domain
151forward_snoops=true
152hit_latency=2
153is_top_level=true
154max_miss_count=0
155mshrs=4
156prefetch_on_access=false
157prefetcher=Null
158response_latency=2
--- 6 unchanged lines hidden (view full) ---
165cpu_side=system.cpu.dcache_port
166mem_side=system.cpu.toL2Bus.slave[1]
167
168[system.cpu.dcache.tags]
169type=LRU
170assoc=2
171block_size=64
172clk_domain=system.cpu_clk_domain
173hit_latency=2
174size=262144
175
176[system.cpu.dtb]
177type=X86TLB
178children=walker
179size=64
180walker=system.cpu.dtb.walker
181
182[system.cpu.dtb.walker]
183type=X86PagetableWalker
184clk_domain=system.cpu_clk_domain
185num_squash_per_cycle=4
186system=system
187port=system.cpu.toL2Bus.slave[3]
188
189[system.cpu.fuPool]
190type=FUPool
191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
192FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
193
194[system.cpu.fuPool.FUList0]
195type=FUDesc
196children=opList
197count=6
198opList=system.cpu.fuPool.FUList0.opList
199
200[system.cpu.fuPool.FUList0.opList]
201type=OpDesc
202issueLat=1
203opClass=IntAlu
204opLat=1
205
206[system.cpu.fuPool.FUList1]
207type=FUDesc
208children=opList0 opList1
209count=2
210opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
211
212[system.cpu.fuPool.FUList1.opList0]
213type=OpDesc
214issueLat=1
215opClass=IntMult
216opLat=3
217
218[system.cpu.fuPool.FUList1.opList1]
219type=OpDesc
220issueLat=19
221opClass=IntDiv
222opLat=20
223
224[system.cpu.fuPool.FUList2]
225type=FUDesc
226children=opList0 opList1 opList2
227count=4
228opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
229
230[system.cpu.fuPool.FUList2.opList0]
231type=OpDesc
232issueLat=1
233opClass=FloatAdd
234opLat=2
235
236[system.cpu.fuPool.FUList2.opList1]
237type=OpDesc
238issueLat=1
239opClass=FloatCmp
240opLat=2
241
242[system.cpu.fuPool.FUList2.opList2]
243type=OpDesc
244issueLat=1
245opClass=FloatCvt
246opLat=2
247
248[system.cpu.fuPool.FUList3]
249type=FUDesc
250children=opList0 opList1 opList2
251count=2
252opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
253
254[system.cpu.fuPool.FUList3.opList0]
255type=OpDesc
256issueLat=1
257opClass=FloatMult
258opLat=4
259
260[system.cpu.fuPool.FUList3.opList1]
261type=OpDesc
262issueLat=12
263opClass=FloatDiv
264opLat=12
265
266[system.cpu.fuPool.FUList3.opList2]
267type=OpDesc
268issueLat=24
269opClass=FloatSqrt
270opLat=24
271
272[system.cpu.fuPool.FUList4]
273type=FUDesc
274children=opList
275count=0
276opList=system.cpu.fuPool.FUList4.opList
277
278[system.cpu.fuPool.FUList4.opList]
279type=OpDesc
280issueLat=1
281opClass=MemRead
282opLat=1
283
284[system.cpu.fuPool.FUList5]
285type=FUDesc
286children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
287count=4
288opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
289
290[system.cpu.fuPool.FUList5.opList00]
291type=OpDesc
292issueLat=1
293opClass=SimdAdd
294opLat=1
295
296[system.cpu.fuPool.FUList5.opList01]
297type=OpDesc
298issueLat=1
299opClass=SimdAddAcc
300opLat=1
301
302[system.cpu.fuPool.FUList5.opList02]
303type=OpDesc
304issueLat=1
305opClass=SimdAlu
306opLat=1
307
308[system.cpu.fuPool.FUList5.opList03]
309type=OpDesc
310issueLat=1
311opClass=SimdCmp
312opLat=1
313
314[system.cpu.fuPool.FUList5.opList04]
315type=OpDesc
316issueLat=1
317opClass=SimdCvt
318opLat=1
319
320[system.cpu.fuPool.FUList5.opList05]
321type=OpDesc
322issueLat=1
323opClass=SimdMisc
324opLat=1
325
326[system.cpu.fuPool.FUList5.opList06]
327type=OpDesc
328issueLat=1
329opClass=SimdMult
330opLat=1
331
332[system.cpu.fuPool.FUList5.opList07]
333type=OpDesc
334issueLat=1
335opClass=SimdMultAcc
336opLat=1
337
338[system.cpu.fuPool.FUList5.opList08]
339type=OpDesc
340issueLat=1
341opClass=SimdShift
342opLat=1
343
344[system.cpu.fuPool.FUList5.opList09]
345type=OpDesc
346issueLat=1
347opClass=SimdShiftAcc
348opLat=1
349
350[system.cpu.fuPool.FUList5.opList10]
351type=OpDesc
352issueLat=1
353opClass=SimdSqrt
354opLat=1
355
356[system.cpu.fuPool.FUList5.opList11]
357type=OpDesc
358issueLat=1
359opClass=SimdFloatAdd
360opLat=1
361
362[system.cpu.fuPool.FUList5.opList12]
363type=OpDesc
364issueLat=1
365opClass=SimdFloatAlu
366opLat=1
367
368[system.cpu.fuPool.FUList5.opList13]
369type=OpDesc
370issueLat=1
371opClass=SimdFloatCmp
372opLat=1
373
374[system.cpu.fuPool.FUList5.opList14]
375type=OpDesc
376issueLat=1
377opClass=SimdFloatCvt
378opLat=1
379
380[system.cpu.fuPool.FUList5.opList15]
381type=OpDesc
382issueLat=1
383opClass=SimdFloatDiv
384opLat=1
385
386[system.cpu.fuPool.FUList5.opList16]
387type=OpDesc
388issueLat=1
389opClass=SimdFloatMisc
390opLat=1
391
392[system.cpu.fuPool.FUList5.opList17]
393type=OpDesc
394issueLat=1
395opClass=SimdFloatMult
396opLat=1
397
398[system.cpu.fuPool.FUList5.opList18]
399type=OpDesc
400issueLat=1
401opClass=SimdFloatMultAcc
402opLat=1
403
404[system.cpu.fuPool.FUList5.opList19]
405type=OpDesc
406issueLat=1
407opClass=SimdFloatSqrt
408opLat=1
409
410[system.cpu.fuPool.FUList6]
411type=FUDesc
412children=opList
413count=0
414opList=system.cpu.fuPool.FUList6.opList
415
416[system.cpu.fuPool.FUList6.opList]
417type=OpDesc
418issueLat=1
419opClass=MemWrite
420opLat=1
421
422[system.cpu.fuPool.FUList7]
423type=FUDesc
424children=opList0 opList1
425count=4
426opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
427
428[system.cpu.fuPool.FUList7.opList0]
429type=OpDesc
430issueLat=1
431opClass=MemRead
432opLat=1
433
434[system.cpu.fuPool.FUList7.opList1]
435type=OpDesc
436issueLat=1
437opClass=MemWrite
438opLat=1
439
440[system.cpu.fuPool.FUList8]
441type=FUDesc
442children=opList
443count=1
444opList=system.cpu.fuPool.FUList8.opList
445
446[system.cpu.fuPool.FUList8.opList]
447type=OpDesc
448issueLat=3
449opClass=IprAccess
450opLat=3
451
452[system.cpu.icache]
453type=BaseCache
454children=tags
455addr_ranges=0:18446744073709551615
456assoc=2
457clk_domain=system.cpu_clk_domain
458forward_snoops=true
459hit_latency=2
460is_top_level=true
461max_miss_count=0
462mshrs=4
463prefetch_on_access=false
464prefetcher=Null
465response_latency=2
--- 6 unchanged lines hidden (view full) ---
472cpu_side=system.cpu.icache_port
473mem_side=system.cpu.toL2Bus.slave[0]
474
475[system.cpu.icache.tags]
476type=LRU
477assoc=2
478block_size=64
479clk_domain=system.cpu_clk_domain
480hit_latency=2
481size=131072
482
483[system.cpu.interrupts]
484type=X86LocalApic
485clk_domain=system.cpu.apic_clk_domain
486int_latency=1000
487pio_addr=2305843009213693952
488pio_latency=100000
489system=system
490int_master=system.membus.slave[2]
491int_slave=system.membus.master[2]
492pio=system.membus.master[1]
493
494[system.cpu.isa]
495type=X86ISA
496
497[system.cpu.itb]
498type=X86TLB
499children=walker
500size=64
501walker=system.cpu.itb.walker
502
503[system.cpu.itb.walker]
504type=X86PagetableWalker
505clk_domain=system.cpu_clk_domain
506num_squash_per_cycle=4
507system=system
508port=system.cpu.toL2Bus.slave[2]
509
510[system.cpu.l2cache]
511type=BaseCache
512children=tags
513addr_ranges=0:18446744073709551615
514assoc=8
515clk_domain=system.cpu_clk_domain
516forward_snoops=true
517hit_latency=20
518is_top_level=false
519max_miss_count=0
520mshrs=20
521prefetch_on_access=false
522prefetcher=Null
523response_latency=20
--- 6 unchanged lines hidden (view full) ---
530cpu_side=system.cpu.toL2Bus.master[0]
531mem_side=system.membus.slave[1]
532
533[system.cpu.l2cache.tags]
534type=LRU
535assoc=8
536block_size=64
537clk_domain=system.cpu_clk_domain
538hit_latency=20
539size=2097152
540
541[system.cpu.toL2Bus]
542type=CoherentBus
543clk_domain=system.cpu_clk_domain
544header_cycles=1
545system=system
546use_default_range=false
547width=32
548master=system.cpu.l2cache.cpu_side
549slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
550
551[system.cpu.tracer]
552type=ExeTracer
553
554[system.cpu.workload]
555type=LiveProcess
556cmd=mcf mcf.in
557cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
558egid=100
559env=
560errout=cerr
561euid=100
562executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
563gid=100
564input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
565max_stack_size=67108864
566output=cout
567pid=100
568ppid=99
569simpoint=55300000000
570system=system
571uid=100
572
573[system.cpu_clk_domain]
574type=SrcClockDomain
575clock=500
576voltage_domain=system.voltage_domain
577
578[system.membus]
579type=CoherentBus
580clk_domain=system.clk_domain
581header_cycles=1
582system=system
583use_default_range=false
584width=8
585master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
586slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
587
588[system.physmem]
589type=SimpleDRAM
590activation_limit=4
591addr_mapping=RaBaChCo
592banks_per_rank=8
593burst_length=8
594channels=1
595clk_domain=system.clk_domain
596conf_table_reported=true
597device_bus_width=8
598device_rowbuffer_size=1024
599devices_per_rank=8
600in_addr_map=true
601mem_sched_policy=frfcfs
602null=false
603page_policy=open
604range=0:268435455
605ranks_per_channel=2
606read_buffer_size=32
607static_backend_latency=10000
608static_frontend_latency=10000
609tBURST=5000
610tCL=13750
611tRCD=13750
612tREFI=7800000
613tRFC=300000
614tRP=13750
615tWTR=7500
616tXAW=40000
617write_buffer_size=32
618write_thresh_perc=70
619port=system.membus.master[0]
620
621[system.voltage_domain]
622type=VoltageDomain
623voltage=1.000000
624