Cross Reference: /gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

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sdiff udiff text old ( 9096:8971a998190a ) new ( 9150:a2370fa5c793 )

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stats.txt (9096:8971a998190a)	stats.txt (9150:a2370fa5c793)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362482 # Number of seconds simulated	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362482 # Number of seconds simulated
4sim_ticks 362481577000 # Number of ticks simulated 5final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)	4sim_ticks 362481563000 # Number of ticks simulated 5final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks	6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1217197 # Simulator instruction rate (inst/s) 8host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1809539933 # Simulator tick rate (ticks/s) 10host_mem_usage 354248 # Number of bytes of host memory used 11host_seconds 200.32 # Real time elapsed on the host 12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated	7host_inst_rate 1415125 # Simulator instruction rate (inst/s) 8host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2103788292 # Simulator tick rate (ticks/s) 10host_mem_usage 363728 # Number of bytes of host memory used 11host_seconds 172.30 # Real time elapsed on the host 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 16system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.workload.num_syscalls 443 # Number of system calls	14system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 16system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.workload.num_syscalls 443 # Number of system calls
31system.cpu.numCycles 724963154 # number of cpu cycles simulated	31system.cpu.numCycles 724963126 # number of cpu cycles simulated
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed	32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
34system.cpu.committedInsts 243825163 # Number of instructions committed 35system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses	34system.cpu.committedInsts 243825150 # Number of instructions committed 35system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
37system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 38system.cpu.num_func_calls 4252956 # number of times a function call or return occured	37system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 38system.cpu.num_func_calls 4252956 # number of times a function call or return occured
39system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls 40system.cpu.num_int_insts 194726506 # number of integer instructions	39system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 40system.cpu.num_int_insts 194726494 # number of integer instructions
41system.cpu.num_fp_insts 11630 # number of float instructions	41system.cpu.num_fp_insts 11630 # number of float instructions
42system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read 43system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written	42system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 43system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
44system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 90 # number of times the floating registers were written	44system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
46system.cpu.num_mem_refs 105711442 # number of memory refs 47system.cpu.num_load_insts 82803522 # Number of load instructions	46system.cpu.num_mem_refs 105711441 # number of memory refs 47system.cpu.num_load_insts 82803521 # Number of load instructions
48system.cpu.num_store_insts 22907920 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles	48system.cpu.num_store_insts 22907920 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles
50system.cpu.num_busy_cycles 724963154 # Number of busy cycles	50system.cpu.num_busy_cycles 724963126 # Number of busy cycles
51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 25 # number of replacements	51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 25 # number of replacements
54system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use 55system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.	54system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use 55system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks.
56system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.	56system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
57system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.	57system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks.
58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.	58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
59system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor	59system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor
60system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy	60system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
62system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits 67system.cpu.icache.overall_hits::total 244420630 # number of overall hits	62system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 67system.cpu.icache.overall_hits::total 244420617 # number of overall hits
68system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 69system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 70system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 71system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 72system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 73system.cpu.icache.overall_misses::total 882 # number of overall misses 74system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles 75system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles 76system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles 77system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles 78system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles 79system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles	68system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 69system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 70system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 71system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 72system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 73system.cpu.icache.overall_misses::total 882 # number of overall misses 74system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles 75system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles 76system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles 77system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles 78system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles 79system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
80system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) 81system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) 82system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses 83system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses 84system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses 85system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses	80system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 81system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 82system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 83system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 84system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 85system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 87system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 88system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 89system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 90system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 91system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency 93system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency --- 30 unchanged lines hidden (view full) --- 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 935475 # number of replacements	86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 87system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 88system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 89system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 90system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 91system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency 93system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency --- 30 unchanged lines hidden (view full) --- 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 935475 # number of replacements
132system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use 133system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.	132system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use 133system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
134system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.	134system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
135system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit. 137system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor	135system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit. 137system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor
138system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy 139system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy	138system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy 139system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
140system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits 141system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits	140system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 141system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
142system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 143system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 144system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 145system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits	142system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 143system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 144system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 145system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
146system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits 147system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits 148system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits 149system.cpu.dcache.overall_hits::total 104182818 # number of overall hits	146system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 147system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 148system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 149system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
150system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 151system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 152system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 153system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 154system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 155system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 156system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 157system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses --- 4 unchanged lines hidden (view full) --- 162system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles 163system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles 164system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles 165system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles 166system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles 167system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles 168system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles 169system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles	150system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 151system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 152system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 153system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 154system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 155system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 156system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 157system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses --- 4 unchanged lines hidden (view full) --- 162system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles 163system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles 164system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles 165system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles 166system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles 167system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles 168system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles 169system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
170system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) 171system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)	170system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 171system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 173system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 175system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)	172system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 173system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 175system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
176system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses 177system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses 178system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses 179system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses	176system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 177system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 178system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 179system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
180system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 181system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 182system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 183system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 184system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 185system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 186system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 187system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses --- 56 unchanged lines hidden (view full) --- 244system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency 245system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency 246system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency 247system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency 248system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency 249system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency 250system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.cpu.l2cache.replacements 0 # number of replacements	180system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 181system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 182system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 183system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 184system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 185system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 186system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 187system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses --- 56 unchanged lines hidden (view full) --- 244system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency 245system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency 246system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency 247system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency 248system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency 249system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency 250system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.cpu.l2cache.replacements 0 # number of replacements
252system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use	252system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use