| stats.txt (9055:38f1926fb599) | stats.txt (9079:9a244ebdc3c9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.362431 # Number of seconds simulated 4sim_ticks 362430887000 # Number of ticks simulated 5final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.362429 # Number of seconds simulated 4sim_ticks 362428997000 # Number of ticks simulated 5final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1267775 # Simulator instruction rate (inst/s) 8host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1884467398 # Simulator tick rate (ticks/s) 10host_mem_usage 355400 # Number of bytes of host memory used 11host_seconds 192.33 # Real time elapsed on the host | 7host_inst_rate 1801112 # Simulator instruction rate (inst/s) 8host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2677225778 # Simulator tick rate (ticks/s) 10host_mem_usage 354292 # Number of bytes of host memory used 11host_seconds 135.37 # Real time elapsed on the host |
| 12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory | 12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 16system.physmem.bytes_read::total 998592 # Number of bytes read from this memory |
| 17system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory | 17system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory |
| 19system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory 20system.physmem.bytes_written::total 2560 # Number of bytes written to this memory | |
| 21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory | 19system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 40 # Number of write requests responded to by this memory | 20system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory |
| 26system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) |
| 27system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s) | 23system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s) |
| 29system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) | 25system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s) | |
| 34system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) | 27system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) |
| 35system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s) | 28system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.workload.num_syscalls 443 # Number of system calls | 30system.cpu.workload.num_syscalls 443 # Number of system calls |
| 38system.cpu.numCycles 724861774 # number of cpu cycles simulated | 31system.cpu.numCycles 724857994 # number of cpu cycles simulated |
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 243825163 # Number of instructions committed 42system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 45system.cpu.num_func_calls 4252956 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls 47system.cpu.num_int_insts 194726506 # number of integer instructions 48system.cpu.num_fp_insts 11630 # number of float instructions 49system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read 50system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written 51system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 53system.cpu.num_mem_refs 105711442 # number of memory refs 54system.cpu.num_load_insts 82803522 # Number of load instructions 55system.cpu.num_store_insts 22907920 # Number of store instructions 56system.cpu.num_idle_cycles 0 # Number of idle cycles | 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 243825163 # Number of instructions committed 35system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 38system.cpu.num_func_calls 4252956 # number of times a function call or return occured 39system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls 40system.cpu.num_int_insts 194726506 # number of integer instructions 41system.cpu.num_fp_insts 11630 # number of float instructions 42system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read 43system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written 44system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 46system.cpu.num_mem_refs 105711442 # number of memory refs 47system.cpu.num_load_insts 82803522 # Number of load instructions 48system.cpu.num_store_insts 22907920 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 57system.cpu.num_busy_cycles 724861774 # Number of busy cycles | 50system.cpu.num_busy_cycles 724857994 # Number of busy cycles |
| 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 25 # number of replacements | 51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 25 # number of replacements |
| 61system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use | 54system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use |
| 62system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 55system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. 56system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. 57system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. 58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 66system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor | 59system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor |
| 67system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits 74system.cpu.icache.overall_hits::total 244420630 # number of overall hits --- 56 unchanged lines hidden (view full) --- 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 935475 # number of replacements | 60system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy 62system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits 67system.cpu.icache.overall_hits::total 244420630 # number of overall hits --- 56 unchanged lines hidden (view full) --- 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 935475 # number of replacements |
| 139system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use | 132system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use |
| 140system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. 141system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. 143system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. | 133system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. 134system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. 135system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. |
| 144system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor | 137system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor |
| 145system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits 149system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 151system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 152system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 159system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 160system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 161system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 162system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 163system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 164system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 165system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 166system.cpu.dcache.overall_misses::total 939567 # number of overall misses | 138system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy 139system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy 140system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits 141system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits 142system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 143system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 144system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 145system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 152system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 153system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 154system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 155system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 156system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 157system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 158system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 159system.cpu.dcache.overall_misses::total 939567 # number of overall misses |
| 167system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles 168system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles | 160system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles 161system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles |
| 169system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles 170system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles 171system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles 172system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles | 162system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles 163system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles 164system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles 165system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles |
| 173system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles 174system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles 175system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles 176system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles | 166system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles 167system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles 168system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles 169system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles |
| 177system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) 178system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) 179system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 180system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 181system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 182system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 183system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses 184system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 189system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 190system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 191system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 192system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 193system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 194system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 195system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 196system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses | 170system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) 171system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 173system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 175system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 176system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses 177system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 182system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 183system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 184system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 185system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 186system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 187system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 188system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 189system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses |
| 197system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency 198system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency | 190system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency 191system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency |
| 199system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency 200system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency 201system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency 202system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency | 192system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency 193system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency 194system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency 195system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency |
| 203system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 204system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency 205system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 206system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency | 196system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency 197system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency 198system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency 199system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency |
| 207system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 208system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 209system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 210system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 211system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 212system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213system.cpu.dcache.fast_writes 0 # number of fast writes performed 214system.cpu.dcache.cache_copies 0 # number of cache copies performed | 200system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 201system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 202system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 203system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 204system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 205system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 206system.cpu.dcache.fast_writes 0 # number of fast writes performed 207system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 215system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks 216system.cpu.dcache.writebacks::total 935237 # number of writebacks | 208system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 209system.cpu.dcache.writebacks::total 935266 # number of writebacks |
| 217system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 218system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 219system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 220system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 221system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 222system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 223system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 224system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 225system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 226system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses | 210system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 211system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 212system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 213system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 214system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 215system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 216system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 217system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 218system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 219system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses |
| 227system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles 228system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles | 220system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles 221system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles |
| 229system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 230system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 231system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 232system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles | 222system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 223system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 224system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 225system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles |
| 233system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles 234system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles 235system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles 236system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles | 226system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles 227system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles 228system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles 229system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles |
| 237system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 238system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 239system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 240system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 241system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 242system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 243system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 244system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 245system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 246system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses | 230system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 231system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 232system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 233system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 234system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 235system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 236system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 237system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 238system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 239system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses |
| 247system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency 248system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency | 240system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency 241system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency |
| 249system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 250system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency 251system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 252system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency | 242system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 243system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency 244system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 245system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency |
| 253system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency 254system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency 255system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency 256system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency | 246system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 247system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 248system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 249system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency |
| 257system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 250system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 258system.cpu.l2cache.replacements 865 # number of replacements 259system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use 260system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks. 261system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks. 262system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks. | 251system.cpu.l2cache.replacements 0 # number of replacements 252system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use 253system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. 254system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. 255system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. |
| 263system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 256system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 264system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor 265system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor 266system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor 267system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy 268system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy 269system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy 270system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy | 257system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor 258system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor 259system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor 260system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy 261system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy 262system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy 263system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy |
| 271system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits | 264system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits |
| 272system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits 273system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits 274system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits 275system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits | 265system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits 266system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits 267system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits 268system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits |
| 276system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 277system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 278system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits | 269system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 270system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 271system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits |
| 279system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits 280system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits | 272system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 273system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits |
| 281system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits | 274system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits |
| 282system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits 283system.cpu.l2cache.overall_hits::total 924805 # number of overall hits | 275system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 276system.cpu.l2cache.overall_hits::total 924850 # number of overall hits |
| 284system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses | 277system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses |
| 285system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses 286system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses | 278system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses 279system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses |
| 287system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 288system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 289system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses | 280system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 281system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 282system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses |
| 290system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses 291system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses | 283system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 284system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses |
| 292system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses | 285system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses |
| 293system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses 294system.cpu.l2cache.overall_misses::total 15648 # number of overall misses | 286system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 287system.cpu.l2cache.overall_misses::total 15603 # number of overall misses |
| 295system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles | 288system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles |
| 296system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles 297system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles | 289system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles 290system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles |
| 298system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 299system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 300system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles | 291system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 292system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 293system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles |
| 301system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles 302system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles | 294system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles 295system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles |
| 303system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles | 296system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles |
| 304system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles 305system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles | 297system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles 298system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles |
| 306system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 307system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 308system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) | 299system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 300system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 301system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) |
| 309system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses) 310system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses) | 302system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) 303system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) |
| 311system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 312system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 313system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 314system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 315system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 316system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 317system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 318system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 319system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses | 304system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 305system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 306system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 307system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 308system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 309system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 310system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 311system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 312system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses |
| 320system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses 321system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses | 313system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses 314system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses |
| 322system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 323system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 324system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses | 315system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 316system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 317system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses |
| 325system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses 326system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses | 318system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 319system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses |
| 327system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses | 320system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses |
| 328system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses 329system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses | 321system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 322system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses |
| 330system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 331system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 332system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 333system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 334system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 335system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 336system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 337system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 338system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 339system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 340system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 341system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.l2cache.fast_writes 0 # number of fast writes performed 348system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 323system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 324system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 325system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 326system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 327system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 328system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 329system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 330system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 331system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 332system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 333system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 334system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 335system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 336system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 337system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 338system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 339system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 340system.cpu.l2cache.fast_writes 0 # number of fast writes performed 341system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 349system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks 350system.cpu.l2cache.writebacks::total 40 # number of writebacks | |
| 351system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses | 342system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses |
| 352system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 353system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses | 343system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses 344system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses |
| 354system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 355system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 356system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses | 345system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 346system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 347system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses |
| 357system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses 358system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses | 348system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 349system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses |
| 359system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses | 350system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses |
| 360system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses 361system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses | 351system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 352system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses |
| 362system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles | 353system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles |
| 363system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles 364system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles | 354system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles 355system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles |
| 365system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 366system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 367system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles | 356system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 357system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 358system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles |
| 368system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles 369system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles | 359system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles 360system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles |
| 370system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles | 361system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles |
| 371system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles 372system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles | 362system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles 363system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles |
| 373system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses | 364system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses |
| 374system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses 375system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses | 365system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses |
| 376system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 377system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 378system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses | 367system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 368system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 369system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses |
| 379system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses 380system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses | 370system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 371system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses |
| 381system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses | 372system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses |
| 382system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses 383system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses | 373system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 374system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses |
| 384system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 385system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 386system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 387system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 388system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 389system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 390system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 391system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 392system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 393system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 394system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 395system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 396 397---------- End Simulation Statistics ---------- | 375system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 376system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 377system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 378system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 379system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 380system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 381system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 382system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 383system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 384system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 385system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 386system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 387 388---------- End Simulation Statistics ---------- |