| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362431 # Number of seconds simulated 4sim_ticks 362430887000 # Number of ticks simulated 5final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362431 # Number of seconds simulated 4sim_ticks 362430887000 # Number of ticks simulated 5final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1947938 # Simulator instruction rate (inst/s) 8host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2895487158 # Simulator tick rate (ticks/s) 10host_mem_usage 344700 # Number of bytes of host memory used 11host_seconds 125.17 # Real time elapsed on the host | 7host_inst_rate 628265 # Simulator instruction rate (inst/s) 8host_op_rate 628291 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 933876298 # Simulator tick rate (ticks/s) 10host_mem_usage 354916 # Number of bytes of host memory used 11host_seconds 388.09 # Real time elapsed on the host |
| 12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 1001472 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 2560 # Number of bytes written to this memory 17system.physmem.num_reads 15648 # Number of read requests responded to by this memory 18system.physmem.num_writes 40 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 62 unchanged lines hidden (view full) --- 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 1001472 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 2560 # Number of bytes written to this memory 17system.physmem.num_reads 15648 # Number of read requests responded to by this memory 18system.physmem.num_writes 40 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 62 unchanged lines hidden (view full) --- 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 90system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 90system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 168system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency 170system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 171system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 172system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 175system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 168system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency 170system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 171system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 172system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 175system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 176system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 177system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 176system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 177system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 178system.cpu.dcache.fast_writes 0 # number of fast writes performed 179system.cpu.dcache.cache_copies 0 # number of cache copies performed 180system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks 181system.cpu.dcache.writebacks::total 935237 # number of writebacks 182system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 183system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 184system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses --- 98 unchanged lines hidden (view full) --- 284system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 285system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 286system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 287system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 288system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 290system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 291system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 178system.cpu.dcache.fast_writes 0 # number of fast writes performed 179system.cpu.dcache.cache_copies 0 # number of cache copies performed 180system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks 181system.cpu.dcache.writebacks::total 935237 # number of writebacks 182system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 183system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 184system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses --- 98 unchanged lines hidden (view full) --- 284system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 285system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 286system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 287system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 288system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 290system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 291system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 292system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 293system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 292system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 293system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 294system.cpu.l2cache.fast_writes 0 # number of fast writes performed 295system.cpu.l2cache.cache_copies 0 # number of cache copies performed 296system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks 297system.cpu.l2cache.writebacks::total 40 # number of writebacks 298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 300system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses 301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses --- 35 unchanged lines hidden --- | 294system.cpu.l2cache.fast_writes 0 # number of fast writes performed 295system.cpu.l2cache.cache_copies 0 # number of cache copies performed 296system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks 297system.cpu.l2cache.writebacks::total 40 # number of writebacks 298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 300system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses 301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses --- 35 unchanged lines hidden --- |