| stats.txt (8802:ef66a9083bc4) | stats.txt (8835:7c68f84d7c4e) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362431 # Number of seconds simulated 4sim_ticks 362430887000 # Number of ticks simulated 5final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362431 # Number of seconds simulated 4sim_ticks 362430887000 # Number of ticks simulated 5final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1587659 # Simulator instruction rate (inst/s) 8host_tick_rate 2359857170 # Simulator tick rate (ticks/s) 9host_mem_usage 346888 # Number of bytes of host memory used 10host_seconds 153.58 # Real time elapsed on the host 11sim_insts 243835278 # Number of instructions simulated | 7host_inst_rate 1947938 # Simulator instruction rate (inst/s) 8host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2895487158 # Simulator tick rate (ticks/s) 10host_mem_usage 344700 # Number of bytes of host memory used 11host_seconds 125.17 # Real time elapsed on the host 12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated |
| 12system.physmem.bytes_read 1001472 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 2560 # Number of bytes written to this memory 15system.physmem.num_reads 15648 # Number of read requests responded to by this memory 16system.physmem.num_writes 40 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s) 22system.cpu.workload.num_syscalls 443 # Number of system calls 23system.cpu.numCycles 724861774 # number of cpu cycles simulated 24system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 25system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 14system.physmem.bytes_read 1001472 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 2560 # Number of bytes written to this memory 17system.physmem.num_reads 15648 # Number of read requests responded to by this memory 18system.physmem.num_writes 40 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.workload.num_syscalls 443 # Number of system calls 25system.cpu.numCycles 724861774 # number of cpu cycles simulated 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 26system.cpu.num_insts 243835278 # Number of instructions executed | 28system.cpu.committedInsts 243825163 # Number of instructions committed 29system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed |
| 27system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses 28system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 29system.cpu.num_func_calls 4252956 # number of times a function call or return occured 30system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls 31system.cpu.num_int_insts 194726506 # number of integer instructions 32system.cpu.num_fp_insts 11630 # number of float instructions 33system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read 34system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written --- 7 unchanged lines hidden (view full) --- 42system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 43system.cpu.idle_fraction 0 # Percentage of idle cycles 44system.cpu.icache.replacements 25 # number of replacements 45system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use 46system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. 47system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. 48system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. 49system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 30system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses 31system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 32system.cpu.num_func_calls 4252956 # number of times a function call or return occured 33system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls 34system.cpu.num_int_insts 194726506 # number of integer instructions 35system.cpu.num_fp_insts 11630 # number of float instructions 36system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read 37system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written --- 7 unchanged lines hidden (view full) --- 45system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 46system.cpu.idle_fraction 0 # Percentage of idle cycles 47system.cpu.icache.replacements 25 # number of replacements 48system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use 49system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. 50system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. 51system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. 52system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 50system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context 51system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy 52system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits 53system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits 54system.cpu.icache.overall_hits 244420630 # number of overall hits 55system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses 56system.cpu.icache.demand_misses 882 # number of demand (read+write) misses 57system.cpu.icache.overall_misses 882 # number of overall misses 58system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles 59system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles 60system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles 61system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) 62system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses 63system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses 64system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses 65system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses 66system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses 67system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency 68system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency 69system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency | 53system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor 54system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy 55system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy 56system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits 57system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits 58system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits 59system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits 60system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits 61system.cpu.icache.overall_hits::total 244420630 # number of overall hits 62system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 63system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 64system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 65system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 66system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 67system.cpu.icache.overall_misses::total 882 # number of overall misses 68system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles 69system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles 70system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles 71system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles 72system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles 73system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles 74system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) 75system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) 76system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses 77system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses 78system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses 79system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses 80system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 81system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency |
| 70system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 71system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 73system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 74system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 76system.cpu.icache.fast_writes 0 # number of fast writes performed 77system.cpu.icache.cache_copies 0 # number of cache copies performed | 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 90system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 78system.cpu.icache.writebacks 0 # number of writebacks 79system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 80system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 81system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses 82system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses 83system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses 84system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 85system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles 86system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles 87system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles 88system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 89system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses 90system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses 91system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses 92system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency 93system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency 94system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency 95system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 96system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 97system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions | 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles 101system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles 102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles 103system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles 104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles 105system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles 106system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 107system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 108system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 109system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 110system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 111system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency |
| 98system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 99system.cpu.dcache.replacements 935475 # number of replacements 100system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use 101system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. 102system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. 103system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. 104system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. | 112system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 113system.cpu.dcache.replacements 935475 # number of replacements 114system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use 115system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. 116system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. 117system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. 118system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. |
| 105system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context 106system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy 107system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits 108system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits 109system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits 110system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits 111system.cpu.dcache.overall_hits 104182818 # number of overall hits 112system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses 113system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses 114system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses 115system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses 116system.cpu.dcache.overall_misses 939567 # number of overall misses 117system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles 118system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles 119system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles 120system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles 121system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles 122system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) 123system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) 124system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) 125system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses 126system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses 127system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses 128system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses 129system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses 130system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses 131system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses 132system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency 133system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency 134system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency 135system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency 136system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency | 119system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor 120system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy 121system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy 122system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits 123system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits 124system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 125system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 126system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 127system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 128system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits 129system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits 130system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits 131system.cpu.dcache.overall_hits::total 104182818 # number of overall hits 132system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 133system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 134system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 135system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 136system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 137system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 138system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 139system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 140system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 141system.cpu.dcache.overall_misses::total 939567 # number of overall misses 142system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles 143system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles 144system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles 145system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles 146system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles 147system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles 148system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles 149system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles 150system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles 151system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles 152system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) 153system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) 154system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 155system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 156system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 157system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 158system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses 159system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses 160system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses 161system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses 162system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 163system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 164system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 165system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 166system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 167system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency 170system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency 171system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency |
| 137system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 138system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 139system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 140system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 141system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 142system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 143system.cpu.dcache.fast_writes 0 # number of fast writes performed 144system.cpu.dcache.cache_copies 0 # number of cache copies performed | 172system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 175system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 176system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 177system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 178system.cpu.dcache.fast_writes 0 # number of fast writes performed 179system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 145system.cpu.dcache.writebacks 935237 # number of writebacks 146system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 147system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 148system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses 149system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses 150system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses 151system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses 152system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses 153system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 154system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles 155system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles 156system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles 157system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles 158system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles 159system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 160system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses 161system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses 162system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses 163system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses 164system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses 165system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency 166system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency 167system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency 168system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency 169system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency 170system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 171system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 172system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions | 180system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks 181system.cpu.dcache.writebacks::total 935237 # number of writebacks 182system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 183system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 184system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 186system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 187system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 188system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 189system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 190system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 191system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles 194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 195system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 196system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 197system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles 198system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles 199system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles 200system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles 201system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles 202system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 203system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 204system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency 208system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 209system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 210system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency 211system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency |
| 173system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 174system.cpu.l2cache.replacements 865 # number of replacements 175system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use 176system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks. 177system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks. 178system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks. 179system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 212system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 213system.cpu.l2cache.replacements 865 # number of replacements 214system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use 215system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks. 216system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks. 217system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks. 218system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 180system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context 181system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context 182system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy 183system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy 184system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits 185system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits 186system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits 187system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits 188system.cpu.l2cache.overall_hits 924805 # number of overall hits 189system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses 190system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses 191system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses 192system.cpu.l2cache.overall_misses 15648 # number of overall misses 193system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles 194system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles 195system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles 196system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles 197system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) 198system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses) 199system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) 200system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses 201system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses 202system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses 203system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses 204system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses 205system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses 206system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 207system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 208system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 209system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency | 219system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor 220system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor 221system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor 222system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy 223system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy 224system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy 225system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy 226system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 227system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits 228system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits 229system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits 230system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits 231system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 232system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 233system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 234system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits 235system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits 236system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 237system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits 238system.cpu.l2cache.overall_hits::total 924805 # number of overall hits 239system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses 240system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses 241system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses 242system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 243system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 244system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 245system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses 246system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses 247system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 248system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses 249system.cpu.l2cache.overall_misses::total 15648 # number of overall misses 250system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles 251system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles 252system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles 253system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 254system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 255system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles 256system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles 257system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles 258system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles 259system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles 260system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles 261system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 262system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 263system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) 264system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses) 265system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses) 266system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 267system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 268system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 269system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 270system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 271system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 272system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 273system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 274system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses 275system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses 276system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 277system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 278system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses 279system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 280system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses 281system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 282system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 283system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 284system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 285system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 286system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 287system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency |
| 210system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 211system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 212system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 213system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 214system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 215system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 216system.cpu.l2cache.fast_writes 0 # number of fast writes performed 217system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 288system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 290system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 291system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 292system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 293system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 294system.cpu.l2cache.fast_writes 0 # number of fast writes performed 295system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 218system.cpu.l2cache.writebacks 40 # number of writebacks 219system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 220system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 221system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses 222system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses 223system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses 224system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses 225system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 226system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles 227system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles 228system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles 229system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles 230system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 231system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses 232system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses 233system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses 234system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses 235system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 236system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 237system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 238system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 239system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 240system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 241system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions | 296system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks 297system.cpu.l2cache.writebacks::total 40 # number of writebacks 298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 300system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses 301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 302system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 303system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 304system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses 305system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses 306system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 307system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses 308system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses 309system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles 310system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles 311system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles 312system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 313system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 314system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles 315system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles 316system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles 317system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles 318system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles 319system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles 320system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 321system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses 322system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 323system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 324system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses 325system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 326system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses 327system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 328system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 329system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 330system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 331system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 332system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 333system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 242system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 243 244---------- End Simulation Statistics ---------- | 334system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 335 336---------- End Simulation Statistics ---------- |