| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361598 # Number of seconds simulated 4sim_ticks 361597758500 # Number of ticks simulated 5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361598 # Number of seconds simulated 4sim_ticks 361597758500 # Number of ticks simulated 5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 779266 # Simulator instruction rate (inst/s) 8host_op_rate 779298 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1155667536 # Simulator tick rate (ticks/s) 10host_mem_usage 379236 # Number of bytes of host memory used 11host_seconds 312.89 # Real time elapsed on the host | 7host_inst_rate 1652209 # Simulator instruction rate (inst/s) 8host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2450259534 # Simulator tick rate (ticks/s) 10host_mem_usage 427260 # Number of bytes of host memory used 11host_seconds 147.58 # Real time elapsed on the host |
| 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 443 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 443 # Number of system calls |
| 36system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states |
|
| 34system.cpu.numCycles 723195517 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 243825150 # Number of instructions committed 38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 41system.cpu.num_func_calls 4252956 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 84system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 244431613 # Class of executed instruction | 37system.cpu.numCycles 723195517 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 243825150 # Number of instructions committed 41system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 44system.cpu.num_func_calls 4252956 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 90system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 91system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 244431613 # Class of executed instruction |
| 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 92system.cpu.dcache.tags.replacements 935475 # number of replacements 93system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 107system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 108system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses | 96system.cpu.dcache.tags.replacements 935475 # number of replacements 97system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use 98system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. 102system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy 105system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 110system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 111system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 112system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses |
| 113system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 109system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 110system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 111system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 112system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 113system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 114system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 115system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 116system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 209system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency 211system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency 212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 214system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 216system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency | 114system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 115system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 116system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 117system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 118system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 119system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 120system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 121system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency 216system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency 218system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency 220system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency |
| 222system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 217system.cpu.icache.tags.replacements 25 # number of replacements 218system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use 219system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 223system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy 226system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 229system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 231system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 232system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 233system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses | 223system.cpu.icache.tags.replacements 25 # number of replacements 224system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use 225system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 226system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 227system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 228system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 229system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor 230system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy 231system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 237system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 238system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 239system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses |
| 240system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 234system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 235system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 236system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 237system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 238system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 239system.cpu.icache.overall_hits::total 244420617 # number of overall hits 240system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 241system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 294system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 295system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency 297system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 299system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 301system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency | 241system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 242system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 243system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 244system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 245system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 246system.cpu.icache.overall_hits::total 244420617 # number of overall hits 247system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 248system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 301system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 302system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency 304system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 306system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 308system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency |
| 309system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 302system.cpu.l2cache.tags.replacements 0 # number of replacements 303system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use 304system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 305system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 308system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id 321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id 322system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses 323system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses | 310system.cpu.l2cache.tags.replacements 0 # number of replacements 311system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use 312system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 313system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 314system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 315system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 316system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id 329system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id 330system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses 331system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses |
| 332system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
|
| 324system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits 325system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits 326system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits 327system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits 328system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 329system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 330system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 331system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 457system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 458system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 461system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 333system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits 334system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits 335system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits 336system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits 337system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 338system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 339system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 340system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 465system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 467system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 468system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 469system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 471system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 472system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 473system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
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| 464system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 488system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram 490system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) 491system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 494system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 495system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) | 474system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 498system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram 500system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) 501system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 502system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 503system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 504system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 505system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 506system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states |
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| 496system.membus.trans_dist::ReadResp 1036 # Transaction distribution 497system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 498system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 499system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution 500system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 501system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 502system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 503system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 507system.membus.trans_dist::ReadResp 1036 # Transaction distribution 508system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 509system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 510system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution 511system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 512system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 513system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 514system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |