| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361598 # Number of seconds simulated 4sim_ticks 361597758500 # Number of ticks simulated 5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361598 # Number of seconds simulated 4sim_ticks 361597758500 # Number of ticks simulated 5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1193747 # Simulator instruction rate (inst/s) 8host_op_rate 1193796 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1770350920 # Simulator tick rate (ticks/s) 10host_mem_usage 429888 # Number of bytes of host memory used 11host_seconds 204.25 # Real time elapsed on the host | 7host_inst_rate 1238958 # Simulator instruction rate (inst/s) 8host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1837400352 # Simulator tick rate (ticks/s) 10host_mem_usage 383872 # Number of bytes of host memory used 11host_seconds 196.80 # Real time elapsed on the host |
| 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory --- 147 unchanged lines hidden (view full) --- 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory --- 147 unchanged lines hidden (view full) --- 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 175system.cpu.dcache.fast_writes 0 # number of fast writes performed 176system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 177system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 178system.cpu.dcache.writebacks::total 935266 # number of writebacks 179system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 180system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 182system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 183system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 184system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency 212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency 215system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency | 175system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 176system.cpu.dcache.writebacks::total 935266 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 181system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 182system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 209system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency 211system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency 212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 214system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 216system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency |
| 219system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 220system.cpu.icache.tags.replacements 25 # number of replacements 221system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use 222system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 223system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 224system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 225system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 226system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor 227system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 271system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency 272system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency 273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 217system.cpu.icache.tags.replacements 25 # number of replacements 218system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use 219system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 223system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 268system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency 269system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 279system.cpu.icache.fast_writes 0 # number of fast writes performed 280system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 281system.cpu.icache.writebacks::writebacks 25 # number of writebacks 282system.cpu.icache.writebacks::total 25 # number of writebacks 283system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 284system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 285system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 286system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 287system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 288system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 299system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 300system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 301system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency 302system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency 303system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 304system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency 305system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 306system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency | 276system.cpu.icache.writebacks::writebacks 25 # number of writebacks 277system.cpu.icache.writebacks::total 25 # number of writebacks 278system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 279system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 280system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 281system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 282system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 283system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 294system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 295system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency 297system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 299system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 301system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency |
| 307system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 308system.cpu.l2cache.tags.replacements 0 # number of replacements 309system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use 310system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 311system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 312system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 313system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 314system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor 315system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 408system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 409system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency 410system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 411system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 412system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 413system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 414system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 415system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 302system.cpu.l2cache.tags.replacements 0 # number of replacements 303system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use 304system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 305system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 308system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 402system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency 404system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 416system.cpu.l2cache.fast_writes 0 # number of fast writes performed 417system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 418system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 419system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 420system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses 421system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses 422system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses 423system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses 424system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 425system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 458system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 459system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 460system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 461system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 462system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 463system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 464system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 465system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency | 410system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 411system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 412system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses 413system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses 414system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses 415system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses 416system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 417system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 450system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 451system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 457system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency |
| 466system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 467system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 468system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 469system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 471system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 472system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 473system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution --- 55 unchanged lines hidden --- | 458system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 461system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 464system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution --- 55 unchanged lines hidden --- |