| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated |
| 4sim_ticks 361488535500 # Number of ticks simulated 5final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 361488536500 # Number of ticks simulated 5final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1224088 # Simulator instruction rate (inst/s) 8host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1814798992 # Simulator tick rate (ticks/s) 10host_mem_usage 426288 # Number of bytes of host memory used 11host_seconds 199.19 # Real time elapsed on the host | 7host_inst_rate 1117046 # Simulator instruction rate (inst/s) 8host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1656101101 # Simulator tick rate (ticks/s) 10host_mem_usage 428664 # Number of bytes of host memory used 11host_seconds 218.28 # Real time elapsed on the host |
| 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory --- 6 unchanged lines hidden (view full) --- 26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 443 # Number of system calls | 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory --- 6 unchanged lines hidden (view full) --- 26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 443 # Number of system calls |
| 34system.cpu.numCycles 722977071 # number of cpu cycles simulated | 34system.cpu.numCycles 722977073 # number of cpu cycles simulated |
| 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 243825150 # Number of instructions committed 38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 41system.cpu.num_func_calls 4252956 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 43system.cpu.num_int_insts 194726494 # number of integer instructions 44system.cpu.num_fp_insts 11630 # number of float instructions 45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 49system.cpu.num_mem_refs 105711441 # number of memory refs 50system.cpu.num_load_insts 82803521 # Number of load instructions 51system.cpu.num_store_insts 22907920 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 243825150 # Number of instructions committed 38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 41system.cpu.num_func_calls 4252956 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 43system.cpu.num_int_insts 194726494 # number of integer instructions 44system.cpu.num_fp_insts 11630 # number of float instructions 45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 49system.cpu.num_mem_refs 105711441 # number of memory refs 50system.cpu.num_load_insts 82803521 # Number of load instructions 51system.cpu.num_store_insts 22907920 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 53system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles | 53system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles |
| 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 29302884 # Number of branches fetched 57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 244431613 # Class of executed instruction 92system.cpu.dcache.tags.replacements 935475 # number of replacements | 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 29302884 # Number of branches fetched 57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 244431613 # Class of executed instruction 92system.cpu.dcache.tags.replacements 935475 # number of replacements |
| 93system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use | 93system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use |
| 94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. | 94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. |
| 97system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor | 97system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor |
| 99system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id --- 14 unchanged lines hidden (view full) --- 121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 128system.cpu.dcache.overall_misses::total 939567 # number of overall misses | 99system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id --- 14 unchanged lines hidden (view full) --- 121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 128system.cpu.dcache.overall_misses::total 939567 # number of overall misses |
| 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles 130system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles | 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles 130system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles |
| 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 133system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 134system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles | 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 133system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 134system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles |
| 135system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles 136system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles 137system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles 138system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles | 135system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles 136system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles 137system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles 138system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles |
| 139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses | 139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses |
| 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency | 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency |
| 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 164system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency | 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 164system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency |
| 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 166system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency | 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency 166system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency |
| 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.dcache.fast_writes 0 # number of fast writes performed 176system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 182system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 183system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 184system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 185system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 186system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 187system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 188system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses | 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.dcache.fast_writes 0 # number of fast writes performed 176system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 182system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 183system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 184system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 185system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 186system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 187system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 188system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses |
| 189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles 190system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles | 189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles 190system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles |
| 191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles 192system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles 193system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles 194system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles | 191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles 192system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles 193system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles 194system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles |
| 195system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles 196system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles 197system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles 198system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles | 195system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles 196system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles 197system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles 198system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles |
| 199system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 200system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 201system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 202system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 203system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 204system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 206system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 207system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 208system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses | 199system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 200system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 201system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 202system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 203system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 204system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 206system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 207system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 208system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses |
| 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency 210system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency | 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency 210system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency |
| 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency 212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency | 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency 212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency |
| 215system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency | 215system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency |
| 219system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 220system.cpu.icache.tags.replacements 25 # number of replacements | 219system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 220system.cpu.icache.tags.replacements 25 # number of replacements |
| 221system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use | 221system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use |
| 222system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 223system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 224system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 225system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 222system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 223system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 224system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 225system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 226system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor | 226system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor |
| 227system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 228system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 234system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id --- 64 unchanged lines hidden (view full) --- 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency 305system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 306system.cpu.l2cache.tags.replacements 0 # number of replacements | 227system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 228system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 234system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id --- 64 unchanged lines hidden (view full) --- 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency 305system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 306system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 307system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use | 307system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use |
| 308system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 308system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 312system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor | 312system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor |
| 314system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor 315system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id --- 131 unchanged lines hidden (view full) --- 453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency 455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 456system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency 457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency 458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency 460system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 314system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor 315system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id --- 131 unchanged lines hidden (view full) --- 453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency 455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 456system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency 457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency 458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency 460system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 461system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 464system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 461system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution 468system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.snoops 0 # Total snoops (count) 475system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram | 467system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution 474system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) 476system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 479system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.snoops 0 # Total snoops (count) 481system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram |
| 476system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 482system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram |
| 478system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 484system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 479system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram | 485system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram |
| 481system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 487system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 483system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 489system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 484system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram 486system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) 487system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 488system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 489system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 490system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 491system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) --- 25 unchanged lines hidden --- | 490system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram 492system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) 493system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 494system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 495system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 496system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 497system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) --- 25 unchanged lines hidden --- |