| stats.txt (10488:7c27480a5031) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated |
| 4sim_ticks 361488530000 # Number of ticks simulated 5final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 361488530500 # Number of ticks simulated 5final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1379749 # Simulator instruction rate (inst/s) 8host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2045576865 # Simulator tick rate (ticks/s) 10host_mem_usage 421936 # Number of bytes of host memory used 11host_seconds 176.72 # Real time elapsed on the host | 7host_inst_rate 1163469 # Simulator instruction rate (inst/s) 8host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1724927568 # Simulator tick rate (ticks/s) 10host_mem_usage 425840 # Number of bytes of host memory used 11host_seconds 209.57 # Real time elapsed on the host |
| 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory --- 4 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory --- 4 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) |
| 32system.membus.trans_dist::ReadReq 1036 # Transaction distribution 33system.membus.trans_dist::ReadResp 1036 # Transaction distribution 34system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 35system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 15603 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 15603 # Request fanout histogram 51system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 53system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.0 # Layer utilization (%) | |
| 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.workload.num_syscalls 443 # Number of system calls | 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 443 # Number of system calls |
| 57system.cpu.numCycles 722977060 # number of cpu cycles simulated | 34system.cpu.numCycles 722977061 # number of cpu cycles simulated |
| 58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 60system.cpu.committedInsts 243825150 # Number of instructions committed 61system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 62system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 63system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 64system.cpu.num_func_calls 4252956 # number of times a function call or return occured 65system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 66system.cpu.num_int_insts 194726494 # number of integer instructions 67system.cpu.num_fp_insts 11630 # number of float instructions 68system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 69system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 70system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 71system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 72system.cpu.num_mem_refs 105711441 # number of memory refs 73system.cpu.num_load_insts 82803521 # Number of load instructions 74system.cpu.num_store_insts 22907920 # Number of store instructions 75system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 243825150 # Number of instructions committed 38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 41system.cpu.num_func_calls 4252956 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 43system.cpu.num_int_insts 194726494 # number of integer instructions 44system.cpu.num_fp_insts 11630 # number of float instructions 45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 49system.cpu.num_mem_refs 105711441 # number of memory refs 50system.cpu.num_load_insts 82803521 # Number of load instructions 51system.cpu.num_store_insts 22907920 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 76system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles | 53system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles |
| 77system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 78system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 79system.cpu.Branches 29302884 # Number of branches fetched 80system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 81system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 82system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 83system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 84system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 107system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 109system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 110system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 111system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 112system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 113system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 114system.cpu.op_class::total 244431613 # Class of executed instruction | 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 29302884 # Number of branches fetched 57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 84system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 244431613 # Class of executed instruction |
| 92system.cpu.dcache.tags.replacements 935475 # number of replacements 93system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 107system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 108system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses 109system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 110system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 111system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 112system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 113system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 114system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 115system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 116system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 117system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 118system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 119system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 120system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 128system.cpu.dcache.overall_misses::total 939567 # number of overall misses 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles 130system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 133system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 134system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles 135system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles 136system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles 137system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles 138system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles 139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 147system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 148system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 149system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 150system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 164system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 166system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.dcache.fast_writes 0 # number of fast writes performed 176system.cpu.dcache.cache_copies 0 # number of cache copies performed 177system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 178system.cpu.dcache.writebacks::total 935266 # number of writebacks 179system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 180system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 182system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 183system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 184system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 185system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 186system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 187system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 188system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles 190system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles 191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles 192system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles 193system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles 194system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles 195system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles 196system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles 197system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles 198system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles 199system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 200system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 201system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 202system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 203system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 204system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 206system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 207system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 208system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency 210system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency 212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency 215system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency 219system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 115system.cpu.icache.tags.replacements 25 # number of replacements | 220system.cpu.icache.tags.replacements 25 # number of replacements |
| 116system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use | 221system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use |
| 117system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 118system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 119system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 120system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 222system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 223system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 224system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 225system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 121system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor | 226system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor |
| 122system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 123system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy 124system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 125system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 126system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 127system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 128system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 129system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 136system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 137system.cpu.icache.overall_hits::total 244420617 # number of overall hits 138system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 139system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 140system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 141system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 142system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 143system.cpu.icache.overall_misses::total 882 # number of overall misses | 227system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 228system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 234system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 241system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 242system.cpu.icache.overall_hits::total 244420617 # number of overall hits 243system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 244system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 245system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 246system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 247system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 248system.cpu.icache.overall_misses::total 882 # number of overall misses |
| 144system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles 145system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles 146system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles 147system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles 148system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles 149system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles | 249system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles 250system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles 251system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles 252system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles 253system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles 254system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles |
| 150system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 151system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 152system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 153system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 154system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 155system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 156system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 157system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 158system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 159system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 160system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 161system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses | 255system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 256system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 257system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 258system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 259system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 260system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 261system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 262system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 263system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 264system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 265system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 266system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
| 162system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency 163system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency 164system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 165system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency 166system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 167system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency | 267system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency 268system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency 269system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency 270system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency 272system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency |
| 168system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.icache.fast_writes 0 # number of fast writes performed 175system.cpu.icache.cache_copies 0 # number of cache copies performed 176system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 177system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 178system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 179system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 180system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 181system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses | 273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 279system.cpu.icache.fast_writes 0 # number of fast writes performed 280system.cpu.icache.cache_copies 0 # number of cache copies performed 281system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 282system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 283system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 284system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 285system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 286system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses |
| 182system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles 183system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles 184system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles 185system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles 186system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles 187system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles | 287system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles 288system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles 289system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles 290system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles 291system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles 292system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles |
| 188system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 189system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 190system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 191system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 192system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 193system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses | 293system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 294system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 295system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 296system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 297system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 298system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses |
| 194system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 195system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency 196system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 197system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 198system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 199system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency | 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency |
| 200system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 201system.cpu.l2cache.tags.replacements 0 # number of replacements | 305system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 306system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 202system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use | 307system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use |
| 203system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. 204system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 205system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. 206system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 308system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 207system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor 208system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor | 312system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor |
| 209system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor 210system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 211system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 212system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 213system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy 214system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 215system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 216system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id --- 22 unchanged lines hidden (view full) --- 239system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 240system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 241system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 242system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 243system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 244system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 245system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 246system.cpu.l2cache.overall_misses::total 15603 # number of overall misses | 314system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor 315system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id --- 22 unchanged lines hidden (view full) --- 344system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 345system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 346system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 347system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 348system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 349system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 350system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 351system.cpu.l2cache.overall_misses::total 15603 # number of overall misses |
| 247system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles 248system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles 249system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles 250system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 251system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 252system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles 253system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles 254system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles 255system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles 256system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles 257system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles | 352system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles 353system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles 354system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles 355system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles 356system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles 357system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles 358system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles 359system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles 360system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles 361system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles 362system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles |
| 258system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 259system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 260system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) 261system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) 262system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) 263system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 264system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 265system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 274system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 275system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 276system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 277system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 278system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 279system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 280system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 281system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses | 363system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 364system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 365system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) 366system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) 367system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) 368system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 369system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 370system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 379system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 380system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 381system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 382system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 383system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 384system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 385system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 386system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses |
| 282system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 283system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 284system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 285system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 286system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 287system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 288system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 289system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 290system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 291system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 292system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency | 387system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency 388system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 389system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency 390system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 391system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 392system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency 393system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 394system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency 395system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency 396system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 397system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency |
| 293system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 294system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 295system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 296system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 297system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 298system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 299system.cpu.l2cache.fast_writes 0 # number of fast writes performed 300system.cpu.l2cache.cache_copies 0 # number of cache copies performed 301system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 302system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses 303system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses 304system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 305system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 306system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 307system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 308system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 309system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 310system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 311system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses | 398system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 399system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 400system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 401system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 402system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 403system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 404system.cpu.l2cache.fast_writes 0 # number of fast writes performed 405system.cpu.l2cache.cache_copies 0 # number of cache copies performed 406system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 407system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses 408system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses 409system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 410system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 411system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 412system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 413system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 414system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 415system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 416system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses |
| 312system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles 313system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles 314system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles 315system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 316system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 317system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles 318system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles 319system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles 320system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles 321system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles 322system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles | 417system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles 418system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles 419system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles 420system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles 421system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles 422system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles 423system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles 424system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles 425system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles 426system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles 427system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles |
| 323system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 324system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses 325system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses 326system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 327system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 328system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 329system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 330system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 331system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 332system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 333system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses | 428system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 429system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses 430system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses 431system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 432system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 433system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 434system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 435system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 436system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 437system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 438system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses |
| 334system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 335system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 336system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 337system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 338system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 339system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 340system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 341system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 342system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 343system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 344system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency | 439system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 440system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 441system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 442system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 443system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 444system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 447system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency |
| 345system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 450system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 346system.cpu.dcache.tags.replacements 935475 # number of replacements 347system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use 348system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 349system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 350system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 351system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. 352system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor 353system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 354system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy 355system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 356system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 357system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id 359system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 360system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 361system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 362system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses 363system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 364system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 365system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 366system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 367system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 368system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 369system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 370system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 371system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 372system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 373system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 374system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 375system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 376system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 377system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 378system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 379system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 382system.cpu.dcache.overall_misses::total 939567 # number of overall misses 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 387system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 388system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles 389system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles 390system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles 391system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles 392system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles 393system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 394system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 395system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 396system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 397system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 398system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 399system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 400system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 401system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 402system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 403system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 404system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 406system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 407system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 408system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 409system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 410system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 411system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 412system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 413system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency 414system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency 415system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 416system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 417system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 418system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency 419system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 420system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency 421system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 422system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency 423system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 424system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 425system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 427system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 429system.cpu.dcache.fast_writes 0 # number of fast writes performed 430system.cpu.dcache.cache_copies 0 # number of cache copies performed 431system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 432system.cpu.dcache.writebacks::total 935266 # number of writebacks 433system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 434system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 435system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 436system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 437system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 438system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 439system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 440system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 441system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 442system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 443system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles 444system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles 445system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 446system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 447system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 448system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles 449system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles 450system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles 452system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles 453system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 457system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 458system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 459system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 460system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 461system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 462system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 463system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency 464system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency 465system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency 467system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 468system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency 469system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 470system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 471system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 472system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 473system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 474system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 479system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) 480system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 495system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram 497system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) 498system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 499system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 500system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 501system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 502system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) | 451system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 456system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) 457system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 472system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram 474system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) 475system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 476system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 477system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 480system.membus.trans_dist::ReadReq 1036 # Transaction distribution 481system.membus.trans_dist::ReadResp 1036 # Transaction distribution 482system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 483system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 484system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 485system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 486system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 487system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 488system.membus.snoops 0 # Total snoops (count) 489system.membus.snoop_fanout::samples 15603 # Request fanout histogram 490system.membus.snoop_fanout::mean 0 # Request fanout histogram 491system.membus.snoop_fanout::stdev 0 # Request fanout histogram 492system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 493system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram 494system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 495system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 496system.membus.snoop_fanout::min_value 0 # Request fanout histogram 497system.membus.snoop_fanout::max_value 0 # Request fanout histogram 498system.membus.snoop_fanout::total 15603 # Request fanout histogram 499system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) 500system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 501system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks) 502system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
|
| 503 504---------- End Simulation Statistics ---------- | 503 504---------- End Simulation Statistics ---------- |