1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362431 # Number of seconds simulated 4sim_ticks 362430887000 # Number of ticks simulated 5final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1267775 # Simulator instruction rate (inst/s) 8host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1884467398 # Simulator tick rate (ticks/s) 10host_mem_usage 355400 # Number of bytes of host memory used 11host_seconds 192.33 # Real time elapsed on the host |
12sim_insts 243825163 # Number of instructions simulated 13sim_ops 243835278 # Number of ops (including micro ops) simulated |
14system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory 20system.physmem.bytes_written::total 2560 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 40 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s) |
37system.cpu.workload.num_syscalls 443 # Number of system calls 38system.cpu.numCycles 724861774 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 243825163 # Number of instructions committed 42system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 86system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles 87system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) 88system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) 89system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses 90system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses 91system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses 92system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses 93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses |
94system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses |
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses |
96system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses |
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses |
98system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency |
100system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency |
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency |
102system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency |
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency |
104system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency |
105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111system.cpu.icache.fast_writes 0 # number of fast writes performed 112system.cpu.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 118system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles 120system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles 121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles 122system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles 123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles 124system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles 125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses |
126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses |
127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses |
128system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses |
129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses |
130system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses |
131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency |
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency |
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency |
134system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency |
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency |
136system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency |
137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 935475 # number of replacements 139system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use 140system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. 141system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. 143system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 180system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 181system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 182system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 183system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses 184system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses 185system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses 186system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses 187system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses |
188system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses |
189system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses |
190system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses |
191system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses |
192system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses |
193system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses |
194system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses |
195system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses |
196system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses |
197system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency |
198system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency |
199system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency |
200system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency |
201system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency |
202system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency |
203system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency |
204system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency |
205system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency |
206system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency |
207system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 208system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 209system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 210system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 211system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 212system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213system.cpu.dcache.fast_writes 0 # number of fast writes performed 214system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 230system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 231system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 232system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles 233system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles 234system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles 235system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles 236system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles 237system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses |
238system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses |
239system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses |
240system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses |
241system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses |
242system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses |
243system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses |
244system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses |
245system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses |
246system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses |
247system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency |
248system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency |
249system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency |
250system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency |
251system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency |
252system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency |
253system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency |
254system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency |
255system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency |
256system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency |
257system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 258system.cpu.l2cache.replacements 865 # number of replacements 259system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use 260system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks. 261system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks. 262system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks. 263system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 264system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 313system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 314system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 315system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 316system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 317system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 318system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 319system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses 320system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses |
321system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses |
322system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses |
323system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses |
324system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 325system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses |
326system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses |
327system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 328system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses |
329system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses |
330system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 331system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency |
332system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency |
333system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency |
334system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency |
335system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 336system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency |
337system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency |
338system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 339system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency |
340system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency |
341system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.l2cache.fast_writes 0 # number of fast writes performed 348system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 367system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles 368system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles 369system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles 370system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles 371system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles 372system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles 373system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 374system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses |
375system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses |
376system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses |
377system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses |
378system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 379system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses |
380system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses |
381system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 382system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses |
383system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses |
384system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 385system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency |
386system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |
387system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency |
388system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency |
389system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 390system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
391system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
392system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 393system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
394system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
395system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 396 397---------- End Simulation Statistics ---------- |