3,5c3,5
< sim_seconds 0.362429 # Number of seconds simulated
< sim_ticks 362428997000 # Number of ticks simulated
< final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.362482 # Number of seconds simulated
> sim_ticks 362481577000 # Number of ticks simulated
> final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1801112 # Simulator instruction rate (inst/s)
< host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2677225778 # Simulator tick rate (ticks/s)
< host_mem_usage 354292 # Number of bytes of host memory used
< host_seconds 135.37 # Real time elapsed on the host
---
> host_inst_rate 1217197 # Simulator instruction rate (inst/s)
> host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1809539933 # Simulator tick rate (ticks/s)
> host_mem_usage 354248 # Number of bytes of host memory used
> host_seconds 200.32 # Real time elapsed on the host
22,29c22,29
< system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s)
31c31
< system.cpu.numCycles 724857994 # number of cpu cycles simulated
---
> system.cpu.numCycles 724963154 # number of cpu cycles simulated
50c50
< system.cpu.num_busy_cycles 724857994 # Number of busy cycles
---
> system.cpu.num_busy_cycles 724963154 # Number of busy cycles
54c54
< system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use
59,61c59,61
< system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
---
> system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
74,79c74,79
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
92,97c92,97
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency
112,117c112,117
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles
124,129c124,129
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
132c132
< system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use
136,139c136,139
< system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
---
> system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
160,169c160,169
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
190,199c190,199
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency
220,229c220,229
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles
240,249c240,249
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
252c252
< system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use
257,260c257,260
< system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy
263c263
< system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy
< sim_seconds 0.362429 # Number of seconds simulated
< sim_ticks 362428997000 # Number of ticks simulated
< final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.362482 # Number of seconds simulated
> sim_ticks 362481577000 # Number of ticks simulated
> final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1801112 # Simulator instruction rate (inst/s)
< host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2677225778 # Simulator tick rate (ticks/s)
< host_mem_usage 354292 # Number of bytes of host memory used
< host_seconds 135.37 # Real time elapsed on the host
---
> host_inst_rate 1217197 # Simulator instruction rate (inst/s)
> host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1809539933 # Simulator tick rate (ticks/s)
> host_mem_usage 354248 # Number of bytes of host memory used
> host_seconds 200.32 # Real time elapsed on the host
22,29c22,29
< system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s)
31c31
< system.cpu.numCycles 724857994 # number of cpu cycles simulated
---
> system.cpu.numCycles 724963154 # number of cpu cycles simulated
50c50
< system.cpu.num_busy_cycles 724857994 # Number of busy cycles
---
> system.cpu.num_busy_cycles 724963154 # Number of busy cycles
54c54
< system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use
59,61c59,61
< system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
---
> system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
74,79c74,79
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
92,97c92,97
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency
112,117c112,117
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles
124,129c124,129
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
132c132
< system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use
136,139c136,139
< system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
---
> system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
160,169c160,169
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
190,199c190,199
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency
220,229c220,229
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles
240,249c240,249
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
252c252
< system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use
257,260c257,260
< system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy
263c263
< system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy