7,11c7,11
< host_inst_rate 628265 # Simulator instruction rate (inst/s)
< host_op_rate 628291 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 933876298 # Simulator tick rate (ticks/s)
< host_mem_usage 354916 # Number of bytes of host memory used
< host_seconds 388.09 # Real time elapsed on the host
---
> host_inst_rate 1267775 # Simulator instruction rate (inst/s)
> host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
> host_mem_usage 355400 # Number of bytes of host memory used
> host_seconds 192.33 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 1001472 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 2560 # Number of bytes written to this memory
< system.physmem.num_reads 15648 # Number of read requests responded to by this memory
< system.physmem.num_writes 40 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
> system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
80a94
> system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
81a96
> system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
82a98
> system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
83a100
> system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
84a102
> system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
85a104
> system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
106a126
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
107a128
> system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
108a130
> system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
109a132
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
110a134
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
111a136
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
162a188
> system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
163a190
> system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
164a192
> system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
165a194
> system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
166a196
> system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
167a198
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
168a200
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
169a202
> system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
170a204
> system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
171a206
> system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
202a238
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
203a240
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
204a242
> system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
205a244
> system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
206a246
> system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
207a248
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
208a250
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
209a252
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
210a254
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
211a256
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
275a321
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
276a323
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
278a326
> system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
280a329
> system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
282a332
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
283a334
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
285a337
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
287a340
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
321a375
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
322a377
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
324a380
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
326a383
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
328a386
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
329a388
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
331a391
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
333a394
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< host_inst_rate 628265 # Simulator instruction rate (inst/s)
< host_op_rate 628291 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 933876298 # Simulator tick rate (ticks/s)
< host_mem_usage 354916 # Number of bytes of host memory used
< host_seconds 388.09 # Real time elapsed on the host
---
> host_inst_rate 1267775 # Simulator instruction rate (inst/s)
> host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
> host_mem_usage 355400 # Number of bytes of host memory used
> host_seconds 192.33 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 1001472 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 2560 # Number of bytes written to this memory
< system.physmem.num_reads 15648 # Number of read requests responded to by this memory
< system.physmem.num_writes 40 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
> system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
80a94
> system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
81a96
> system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
82a98
> system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
83a100
> system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
84a102
> system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
85a104
> system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
106a126
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
107a128
> system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
108a130
> system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
109a132
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
110a134
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
111a136
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
162a188
> system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
163a190
> system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
164a192
> system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
165a194
> system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
166a196
> system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
167a198
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
168a200
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
169a202
> system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
170a204
> system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
171a206
> system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
202a238
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
203a240
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
204a242
> system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
205a244
> system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
206a246
> system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
207a248
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
208a250
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
209a252
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
210a254
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
211a256
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
275a321
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
276a323
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
278a326
> system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
280a329
> system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
282a332
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
283a334
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
285a337
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
287a340
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
321a375
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
322a377
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
324a380
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
326a383
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
328a386
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
329a388
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
331a391
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
333a394
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency