3,5c3,5
< sim_seconds 0.361598 # Number of seconds simulated
< sim_ticks 361597758500 # Number of ticks simulated
< final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.361613 # Number of seconds simulated
> sim_ticks 361613361500 # Number of ticks simulated
> final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1165746 # Simulator instruction rate (inst/s)
< host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1728825291 # Simulator tick rate (ticks/s)
< host_mem_usage 381188 # Number of bytes of host memory used
< host_seconds 209.16 # Real time elapsed on the host
---
> host_inst_rate 1370596 # Simulator instruction rate (inst/s)
> host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2032709522 # Simulator tick rate (ticks/s)
> host_mem_usage 385816 # Number of bytes of host memory used
> host_seconds 177.90 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 723195517 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 723226723 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use
101,104c101,104
< system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy
106c106
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
109c109
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
113c113
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
134,143c134,143
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles
164,173c164,173
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency
192,201c192,201
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles
212,222c212,222
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
224c224
< system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use
229,231c229,231
< system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy
240c240
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
253,258c253,258
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles
271,276c271,276
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency
291,296c291,296
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles
303,309c303,309
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
311,314c311,314
< system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks.
316,319c316,317
< system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor
321,323c319,321
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id
325,332c323,330
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
361,372c359,370
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles
401,412c399,410
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency
431,442c429,440
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles
455,466c453,464
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
473c471
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
507c505,511
< system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.361598 # Number of seconds simulated
< sim_ticks 361597758500 # Number of ticks simulated
< final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.361613 # Number of seconds simulated
> sim_ticks 361613361500 # Number of ticks simulated
> final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1165746 # Simulator instruction rate (inst/s)
< host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1728825291 # Simulator tick rate (ticks/s)
< host_mem_usage 381188 # Number of bytes of host memory used
< host_seconds 209.16 # Real time elapsed on the host
---
> host_inst_rate 1370596 # Simulator instruction rate (inst/s)
> host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2032709522 # Simulator tick rate (ticks/s)
> host_mem_usage 385816 # Number of bytes of host memory used
> host_seconds 177.90 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 723195517 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 723226723 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use
101,104c101,104
< system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy
106c106
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
109c109
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
113c113
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
134,143c134,143
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles
164,173c164,173
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency
192,201c192,201
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles
212,222c212,222
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
224c224
< system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use
229,231c229,231
< system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy
240c240
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
253,258c253,258
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles
271,276c271,276
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency
291,296c291,296
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles
303,309c303,309
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
311,314c311,314
< system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks.
316,319c316,317
< system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor
321,323c319,321
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id
325,332c323,330
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
361,372c359,370
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles
401,412c399,410
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency
431,442c429,440
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles
455,466c453,464
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
473c471
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
507c505,511
< system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states