4,5c4,5
< sim_ticks 361488535500 # Number of ticks simulated
< final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 361488536500 # Number of ticks simulated
> final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1224088 # Simulator instruction rate (inst/s)
< host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1814798992 # Simulator tick rate (ticks/s)
< host_mem_usage 426288 # Number of bytes of host memory used
< host_seconds 199.19 # Real time elapsed on the host
---
> host_inst_rate 1117046 # Simulator instruction rate (inst/s)
> host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1656101101 # Simulator tick rate (ticks/s)
> host_mem_usage 428664 # Number of bytes of host memory used
> host_seconds 218.28 # Real time elapsed on the host
34c34
< system.cpu.numCycles 722977071 # number of cpu cycles simulated
---
> system.cpu.numCycles 722977073 # number of cpu cycles simulated
53c53
< system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles
93c93
< system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use
97,98c97,98
< system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor
129,130c129,130
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles
135,138c135,138
< system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles
159,160c159,160
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency
165,168c165,168
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency
189,190c189,190
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles
195,198c195,198
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles
209,210c209,210
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency
215,218c215,218
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
221c221
< system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use
226c226
< system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor
307c307
< system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use
312,313c312,313
< system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor
460a461,466
> system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
476,477c482,483
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram
479,480c485,486
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram
483c489
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 361488535500 # Number of ticks simulated
< final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 361488536500 # Number of ticks simulated
> final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1224088 # Simulator instruction rate (inst/s)
< host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1814798992 # Simulator tick rate (ticks/s)
< host_mem_usage 426288 # Number of bytes of host memory used
< host_seconds 199.19 # Real time elapsed on the host
---
> host_inst_rate 1117046 # Simulator instruction rate (inst/s)
> host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1656101101 # Simulator tick rate (ticks/s)
> host_mem_usage 428664 # Number of bytes of host memory used
> host_seconds 218.28 # Real time elapsed on the host
34c34
< system.cpu.numCycles 722977071 # number of cpu cycles simulated
---
> system.cpu.numCycles 722977073 # number of cpu cycles simulated
53c53
< system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles
93c93
< system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use
97,98c97,98
< system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor
129,130c129,130
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles
135,138c135,138
< system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles
159,160c159,160
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency
165,168c165,168
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency
189,190c189,190
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles
195,198c195,198
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles
209,210c209,210
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency
215,218c215,218
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
221c221
< system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use
226c226
< system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor
307c307
< system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use
312,313c312,313
< system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor
460a461,466
> system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
476,477c482,483
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram
479,480c485,486
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram
483c489
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram