4,5c4,5
< sim_ticks 361488530000 # Number of ticks simulated
< final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 361488530500 # Number of ticks simulated
> final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1379749 # Simulator instruction rate (inst/s)
< host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2045576865 # Simulator tick rate (ticks/s)
< host_mem_usage 421936 # Number of bytes of host memory used
< host_seconds 176.72 # Real time elapsed on the host
---
> host_inst_rate 1163469 # Simulator instruction rate (inst/s)
> host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1724927568 # Simulator tick rate (ticks/s)
> host_mem_usage 425840 # Number of bytes of host memory used
> host_seconds 209.57 # Real time elapsed on the host
32,54d31
< system.membus.trans_dist::ReadReq 1036 # Transaction distribution
< system.membus.trans_dist::ReadResp 1036 # Transaction distribution
< system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
< system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 15603 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 15603 # Request fanout histogram
< system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
57c34
< system.cpu.numCycles 722977060 # number of cpu cycles simulated
---
> system.cpu.numCycles 722977061 # number of cpu cycles simulated
76c53
< system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles
114a92,219
> system.cpu.dcache.tags.replacements 935475 # number of replacements
> system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
> system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
> system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
> system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
> system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
> system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
> system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
> system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
> system.cpu.dcache.overall_misses::total 939567 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
> system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
> system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
> system.cpu.dcache.writebacks::total 935266 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
> system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
> system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
> system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
116c221
< system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use
121c226
< system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor
144,149c249,254
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles
162,167c267,272
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency
182,187c287,292
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles
194,199c299,304
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency
202c307
< system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use
207,208c312,313
< system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor
247,257c352,362
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles
282,292c387,397
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency
312,322c417,427
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles
334,344c439,449
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
346,473d450
< system.cpu.dcache.tags.replacements 935475 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
< system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
< system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
< system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
< system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
< system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
< system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
< system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
< system.cpu.dcache.overall_misses::total 939567 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
< system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
< system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
< system.cpu.dcache.writebacks::total 935266 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
< system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
< system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
< system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
502a480,502
> system.membus.trans_dist::ReadReq 1036 # Transaction distribution
> system.membus.trans_dist::ReadResp 1036 # Transaction distribution
> system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
> system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 15603 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 15603 # Request fanout histogram
> system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
< sim_ticks 361488530000 # Number of ticks simulated
< final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 361488530500 # Number of ticks simulated
> final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1379749 # Simulator instruction rate (inst/s)
< host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2045576865 # Simulator tick rate (ticks/s)
< host_mem_usage 421936 # Number of bytes of host memory used
< host_seconds 176.72 # Real time elapsed on the host
---
> host_inst_rate 1163469 # Simulator instruction rate (inst/s)
> host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1724927568 # Simulator tick rate (ticks/s)
> host_mem_usage 425840 # Number of bytes of host memory used
> host_seconds 209.57 # Real time elapsed on the host
32,54d31
< system.membus.trans_dist::ReadReq 1036 # Transaction distribution
< system.membus.trans_dist::ReadResp 1036 # Transaction distribution
< system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
< system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 15603 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 15603 # Request fanout histogram
< system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
57c34
< system.cpu.numCycles 722977060 # number of cpu cycles simulated
---
> system.cpu.numCycles 722977061 # number of cpu cycles simulated
76c53
< system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles
114a92,219
> system.cpu.dcache.tags.replacements 935475 # number of replacements
> system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
> system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
> system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
> system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
> system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
> system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
> system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
> system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
> system.cpu.dcache.overall_misses::total 939567 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
> system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
> system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
> system.cpu.dcache.writebacks::total 935266 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
> system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
> system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
> system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
116c221
< system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use
121c226
< system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor
144,149c249,254
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles
162,167c267,272
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency
182,187c287,292
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles
194,199c299,304
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency
202c307
< system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use
207,208c312,313
< system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor
247,257c352,362
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles
282,292c387,397
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency
312,322c417,427
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles
334,344c439,449
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
346,473d450
< system.cpu.dcache.tags.replacements 935475 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
< system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
< system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
< system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
< system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
< system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
< system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
< system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
< system.cpu.dcache.overall_misses::total 939567 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
< system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
< system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
< system.cpu.dcache.writebacks::total 935266 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
< system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
< system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
< system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
502a480,502
> system.membus.trans_dist::ReadReq 1036 # Transaction distribution
> system.membus.trans_dist::ReadResp 1036 # Transaction distribution
> system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
> system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 15603 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 15603 # Request fanout histogram
> system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.0 # Layer utilization (%)