Cross Reference: /gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11955:1170d039b31e )

full compact

stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361613 # Number of seconds simulated 4sim_ticks 361613361500 # Number of ticks simulated 5final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1844871 # Simulator instruction rate (inst/s) 8host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2736100211 # Simulator tick rate (ticks/s) 10host_mem_usage 385448 # Number of bytes of host memory used 11host_seconds 132.16 # Real time elapsed on the host 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361613 # Number of seconds simulated 4sim_ticks 361613361500 # Number of ticks simulated 5final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1844871 # Simulator instruction rate (inst/s) 8host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2736100211 # Simulator tick rate (ticks/s) 10host_mem_usage 385448 # Number of bytes of host memory used 11host_seconds 132.16 # Real time elapsed on the host 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks
35system.cpu.workload.num_syscalls 443 # Number of system calls	35system.cpu.workload.numSyscalls 443 # Number of system calls
36system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 723226723 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 243825150 # Number of instructions committed 41system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 44system.cpu.num_func_calls 4252956 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 46system.cpu.num_int_insts 194726494 # number of integer instructions 47system.cpu.num_fp_insts 11630 # number of float instructions 48system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 49system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 52system.cpu.num_mem_refs 105711441 # number of memory refs 53system.cpu.num_load_insts 82803521 # Number of load instructions 54system.cpu.num_store_insts 22907920 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 29302884 # Number of branches fetched 60system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 61system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 64system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction 68system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction 69system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction 70system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction 71system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction 72system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction 73system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction 74system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction 75system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction 76system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction 77system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction 78system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction 79system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction 80system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction 81system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction 82system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction 83system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction 84system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction 88system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction 89system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 90system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 91system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 92system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction 93system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction 94system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction 95system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 244431613 # Class of executed instruction 99system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 100system.cpu.dcache.tags.replacements 935475 # number of replacements 101system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use 102system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 103system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 104system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 105system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. 106system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor 107system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy 109system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 114system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 115system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 116system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses 117system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 118system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 119system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 120system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 121system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 122system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 123system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 124system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 127system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 132system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 133system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 134system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 135system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 136system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 137system.cpu.dcache.overall_misses::total 939567 # number of overall misses 138system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles 139system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles 142system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles 143system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles 144system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles 145system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles 146system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles 147system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles 148system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 149system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 150system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 151system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 152system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 153system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 154system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 155system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 156system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 157system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 158system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 159system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 160system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 161system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 162system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 163system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 164system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 165system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 166system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 167system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 168system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency 169system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency 170system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency 171system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency 172system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency 173system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency 174system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency 175system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency 176system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency 177system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency 178system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 180system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 183system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 184system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 185system.cpu.dcache.writebacks::total 935266 # number of writebacks 186system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 187system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 189system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 190system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 191system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles 201system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles 202system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles 203system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles 204system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles 205system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles 206system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 207system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 208system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 209system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 210system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 211system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 212system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 213system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 214system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 215system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 216system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency 217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency 218system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency 219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency 220system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency 221system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency 223system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency 225system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency 226system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 227system.cpu.icache.tags.replacements 25 # number of replacements 228system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use 229system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 230system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 231system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 232system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 233system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor 234system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy 235system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy 236system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 241system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 242system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 243system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses 244system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 245system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 246system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 247system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 248system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 249system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 250system.cpu.icache.overall_hits::total 244420617 # number of overall hits 251system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 252system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 253system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 254system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 255system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 256system.cpu.icache.overall_misses::total 882 # number of overall misses 257system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles 258system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles 259system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles 260system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles 261system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles 262system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles 263system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 265system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 266system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 267system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 268system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 269system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 270system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 271system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 272system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 273system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 274system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 275system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency 276system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency 277system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency 278system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency 279system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency 280system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency 281system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.icache.writebacks::writebacks 25 # number of writebacks 288system.cpu.icache.writebacks::total 25 # number of writebacks 289system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 290system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 291system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 292system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 293system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 294system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 295system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles 296system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles 298system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles 300system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles 301system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 302system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 303system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 304system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 305system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 306system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 307system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency 308system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency 309system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency 310system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency 311system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency 313system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 314system.cpu.l2cache.tags.replacements 0 # number of replacements 315system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use 316system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. 317system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 318system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. 319system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 320system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor 321system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy 324system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 329system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 330system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id 331system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id 332system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses 333system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses 334system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 335system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits 336system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits 337system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits 338system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits 339system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 340system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 341system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 342system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 343system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits 344system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits 345system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 346system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 347system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 348system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 349system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 350system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 351system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 352system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 353system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses 354system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses 355system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses 356system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses 357system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 358system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 359system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 360system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 361system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 362system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 363system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles 364system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles 365system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles 366system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles 367system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles 368system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles 369system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles 370system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles 371system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles 372system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles 373system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles 374system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles 375system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) 376system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) 377system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) 378system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) 379system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 380system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 381system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) 382system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) 383system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) 384system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) 385system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 386system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 387system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 388system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 389system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 390system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 391system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 392system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 393system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses 394system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses 395system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses 396system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses 397system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 398system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 399system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 400system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 401system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 402system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 403system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 404system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 405system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency 406system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency 407system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 408system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 409system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency 410system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 411system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency 412system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency 413system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 414system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency 415system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 422system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 423system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses 424system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses 425system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses 426system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses 427system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 428system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 429system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 430system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 431system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 432system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 433system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles 434system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles 435system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles 436system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles 437system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles 438system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles 439system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles 440system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles 441system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles 442system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles 443system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles 444system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles 445system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 446system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 447system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses 448system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses 449system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses 450system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses 451system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 452system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 453system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 454system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 455system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 456system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 457system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 458system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 459system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency 460system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency 461system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 462system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 463system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency 464system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency 467system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 468system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency 469system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 470system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 471system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 472system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 473system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 474system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 475system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 476system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution 484system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) 485system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) 486system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) 487system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) 488system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 489system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) 490system.cpu.toL2Bus.snoops 0 # Total snoops (count) 491system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 492system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 501system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram 503system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) 504system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 505system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 506system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 507system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 508system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 509system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. 510system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 511system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 512system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 513system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 514system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 515system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 516system.membus.trans_dist::ReadResp 1036 # Transaction distribution 517system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 518system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 519system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution 520system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 521system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 522system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 523system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 524system.membus.snoops 0 # Total snoops (count) 525system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 526system.membus.snoop_fanout::samples 15603 # Request fanout histogram 527system.membus.snoop_fanout::mean 0 # Request fanout histogram 528system.membus.snoop_fanout::stdev 0 # Request fanout histogram 529system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 530system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram 531system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 532system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 533system.membus.snoop_fanout::min_value 0 # Request fanout histogram 534system.membus.snoop_fanout::max_value 0 # Request fanout histogram 535system.membus.snoop_fanout::total 15603 # Request fanout histogram 536system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) 537system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 538system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) 539system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 540 541---------- End Simulation Statistics ----------	36system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 723226723 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 243825150 # Number of instructions committed 41system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 44system.cpu.num_func_calls 4252956 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 46system.cpu.num_int_insts 194726494 # number of integer instructions 47system.cpu.num_fp_insts 11630 # number of float instructions 48system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 49system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 52system.cpu.num_mem_refs 105711441 # number of memory refs 53system.cpu.num_load_insts 82803521 # Number of load instructions 54system.cpu.num_store_insts 22907920 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 29302884 # Number of branches fetched 60system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 61system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 64system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction 68system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction 69system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction 70system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction 71system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction 72system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction 73system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction 74system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction 75system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction 76system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction 77system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction 78system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction 79system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction 80system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction 81system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction 82system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction 83system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction 84system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction 88system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction 89system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 90system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 91system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 92system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction 93system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction 94system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction 95system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 244431613 # Class of executed instruction 99system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 100system.cpu.dcache.tags.replacements 935475 # number of replacements 101system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use 102system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 103system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 104system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 105system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. 106system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor 107system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy 109system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 114system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 115system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 116system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses 117system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 118system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 119system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 120system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 121system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 122system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 123system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 124system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 127system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 132system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 133system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 134system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 135system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 136system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 137system.cpu.dcache.overall_misses::total 939567 # number of overall misses 138system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles 139system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles 142system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles 143system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles 144system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles 145system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles 146system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles 147system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles 148system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 149system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 150system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 151system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 152system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 153system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 154system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 155system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 156system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 157system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 158system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 159system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 160system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 161system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 162system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 163system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 164system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 165system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 166system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 167system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 168system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency 169system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency 170system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency 171system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency 172system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency 173system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency 174system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency 175system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency 176system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency 177system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency 178system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 180system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 183system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 184system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 185system.cpu.dcache.writebacks::total 935266 # number of writebacks 186system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 187system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 189system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 190system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 191system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles 201system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles 202system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles 203system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles 204system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles 205system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles 206system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 207system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 208system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 209system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 210system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 211system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 212system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 213system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 214system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 215system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 216system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency 217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency 218system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency 219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency 220system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency 221system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency 223system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency 225system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency 226system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 227system.cpu.icache.tags.replacements 25 # number of replacements 228system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use 229system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 230system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 231system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 232system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 233system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor 234system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy 235system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy 236system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 241system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 242system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 243system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses 244system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 245system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 246system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 247system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 248system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 249system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 250system.cpu.icache.overall_hits::total 244420617 # number of overall hits 251system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 252system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 253system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 254system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 255system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 256system.cpu.icache.overall_misses::total 882 # number of overall misses 257system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles 258system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles 259system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles 260system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles 261system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles 262system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles 263system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 265system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 266system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 267system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 268system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 269system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 270system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 271system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 272system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 273system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 274system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 275system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency 276system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency 277system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency 278system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency 279system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency 280system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency 281system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.icache.writebacks::writebacks 25 # number of writebacks 288system.cpu.icache.writebacks::total 25 # number of writebacks 289system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 290system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 291system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 292system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 293system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 294system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 295system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles 296system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles 298system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles 300system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles 301system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 302system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 303system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 304system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 305system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 306system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 307system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency 308system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency 309system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency 310system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency 311system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency 313system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 314system.cpu.l2cache.tags.replacements 0 # number of replacements 315system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use 316system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. 317system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 318system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. 319system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 320system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor 321system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy 324system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 329system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 330system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id 331system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id 332system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses 333system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses 334system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 335system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits 336system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits 337system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits 338system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits 339system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 340system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 341system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 342system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 343system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits 344system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits 345system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 346system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 347system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 348system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 349system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 350system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 351system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 352system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 353system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses 354system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses 355system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses 356system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses 357system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 358system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 359system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 360system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 361system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 362system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 363system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles 364system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles 365system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles 366system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles 367system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles 368system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles 369system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles 370system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles 371system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles 372system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles 373system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles 374system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles 375system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) 376system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) 377system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) 378system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) 379system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 380system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 381system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) 382system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) 383system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) 384system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) 385system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 386system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 387system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 388system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 389system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 390system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 391system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 392system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 393system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses 394system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses 395system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses 396system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses 397system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 398system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 399system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 400system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 401system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 402system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 403system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 404system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 405system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency 406system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency 407system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 408system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 409system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency 410system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 411system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency 412system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency 413system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 414system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency 415system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 422system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 423system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses 424system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses 425system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses 426system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses 427system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 428system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 429system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 430system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 431system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 432system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 433system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles 434system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles 435system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles 436system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles 437system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles 438system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles 439system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles 440system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles 441system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles 442system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles 443system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles 444system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles 445system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 446system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 447system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses 448system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses 449system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses 450system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses 451system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 452system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 453system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 454system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 455system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 456system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 457system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 458system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 459system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency 460system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency 461system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 462system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 463system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency 464system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency 467system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 468system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency 469system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 470system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 471system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 472system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 473system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 474system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 475system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 476system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution 484system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) 485system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) 486system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) 487system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) 488system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 489system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) 490system.cpu.toL2Bus.snoops 0 # Total snoops (count) 491system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 492system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 501system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram 503system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) 504system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 505system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 506system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 507system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 508system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 509system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. 510system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 511system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 512system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 513system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 514system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 515system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states 516system.membus.trans_dist::ReadResp 1036 # Transaction distribution 517system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 518system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 519system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution 520system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 521system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 522system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 523system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 524system.membus.snoops 0 # Total snoops (count) 525system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 526system.membus.snoop_fanout::samples 15603 # Request fanout histogram 527system.membus.snoop_fanout::mean 0 # Request fanout histogram 528system.membus.snoop_fanout::stdev 0 # Request fanout histogram 529system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 530system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram 531system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 532system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 533system.membus.snoop_fanout::min_value 0 # Request fanout histogram 534system.membus.snoop_fanout::max_value 0 # Request fanout histogram 535system.membus.snoop_fanout::total 15603 # Request fanout histogram 536system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) 537system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 538system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) 539system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 540 541---------- End Simulation Statistics ----------