Cross Reference: /gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361598 # Number of seconds simulated 4sim_ticks 361597758500 # Number of ticks simulated 5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361598 # Number of seconds simulated 4sim_ticks 361597758500 # Number of ticks simulated 5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 779266 # Simulator instruction rate (inst/s) 8host_op_rate 779298 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1155667536 # Simulator tick rate (ticks/s) 10host_mem_usage 379236 # Number of bytes of host memory used 11host_seconds 312.89 # Real time elapsed on the host	7host_inst_rate 1652209 # Simulator instruction rate (inst/s) 8host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2450259534 # Simulator tick rate (ticks/s) 10host_mem_usage 427260 # Number of bytes of host memory used 11host_seconds 147.58 # Real time elapsed on the host
12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
	33system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 443 # Number of system calls	34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 443 # Number of system calls
	36system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
34system.cpu.numCycles 723195517 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 243825150 # Number of instructions committed 38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 41system.cpu.num_func_calls 4252956 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 43system.cpu.num_int_insts 194726494 # number of integer instructions 44system.cpu.num_fp_insts 11630 # number of float instructions 45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 49system.cpu.num_mem_refs 105711441 # number of memory refs 50system.cpu.num_load_insts 82803521 # Number of load instructions 51system.cpu.num_store_insts 22907920 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 53system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 29302884 # Number of branches fetched 57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction 62system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction 63system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction 64system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction 65system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction 66system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction 67system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction 68system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction 69system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction 70system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction 71system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction 72system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction 73system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction 74system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction 75system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction 76system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction 77system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction 78system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction 79system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction 80system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction 81system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction 82system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction 83system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction 84system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 244431613 # Class of executed instruction	37system.cpu.numCycles 723195517 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 243825150 # Number of instructions committed 41system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 44system.cpu.num_func_calls 4252956 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 46system.cpu.num_int_insts 194726494 # number of integer instructions 47system.cpu.num_fp_insts 11630 # number of float instructions 48system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 49system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 52system.cpu.num_mem_refs 105711441 # number of memory refs 53system.cpu.num_load_insts 82803521 # Number of load instructions 54system.cpu.num_store_insts 22907920 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 29302884 # Number of branches fetched 60system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 61system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 64system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction 68system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction 69system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction 70system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction 71system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction 72system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction 73system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction 74system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction 75system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction 76system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction 77system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction 78system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction 79system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction 80system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction 81system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction 82system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction 83system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction 84system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 90system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 91system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 244431613 # Class of executed instruction
	95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
92system.cpu.dcache.tags.replacements 935475 # number of replacements 93system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 107system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 108system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses	96system.cpu.dcache.tags.replacements 935475 # number of replacements 97system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use 98system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. 102system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy 105system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 110system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 111system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 112system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
	113system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
109system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 110system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 111system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 112system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 113system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 114system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 115system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 116system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 117system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 118system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 119system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 120system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 128system.cpu.dcache.overall_misses::total 939567 # number of overall misses 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles 130system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles 133system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles 134system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles 135system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles 136system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles 137system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles 138system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles 139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 147system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 148system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 149system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 150system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency 163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency 164system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency 166system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 176system.cpu.dcache.writebacks::total 935266 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 181system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 182system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 183system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 184system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 185system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 186system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 187system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles 188system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles 189system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles 190system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles 191system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles 192system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles 193system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles 194system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles 195system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles 196system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 198system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 199system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 200system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 201system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 202system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 203system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 204system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 205system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 206system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency 209system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency 211system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency 212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 214system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 216system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency	114system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 115system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 116system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 117system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 118system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 119system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 120system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 121system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 122system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 123system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 124system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 125system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 126system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 127system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 128system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 129system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 130system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 131system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 132system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 133system.cpu.dcache.overall_misses::total 939567 # number of overall misses 134system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles 135system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles 136system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles 138system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles 139system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 149system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 150system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 151system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 152system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 153system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 155system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 156system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 157system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 158system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 159system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 160system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 161system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 162system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 163system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 164system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency 165system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency 166system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency 167system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency 168system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency 170system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency 171system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency 172system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency 174system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 181system.cpu.dcache.writebacks::total 935266 # number of writebacks 182system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 183system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 184system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 186system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 187system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 188system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 189system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 190system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 191system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles 194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles 195system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles 196system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles 197system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles 198system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles 199system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles 200system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles 201system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles 202system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 203system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 204system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 205system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 206system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 207system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 209system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 211system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency 216system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency 218system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency 220system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
	222system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
217system.cpu.icache.tags.replacements 25 # number of replacements 218system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use 219system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 223system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy 226system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 229system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 231system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 232system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 233system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses	223system.cpu.icache.tags.replacements 25 # number of replacements 224system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use 225system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 226system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 227system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 228system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 229system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor 230system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy 231system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 237system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 238system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 239system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
	240system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
234system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 235system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 236system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 237system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 238system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 239system.cpu.icache.overall_hits::total 244420617 # number of overall hits 240system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 241system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 242system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 243system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 244system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 245system.cpu.icache.overall_misses::total 882 # number of overall misses 246system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles 247system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles 248system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles 249system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles 250system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles 251system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles 252system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 253system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 254system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 255system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 256system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 257system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 258system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 259system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 260system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 261system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 262system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 263system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 264system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency 265system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency 266system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency 267system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency 268system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency 269system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.cpu.icache.writebacks::writebacks 25 # number of writebacks 277system.cpu.icache.writebacks::total 25 # number of writebacks 278system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 279system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 280system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 281system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 282system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 283system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 284system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles 285system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles 286system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles 287system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles 288system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles 289system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles 290system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 291system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 292system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 293system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 294system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 295system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency 297system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 299system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 301system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency	241system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 242system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 243system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 244system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 245system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 246system.cpu.icache.overall_hits::total 244420617 # number of overall hits 247system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 248system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 249system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 250system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 251system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 252system.cpu.icache.overall_misses::total 882 # number of overall misses 253system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles 254system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles 255system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles 256system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles 257system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles 258system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles 259system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 261system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 262system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 263system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 264system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 265system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 266system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 267system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 268system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 269system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 270system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 271system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency 272system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency 273system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency 274system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency 275system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency 276system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency 277system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 282system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 283system.cpu.icache.writebacks::writebacks 25 # number of writebacks 284system.cpu.icache.writebacks::total 25 # number of writebacks 285system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 286system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 287system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 288system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 289system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 290system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 291system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles 292system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles 293system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles 294system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles 295system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles 296system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles 297system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 298system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 299system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 300system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 301system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 302system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency 304system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 306system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency 308system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
	309system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
302system.cpu.l2cache.tags.replacements 0 # number of replacements 303system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use 304system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 305system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 308system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor 310system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor 311system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy 312system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 313system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 314system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy 315system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id 321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id 322system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses 323system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses	310system.cpu.l2cache.tags.replacements 0 # number of replacements 311system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use 312system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. 313system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 314system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. 315system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 316system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor 318system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy 320system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 322system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id 329system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id 330system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses 331system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
	332system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
324system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits 325system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits 326system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits 327system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits 328system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 329system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 330system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 331system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 332system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits 333system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits 334system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 335system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 336system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 337system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 338system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 339system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 340system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 341system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 342system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses 343system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses 344system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses 345system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses 346system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 347system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 348system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 349system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 350system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 351system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 352system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles 353system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles 354system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles 355system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles 356system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles 357system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles 358system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles 359system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles 360system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles 361system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles 362system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles 363system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles 364system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) 365system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) 366system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) 367system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) 368system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 369system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 370system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) 371system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) 372system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) 373system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) 374system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 375system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 376system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 377system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 378system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 379system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 380system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 381system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 382system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses 383system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses 384system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses 385system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses 386system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 387system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 388system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 389system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 390system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 391system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 392system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 393system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 394system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency 395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency 396system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 398system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency 399system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 400system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency 401system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency 402system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency 404system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 410system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 411system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 412system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses 413system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses 414system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses 415system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses 416system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 417system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 418system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 419system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 420system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 421system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 422system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles 423system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles 424system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles 425system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles 426system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles 427system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles 428system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles 429system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles 430system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles 431system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles 432system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles 433system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles 434system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 435system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 436system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses 437system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses 438system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses 439system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses 440system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 441system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 442system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 443system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 444system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 445system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 446system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 447system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 448system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency 449system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency 450system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 451system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 457system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 458system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 461system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	333system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits 334system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits 335system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits 336system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits 337system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 338system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 339system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 340system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 341system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits 342system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits 343system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 344system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 345system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 346system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 347system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 348system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 349system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 350system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 351system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses 352system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses 353system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses 354system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses 355system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 356system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 357system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 358system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 359system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 360system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 361system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles 362system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles 363system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles 364system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles 365system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles 366system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles 367system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles 368system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles 369system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles 370system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles 371system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles 372system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles 373system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) 374system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) 375system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) 376system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) 377system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 378system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 379system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) 380system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) 381system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) 382system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) 383system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 384system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 385system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 386system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 387system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 388system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 389system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 390system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 391system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses 392system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses 393system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses 394system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses 395system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 396system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 397system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 398system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 399system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 400system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 401system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 402system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 403system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency 404system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency 405system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 406system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 407system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency 408system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 409system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency 410system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency 411system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 412system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency 413system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 420system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 421system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses 422system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses 423system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses 424system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses 425system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 426system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 427system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 428system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 429system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 430system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 431system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles 432system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles 433system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles 434system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles 435system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles 436system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles 437system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles 438system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles 439system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles 440system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles 441system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles 442system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles 443system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 444system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 445system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses 446system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses 447system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses 448system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses 449system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 450system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 451system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 452system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 453system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 454system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 455system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 456system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 457system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency 458system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency 459system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 460system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 461system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 462system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 463system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 464system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency 465system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency 467system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 468system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. 469system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 471system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 472system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	473system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
464system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution 472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) 478system.cpu.toL2Bus.snoops 0 # Total snoops (count) 479system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram 490system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) 491system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 494system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 495system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)	474system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution 482system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) 485system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 487system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) 488system.cpu.toL2Bus.snoops 0 # Total snoops (count) 489system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram 500system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) 501system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 502system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 503system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 504system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 505system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
	506system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
496system.membus.trans_dist::ReadResp 1036 # Transaction distribution 497system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 498system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 499system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution 500system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 501system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 502system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 503system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 504system.membus.snoops 0 # Total snoops (count) 505system.membus.snoop_fanout::samples 15603 # Request fanout histogram 506system.membus.snoop_fanout::mean 0 # Request fanout histogram 507system.membus.snoop_fanout::stdev 0 # Request fanout histogram 508system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 509system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram 510system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 511system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 512system.membus.snoop_fanout::min_value 0 # Request fanout histogram 513system.membus.snoop_fanout::max_value 0 # Request fanout histogram 514system.membus.snoop_fanout::total 15603 # Request fanout histogram 515system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) 516system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 517system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) 518system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 519 520---------- End Simulation Statistics ----------	507system.membus.trans_dist::ReadResp 1036 # Transaction distribution 508system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 509system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 510system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution 511system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 512system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 513system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 514system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 515system.membus.snoops 0 # Total snoops (count) 516system.membus.snoop_fanout::samples 15603 # Request fanout histogram 517system.membus.snoop_fanout::mean 0 # Request fanout histogram 518system.membus.snoop_fanout::stdev 0 # Request fanout histogram 519system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 520system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram 521system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 522system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 523system.membus.snoop_fanout::min_value 0 # Request fanout histogram 524system.membus.snoop_fanout::max_value 0 # Request fanout histogram 525system.membus.snoop_fanout::total 15603 # Request fanout histogram 526system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) 527system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 528system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) 529system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 530 531---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.361598 # Number of seconds simulated
4sim_ticks 361597758500 # Number of ticks simulated
5final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 779266 # Simulator instruction rate (inst/s)
8host_op_rate 779298 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1155667536 # Simulator tick rate (ticks/s)
10host_mem_usage 379236 # Number of bytes of host memory used
11host_seconds 312.89 # Real time elapsed on the host

7host_inst_rate 1652209 # Simulator instruction rate (inst/s)
8host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2450259534 # Simulator tick rate (ticks/s)
10host_mem_usage 427260 # Number of bytes of host memory used
11host_seconds 147.58 # Real time elapsed on the host

12sim_insts 243825150 # Number of instructions simulated
13sim_ops 243835265 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
19system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)

33system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 443 # Number of system calls

34system.cpu_clk_domain.clock 500 # Clock period in ticks
35system.cpu.workload.num_syscalls 443 # Number of system calls

36system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states

34system.cpu.numCycles 723195517 # number of cpu cycles simulated
35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 243825150 # Number of instructions committed
38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
41system.cpu.num_func_calls 4252956 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
43system.cpu.num_int_insts 194726494 # number of integer instructions
44system.cpu.num_fp_insts 11630 # number of float instructions
45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
49system.cpu.num_mem_refs 105711441 # number of memory refs
50system.cpu.num_load_insts 82803521 # Number of load instructions
51system.cpu.num_store_insts 22907920 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
53system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 29302884 # Number of branches fetched
57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
62system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
63system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
64system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
65system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
66system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
67system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
68system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
69system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
70system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
71system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
72system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
73system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
74system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
75system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
76system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
77system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
78system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
79system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
80system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
81system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
82system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
83system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
84system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 244431613 # Class of executed instruction

37system.cpu.numCycles 723195517 # number of cpu cycles simulated
38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
40system.cpu.committedInsts 243825150 # Number of instructions committed
41system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
42system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
43system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
44system.cpu.num_func_calls 4252956 # number of times a function call or return occured
45system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
46system.cpu.num_int_insts 194726494 # number of integer instructions
47system.cpu.num_fp_insts 11630 # number of float instructions
48system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
49system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
50system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
51system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
52system.cpu.num_mem_refs 105711441 # number of memory refs
53system.cpu.num_load_insts 82803521 # Number of load instructions
54system.cpu.num_store_insts 22907920 # Number of store instructions
55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
56system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
59system.cpu.Branches 29302884 # Number of branches fetched
60system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
61system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
62system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
63system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
64system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
65system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
66system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
67system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
68system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
69system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
70system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
71system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
72system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
73system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
74system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
75system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
76system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
77system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
78system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
79system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
80system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
81system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
82system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
83system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
84system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
85system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
86system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
87system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
89system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
90system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
91system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
94system.cpu.op_class::total 244431613 # Class of executed instruction

95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

92system.cpu.dcache.tags.replacements 935475 # number of replacements
93system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
97system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
99system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
107system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
108system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses

96system.cpu.dcache.tags.replacements 935475 # number of replacements
97system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
98system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
99system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
100system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
101system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
102system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
103system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
104system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
105system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
106system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
107system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
108system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
109system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
110system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
111system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
112system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses

113system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

109system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
110system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
111system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
112system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
113system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
114system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
115system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
116system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
117system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
118system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
119system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
120system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
128system.cpu.dcache.overall_misses::total 939567 # number of overall misses
129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
130system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
132system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
133system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
134system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
135system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
136system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
137system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
138system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
147system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
148system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
149system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
150system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
160system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
162system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
164system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
166system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
168system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
175system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
176system.cpu.dcache.writebacks::total 935266 # number of writebacks
177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
178system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
180system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
181system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
182system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
183system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
184system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
185system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
186system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
187system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
188system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
189system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
190system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
191system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
192system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
193system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
194system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
195system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
196system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
197system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
198system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
199system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
200system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
201system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
202system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
203system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
204system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
205system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
206system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
209system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
211system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
214system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
216system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency

114system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
115system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
116system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
117system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
118system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
119system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
120system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
121system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
122system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
123system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
124system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
125system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
126system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
127system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
128system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
129system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
130system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
131system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
132system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
133system.cpu.dcache.overall_misses::total 939567 # number of overall misses
134system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
135system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
136system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
137system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
138system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
139system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
140system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
141system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
142system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
143system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
144system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
145system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
146system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
147system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
148system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
149system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
150system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
151system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
152system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
153system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
155system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
156system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
157system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
158system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
159system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
160system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
161system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
162system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
163system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
164system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
165system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
166system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
167system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
168system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
169system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
170system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
171system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
172system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
173system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
174system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
175system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
176system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
177system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
178system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
179system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
180system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
181system.cpu.dcache.writebacks::total 935266 # number of writebacks
182system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
183system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
184system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
185system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
186system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
187system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
188system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
189system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
190system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
191system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
193system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
196system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
197system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
198system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
199system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
200system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
201system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
202system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
203system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
204system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
205system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
206system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
207system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
209system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
211system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
216system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
218system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
219system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
220system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
221system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency

222system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

217system.cpu.icache.tags.replacements 25 # number of replacements
218system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
219system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
220system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
221system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
223system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
224system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
225system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
226system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
227system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
228system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
229system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
230system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
231system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
232system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
233system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses

223system.cpu.icache.tags.replacements 25 # number of replacements
224system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
225system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
226system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
227system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
228system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
229system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
230system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
231system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
232system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
233system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
234system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
235system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
236system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
237system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
238system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
239system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses

240system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

234system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
235system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
236system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
237system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
238system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
239system.cpu.icache.overall_hits::total 244420617 # number of overall hits
240system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
241system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
242system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
243system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
244system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
245system.cpu.icache.overall_misses::total 882 # number of overall misses
246system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
247system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
248system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
249system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
250system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
251system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
252system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
253system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
254system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
255system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
256system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
257system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
258system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
259system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
260system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
261system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
262system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
263system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
264system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
265system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
266system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
267system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
268system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
269system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
276system.cpu.icache.writebacks::writebacks 25 # number of writebacks
277system.cpu.icache.writebacks::total 25 # number of writebacks
278system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
279system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
280system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
281system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
282system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
283system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
284system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
285system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
286system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
287system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
288system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
289system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
290system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
291system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
292system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
293system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
294system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
295system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
296system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
297system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
298system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
299system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
300system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
301system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency

241system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
242system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
243system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
244system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
245system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
246system.cpu.icache.overall_hits::total 244420617 # number of overall hits
247system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
248system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
249system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
250system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
251system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
252system.cpu.icache.overall_misses::total 882 # number of overall misses
253system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
254system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
255system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
256system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
257system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
258system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
259system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
260system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
261system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
262system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
263system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
264system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
265system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
266system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
267system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
268system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
269system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
270system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
271system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
272system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
273system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
274system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
275system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
276system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
277system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
279system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
280system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
281system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
282system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
283system.cpu.icache.writebacks::writebacks 25 # number of writebacks
284system.cpu.icache.writebacks::total 25 # number of writebacks
285system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
286system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
287system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
288system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
289system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
290system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
291system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
292system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
293system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
294system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
295system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
296system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
297system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
298system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
299system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
300system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
301system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
302system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
303system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
304system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
305system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
306system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
307system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
308system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency

309system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

302system.cpu.l2cache.tags.replacements 0 # number of replacements
303system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
304system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
305system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
306system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
308system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
310system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
311system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
312system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
313system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
314system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
315system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
322system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
323system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses

310system.cpu.l2cache.tags.replacements 0 # number of replacements
311system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
312system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
313system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
314system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
315system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
316system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
317system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
318system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
319system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
320system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
321system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
322system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
323system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
326system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
327system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
328system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
329system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
330system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
331system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses

332system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

324system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
325system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
326system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
327system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
328system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
329system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
330system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
331system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
332system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
333system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
334system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
335system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
336system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
337system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
338system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
339system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
340system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
341system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
342system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
343system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
344system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
345system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
346system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
347system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
348system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
349system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
350system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
351system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
352system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
353system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
354system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
355system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
356system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
357system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
358system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
359system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
360system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
361system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
362system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
363system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
364system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
365system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
366system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
367system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
368system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
369system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
370system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
371system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
372system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
373system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
374system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
375system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
376system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
377system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
378system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
379system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
380system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
381system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
382system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
383system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
384system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
385system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
386system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
387system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
388system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
389system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
390system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
391system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
392system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
393system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
394system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
396system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
398system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
399system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
400system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
401system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
402system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
403system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
404system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
405system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
406system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
407system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
408system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
409system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
410system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
411system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
412system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
413system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
414system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
415system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
416system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
417system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
418system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
419system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
420system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
421system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
422system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
423system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
424system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
425system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
426system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
427system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
428system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
429system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
430system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
431system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
432system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
433system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
434system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
435system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
436system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
437system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
438system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
439system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
440system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
441system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
442system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
443system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
444system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
445system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
446system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
447system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
448system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
449system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
450system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
451system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
457system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
458system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
459system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
460system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
461system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
462system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
463system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

333system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
334system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
335system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
336system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
337system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
338system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
339system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
340system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
341system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
342system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
343system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
344system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
345system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
346system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
347system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
348system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
349system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
350system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
351system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
352system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
353system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
354system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
355system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
356system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
357system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
358system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
359system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
360system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
361system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
362system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
363system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
364system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
365system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
366system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
367system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
368system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
369system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
370system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
371system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
372system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
373system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
374system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
375system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
376system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
377system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
378system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
379system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
380system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
381system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
382system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
383system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
384system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
385system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
386system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
387system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
388system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
389system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
390system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
391system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
392system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
393system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
394system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
395system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
396system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
397system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
398system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
399system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
400system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
401system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
402system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
403system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
404system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
405system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
406system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
407system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
408system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
409system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
410system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
411system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
412system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
413system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
414system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
415system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
416system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
417system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
418system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
419system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
420system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
421system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
422system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
423system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
424system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
425system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
426system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
427system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
428system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
429system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
430system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
431system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
432system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
433system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
434system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
435system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
436system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
437system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
438system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
439system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
440system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
441system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
442system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
443system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
444system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
445system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
446system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
447system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
448system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
449system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
450system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
451system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
452system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
453system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
454system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
455system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
456system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
457system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
458system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
459system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
460system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
461system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
462system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
463system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
464system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
465system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
466system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
467system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
468system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
469system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
470system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
471system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
472system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

473system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states

464system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
465system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
466system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
467system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
468system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
474system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
475system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
476system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
477system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
478system.cpu.toL2Bus.snoops 0 # Total snoops (count)
479system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
487system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
488system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
489system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
490system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
491system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
492system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
493system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
494system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
495system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

474system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
475system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
476system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
477system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
478system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
479system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
480system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
481system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
482system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
483system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
484system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
485system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
486system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
487system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
488system.cpu.toL2Bus.snoops 0 # Total snoops (count)
489system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
490system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
492system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
493system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
494system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
495system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
496system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
497system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
498system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
499system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
500system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
501system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
502system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
503system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
504system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
505system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

506system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states