1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.361489 # Number of seconds simulated
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.361489 # Number of seconds simulated
|
4sim_ticks 361488535500 # Number of ticks simulated
5final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 4sim_ticks 361488536500 # Number of ticks simulated
5final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1224088 # Simulator instruction rate (inst/s)
8host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1814798992 # Simulator tick rate (ticks/s)
10host_mem_usage 426288 # Number of bytes of host memory used
11host_seconds 199.19 # Real time elapsed on the host
| 7host_inst_rate 1117046 # Simulator instruction rate (inst/s)
8host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1656101101 # Simulator tick rate (ticks/s)
10host_mem_usage 428664 # Number of bytes of host memory used
11host_seconds 218.28 # Real time elapsed on the host
|
12sim_insts 243825150 # Number of instructions simulated
13sim_ops 243835265 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 443 # Number of system calls
| 12sim_insts 243825150 # Number of instructions simulated
13sim_ops 243835265 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 443 # Number of system calls
|
34system.cpu.numCycles 722977071 # number of cpu cycles simulated
| 34system.cpu.numCycles 722977073 # number of cpu cycles simulated
|
35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 243825150 # Number of instructions committed
38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
41system.cpu.num_func_calls 4252956 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
43system.cpu.num_int_insts 194726494 # number of integer instructions
44system.cpu.num_fp_insts 11630 # number of float instructions
45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
49system.cpu.num_mem_refs 105711441 # number of memory refs
50system.cpu.num_load_insts 82803521 # Number of load instructions
51system.cpu.num_store_insts 22907920 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
| 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 243825150 # Number of instructions committed
38system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
41system.cpu.num_func_calls 4252956 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
43system.cpu.num_int_insts 194726494 # number of integer instructions
44system.cpu.num_fp_insts 11630 # number of float instructions
45system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
46system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
49system.cpu.num_mem_refs 105711441 # number of memory refs
50system.cpu.num_load_insts 82803521 # Number of load instructions
51system.cpu.num_store_insts 22907920 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
53system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles
| 53system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles
|
54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 29302884 # Number of branches fetched
57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
62system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
63system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
64system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
65system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
66system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
67system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
68system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
69system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
70system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
71system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
72system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
73system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
74system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
75system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
76system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
77system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
78system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
79system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
80system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
81system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
82system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
83system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
84system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 244431613 # Class of executed instruction
92system.cpu.dcache.tags.replacements 935475 # number of replacements
| 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 29302884 # Number of branches fetched
57system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
58system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
61system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
62system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
63system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
64system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
65system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
66system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
67system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
68system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
69system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
70system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
71system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
72system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
73system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
74system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
75system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
76system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
77system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
78system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
79system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
80system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
81system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
82system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
83system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
84system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
87system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
88system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 244431613 # Class of executed instruction
92system.cpu.dcache.tags.replacements 935475 # number of replacements
|
93system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use
| 93system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use
|
94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
| 94system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
97system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit.
98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor
| 97system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit.
98system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor
|
99system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
107system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
108system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
109system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
110system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
111system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
112system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
113system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
114system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
115system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
116system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
117system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
118system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
119system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
120system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
128system.cpu.dcache.overall_misses::total 939567 # number of overall misses
| 99system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
104system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
105system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
106system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
107system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
108system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
109system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
110system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
111system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
112system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
113system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
114system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
115system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
116system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
117system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
118system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
119system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
120system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
121system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
122system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
123system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
124system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
125system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
126system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
127system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
128system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
130system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
| 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles
130system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles
|
131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
132system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
133system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
134system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
| 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
132system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
133system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
134system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
|
135system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
136system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
137system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
138system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
| 135system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles
136system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles
137system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles
138system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles
|
139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
147system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
148system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
149system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
150system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
| 139system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
140system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
141system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
142system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
143system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
144system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
145system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
146system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
147system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
148system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
149system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
150system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
151system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
152system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
153system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
154system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
155system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
156system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
157system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
158system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
160system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
| 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency
160system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency
|
161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
162system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
164system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
| 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
162system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
163system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
164system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
|
165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
166system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
168system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
| 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
166system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency
167system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
168system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency
|
169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
175system.cpu.dcache.fast_writes 0 # number of fast writes performed
176system.cpu.dcache.cache_copies 0 # number of cache copies performed
177system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
178system.cpu.dcache.writebacks::total 935266 # number of writebacks
179system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
180system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
182system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
183system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
184system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
185system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
186system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
187system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
188system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
| 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
175system.cpu.dcache.fast_writes 0 # number of fast writes performed
176system.cpu.dcache.cache_copies 0 # number of cache copies performed
177system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
178system.cpu.dcache.writebacks::total 935266 # number of writebacks
179system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
180system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
182system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
183system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
184system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
185system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
186system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
187system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
188system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles
190system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles
| 189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles
190system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles
|
191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles
192system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles
193system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles
194system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles
| 191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles
192system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles
193system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles
194system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles
|
195system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles
196system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles
197system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles
198system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles
| 195system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles
196system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles
197system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles
198system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles
|
199system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
200system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
201system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
202system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
203system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
204system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
206system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
207system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
208system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
| 199system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
200system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
201system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
202system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
203system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
204system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
206system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
207system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
208system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency
210system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency
| 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency
210system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency
|
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency
212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency
213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency
214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency
| 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency
212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency
213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency
214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency
|
215system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
216system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
217system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
218system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
| 215system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
216system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
217system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
218system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
|
219system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
220system.cpu.icache.tags.replacements 25 # number of replacements
| 219system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
220system.cpu.icache.tags.replacements 25 # number of replacements
|
221system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use
| 221system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use
|
222system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
223system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
224system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
225system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 222system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
223system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
224system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
225system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
226system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor
| 226system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor
|
227system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
228system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
229system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
230system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
231system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
232system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
233system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
234system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
235system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
236system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
237system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
238system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
239system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
240system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
241system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
242system.cpu.icache.overall_hits::total 244420617 # number of overall hits
243system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
244system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
245system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
246system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
247system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
248system.cpu.icache.overall_misses::total 882 # number of overall misses
249system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles
250system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles
251system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles
252system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles
253system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles
254system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles
255system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
256system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
257system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
258system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
259system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
260system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
261system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
262system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
263system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
264system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
265system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
266system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
267system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency
268system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency
269system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency
270system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency
271system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency
272system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency
273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279system.cpu.icache.fast_writes 0 # number of fast writes performed
280system.cpu.icache.cache_copies 0 # number of cache copies performed
281system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
282system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
283system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
284system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
285system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
286system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
287system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles
288system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles
289system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles
290system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles
291system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles
292system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles
293system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
294system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
295system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
296system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
297system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
298system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency
300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency
301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency
302system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency
304system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
305system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
306system.cpu.l2cache.tags.replacements 0 # number of replacements
| 227system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
228system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
229system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
230system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
231system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
232system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
233system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
234system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
235system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
236system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
237system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
238system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
239system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
240system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
241system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
242system.cpu.icache.overall_hits::total 244420617 # number of overall hits
243system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
244system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
245system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
246system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
247system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
248system.cpu.icache.overall_misses::total 882 # number of overall misses
249system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles
250system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles
251system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles
252system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles
253system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles
254system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles
255system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
256system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
257system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
258system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
259system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
260system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
261system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
262system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
263system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
264system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
265system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
266system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
267system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency
268system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency
269system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency
270system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency
271system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency
272system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency
273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279system.cpu.icache.fast_writes 0 # number of fast writes performed
280system.cpu.icache.cache_copies 0 # number of cache copies performed
281system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
282system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
283system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
284system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
285system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
286system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
287system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles
288system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles
289system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles
290system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles
291system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles
292system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles
293system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
294system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
295system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
296system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
297system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
298system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency
300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency
301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency
302system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency
304system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
305system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
306system.cpu.l2cache.tags.replacements 0 # number of replacements
|
307system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use
| 307system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use
|
308system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
309system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
310system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 308system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
309system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
310system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
312system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor
313system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor
| 312system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor
313system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor
|
314system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor
315system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
317system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
318system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
319system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
322system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
323system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
324system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
325system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
326system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
327system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
328system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
329system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
330system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
331system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
332system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
333system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
334system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
335system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
336system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
337system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
338system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
339system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
340system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
341system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
342system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
343system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
344system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
345system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
346system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
347system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
348system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
349system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
350system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
351system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
352system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
353system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
354system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles
355system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles
356system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles
357system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles
358system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles
359system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles
360system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles
361system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles
362system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles
363system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles
364system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles
365system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles
366system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
367system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
368system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
369system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
370system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
371system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
372system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
373system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
374system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
375system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
376system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
377system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
378system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
379system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
380system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
381system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
382system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
383system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
384system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
385system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
386system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
387system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
388system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
389system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
390system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
391system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
392system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
393system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
394system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency
395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency
396system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
398system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency
399system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
400system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency
401system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency
402system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
403system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency
404system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
405system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
406system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
407system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
408system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
409system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
410system.cpu.l2cache.fast_writes 0 # number of fast writes performed
411system.cpu.l2cache.cache_copies 0 # number of cache copies performed
412system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
413system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
414system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
415system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
416system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
417system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
418system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
419system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
420system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
421system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
422system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
423system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
424system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles
425system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles
426system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles
427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles
428system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles
429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles
430system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles
431system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles
432system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles
433system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles
434system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles
435system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles
436system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
437system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
438system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
439system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
440system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
442system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
443system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
444system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
445system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
446system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
447system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
448system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
450system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency
451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency
452system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency
455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
456system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency
458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
460system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 314system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor
315system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
317system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
318system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
319system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
322system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
323system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
324system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
325system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
326system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
327system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
328system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
329system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
330system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
331system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
332system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
333system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
334system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
335system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
336system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
337system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
338system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
339system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
340system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
341system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
342system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
343system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
344system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
345system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
346system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
347system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
348system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
349system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
350system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
351system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
352system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
353system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
354system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles
355system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles
356system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles
357system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles
358system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles
359system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles
360system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles
361system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles
362system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles
363system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles
364system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles
365system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles
366system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
367system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
368system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
369system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
370system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
371system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
372system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
373system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
374system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
375system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
376system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
377system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
378system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
379system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
380system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
381system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
382system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
383system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
384system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
385system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
386system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
387system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
388system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
389system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
390system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
391system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
392system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
393system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
394system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency
395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency
396system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
398system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency
399system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
400system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency
401system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency
402system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
403system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency
404system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
405system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
406system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
407system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
408system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
409system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
410system.cpu.l2cache.fast_writes 0 # number of fast writes performed
411system.cpu.l2cache.cache_copies 0 # number of cache copies performed
412system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
413system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
414system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
415system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
416system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
417system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
418system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
419system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
420system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
421system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
422system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
423system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
424system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles
425system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles
426system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles
427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles
428system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles
429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles
430system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles
431system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles
432system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles
433system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles
434system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles
435system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles
436system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
437system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
438system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
439system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
440system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
442system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
443system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
444system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
445system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
446system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
447system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
448system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
450system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency
451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency
452system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency
455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
456system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency
458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
460system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
| 461system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
462system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
464system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
461system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution
464system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
465system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
466system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
467system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
468system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
469system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes)
470system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes)
471system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
472system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
473system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
474system.cpu.toL2Bus.snoops 0 # Total snoops (count)
475system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram
| 467system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
468system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
472system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
473system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
474system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
475system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes)
476system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes)
477system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
478system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
479system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
480system.cpu.toL2Bus.snoops 0 # Total snoops (count)
481system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram
|
476system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
| 482system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram
|
478system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
| 484system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
479system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram
| 485system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram
|
481system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
| 487system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
488system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
483system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
| 489system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
484system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram
486system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks)
487system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
488system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
489system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
490system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
491system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
492system.membus.trans_dist::ReadResp 1036 # Transaction distribution
493system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
494system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
495system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution
496system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
497system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
498system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
499system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
500system.membus.snoops 0 # Total snoops (count)
501system.membus.snoop_fanout::samples 15603 # Request fanout histogram
502system.membus.snoop_fanout::mean 0 # Request fanout histogram
503system.membus.snoop_fanout::stdev 0 # Request fanout histogram
504system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
505system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
506system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
507system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
508system.membus.snoop_fanout::min_value 0 # Request fanout histogram
509system.membus.snoop_fanout::max_value 0 # Request fanout histogram
510system.membus.snoop_fanout::total 15603 # Request fanout histogram
511system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks)
512system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
513system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks)
514system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
515
516---------- End Simulation Statistics ----------
| 490system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram
492system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks)
493system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
494system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
495system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
496system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
497system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
498system.membus.trans_dist::ReadResp 1036 # Transaction distribution
499system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
500system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
501system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution
502system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
503system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
504system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
505system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
506system.membus.snoops 0 # Total snoops (count)
507system.membus.snoop_fanout::samples 15603 # Request fanout histogram
508system.membus.snoop_fanout::mean 0 # Request fanout histogram
509system.membus.snoop_fanout::stdev 0 # Request fanout histogram
510system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
511system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
512system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
513system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
514system.membus.snoop_fanout::min_value 0 # Request fanout histogram
515system.membus.snoop_fanout::max_value 0 # Request fanout histogram
516system.membus.snoop_fanout::total 15603 # Request fanout histogram
517system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks)
518system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
519system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks)
520system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
521
522---------- End Simulation Statistics ----------
|