Cross Reference: /gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

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stats.txt (10063:9595c7a1d837)	stats.txt (10220:9eab5efc02e8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated 4sim_ticks 361488530000 # Number of ticks simulated 5final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated 4sim_ticks 361488530000 # Number of ticks simulated 5final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1454320 # Simulator instruction rate (inst/s) 8host_op_rate 1454380 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2156135283 # Simulator tick rate (ticks/s) 10host_mem_usage 371132 # Number of bytes of host memory used 11host_seconds 167.66 # Real time elapsed on the host	7host_inst_rate 1070091 # Simulator instruction rate (inst/s) 8host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1586487053 # Simulator tick rate (ticks/s) 10host_mem_usage 406976 # Number of bytes of host memory used 11host_seconds 227.85 # Real time elapsed on the host
12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 2762444 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 1036 # Transaction distribution 34system.membus.trans_dist::ReadResp 1036 # Transaction distribution 35system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 36system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 998592 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 443 # Number of system calls 49system.cpu.numCycles 722977060 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 243825150 # Number of instructions committed 53system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 56system.cpu.num_func_calls 4252956 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 58system.cpu.num_int_insts 194726494 # number of integer instructions 59system.cpu.num_fp_insts 11630 # number of float instructions 60system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 61system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 64system.cpu.num_mem_refs 105711441 # number of memory refs 65system.cpu.num_load_insts 82803521 # Number of load instructions 66system.cpu.num_store_insts 22907920 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 722977060 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.Branches 29302884 # Number of branches fetched	12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 2762444 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 1036 # Transaction distribution 34system.membus.trans_dist::ReadResp 1036 # Transaction distribution 35system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 36system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 998592 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 443 # Number of system calls 49system.cpu.numCycles 722977060 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 243825150 # Number of instructions committed 53system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 56system.cpu.num_func_calls 4252956 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 58system.cpu.num_int_insts 194726494 # number of integer instructions 59system.cpu.num_fp_insts 11630 # number of float instructions 60system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 61system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 64system.cpu.num_mem_refs 105711441 # number of memory refs 65system.cpu.num_load_insts 82803521 # Number of load instructions 66system.cpu.num_store_insts 22907920 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 722977060 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.Branches 29302884 # Number of branches fetched
	72system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction 73system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction 74system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction 75system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction 76system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction 77system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction 78system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction 79system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction 80system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction 81system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction 82system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction 83system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction 84system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction 85system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction 86system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction 87system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction 88system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction 89system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction 90system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction 91system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction 92system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction 93system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction 94system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction 95system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction 96system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction 97system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction 98system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction 99system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction 100system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction 101system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction 102system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction 103system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction 104system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 105system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 106system.cpu.op_class::total 244431613 # Class of executed instruction
72system.cpu.icache.tags.replacements 25 # number of replacements 73system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use 74system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 75system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 76system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 77system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor 79system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 80system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy 81system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 82system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 83system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 84system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 85system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 86system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 87system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 88system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses 89system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 90system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 91system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 92system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 93system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 94system.cpu.icache.overall_hits::total 244420617 # number of overall hits 95system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 96system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 97system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 98system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 99system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 100system.cpu.icache.overall_misses::total 882 # number of overall misses 101system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles 102system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles 103system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles 104system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles 105system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles 106system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles 107system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 108system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 109system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 110system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 111system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 112system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 113system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 114system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 115system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 116system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 117system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 118system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 119system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency 120system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency 121system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 122system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency 123system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 124system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency 125system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 127system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131system.cpu.icache.fast_writes 0 # number of fast writes performed 132system.cpu.icache.cache_copies 0 # number of cache copies performed 133system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 134system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 135system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 136system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 137system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 138system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 139system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles 140system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles 141system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles 142system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles 143system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles 144system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles 145system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 146system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 147system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 148system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 149system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 150system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 151system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 152system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency 153system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 154system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 155system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 156system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 157system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 158system.cpu.l2cache.tags.replacements 0 # number of replacements 159system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use 160system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. 161system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 162system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. 163system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 164system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor 165system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor 166system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor 167system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 168system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 169system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 170system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy 171system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 172system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 173system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 174system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 175system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id 176system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id 177system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id 178system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses 179system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses 180system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 181system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits 182system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits 183system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits 184system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits 185system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 186system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 187system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 188system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 189system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 190system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 191system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 192system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 193system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses 194system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses 195system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses 196system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 197system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 198system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 199system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 200system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 201system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 202system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 203system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 204system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles 205system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles 206system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles 207system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 208system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 209system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles 210system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles 211system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles 212system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles 213system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles 214system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles 215system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 216system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 217system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) 218system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) 219system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) 220system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 221system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 222system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 223system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 224system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 225system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 226system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 227system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 228system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses 229system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses 230system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses 231system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 232system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 233system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 234system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 235system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 236system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 237system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 238system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 239system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 240system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 241system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 242system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 243system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 244system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 245system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 246system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 247system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 248system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 249system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 250system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 251system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 253system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 254system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 255system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 256system.cpu.l2cache.fast_writes 0 # number of fast writes performed 257system.cpu.l2cache.cache_copies 0 # number of cache copies performed 258system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 259system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses 260system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses 261system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 262system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 263system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 264system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 265system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 266system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 267system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 268system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 269system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles 270system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles 271system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles 272system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 273system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 274system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles 275system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles 276system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles 277system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles 278system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles 279system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles 280system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 281system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses 282system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses 283system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 284system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 285system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 286system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 287system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 288system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 289system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 290system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 291system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 292system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 293system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 294system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 295system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 296system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 297system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 298system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 299system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 301system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 302system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 303system.cpu.dcache.tags.replacements 935475 # number of replacements 304system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use 305system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 306system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 307system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 308system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. 309system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor 310system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 311system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy 312system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 313system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 314system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id 315system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id 316system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 317system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 318system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 319system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses 320system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 321system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 322system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 323system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 324system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 325system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 326system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 327system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 328system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 329system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 330system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 331system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 332system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 333system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 334system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 335system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 336system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 337system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 338system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 339system.cpu.dcache.overall_misses::total 939567 # number of overall misses 340system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles 341system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles 342system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 343system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 344system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 345system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles 346system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles 347system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles 348system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles 349system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles 350system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 351system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 352system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 353system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 354system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 355system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 356system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 357system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 358system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 359system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 360system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 361system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 362system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 363system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 364system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 365system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 366system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 367system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 368system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 369system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 370system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency 371system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency 372system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 373system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 374system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 375system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency 376system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 377system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency 378system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 379system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency 380system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 381system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 382system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 383system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 384system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 385system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.cpu.dcache.fast_writes 0 # number of fast writes performed 387system.cpu.dcache.cache_copies 0 # number of cache copies performed 388system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 389system.cpu.dcache.writebacks::total 935266 # number of writebacks 390system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 391system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 392system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 393system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 394system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 395system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 396system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 397system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 398system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 399system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 400system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles 401system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles 402system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 403system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 404system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 405system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles 406system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles 407system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles 408system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles 409system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles 410system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 411system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 412system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 413system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 414system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 415system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 416system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 417system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 418system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 419system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 420system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency 421system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency 422system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 423system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency 424system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 425system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency 426system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 427system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 428system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 429system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 430system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 431system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s) 432system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 437system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 442system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) 443system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) 444system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 445system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) 446system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 447system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 448system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 449system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 450system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 451 452---------- End Simulation Statistics ----------	107system.cpu.icache.tags.replacements 25 # number of replacements 108system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use 109system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. 110system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. 111system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. 112system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 113system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor 114system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 115system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy 116system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id 117system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 118system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 119system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 120system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id 121system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id 122system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses 123system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses 124system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 125system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 126system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 127system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 128system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 129system.cpu.icache.overall_hits::total 244420617 # number of overall hits 130system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 131system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 132system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 133system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 134system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 135system.cpu.icache.overall_misses::total 882 # number of overall misses 136system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles 137system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles 138system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles 139system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles 140system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles 141system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles 142system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 143system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 144system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 145system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 146system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 147system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 148system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 149system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 150system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 151system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 152system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 153system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 154system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency 155system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency 156system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 157system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency 158system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 159system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency 160system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 161system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 162system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 163system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 164system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 165system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 166system.cpu.icache.fast_writes 0 # number of fast writes performed 167system.cpu.icache.cache_copies 0 # number of cache copies performed 168system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 169system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 170system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 171system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 172system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 173system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 174system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles 175system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles 176system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles 177system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles 178system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles 179system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles 180system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 181system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 182system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 183system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 184system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 185system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 186system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 187system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency 188system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 189system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 190system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 191system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 192system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 193system.cpu.l2cache.tags.replacements 0 # number of replacements 194system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use 195system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. 196system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. 197system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. 198system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 199system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor 200system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor 201system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor 202system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 203system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 204system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 205system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy 206system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id 207system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 208system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 209system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 210system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id 211system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id 212system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id 213system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses 214system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses 215system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 216system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits 217system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits 218system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits 219system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits 220system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 221system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 222system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 223system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 224system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 225system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 226system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 227system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 228system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses 229system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses 230system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses 231system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 232system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 233system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 234system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 235system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 236system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 237system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 238system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 239system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles 240system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles 241system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles 242system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 243system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 244system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles 245system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles 246system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles 247system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles 248system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles 249system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles 250system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 251system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 252system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) 253system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) 254system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) 255system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 256system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 257system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 258system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 259system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 260system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 261system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 262system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 263system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses 264system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses 265system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses 266system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 267system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 268system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 269system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 270system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 271system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 272system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 273system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 274system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 275system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 276system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 277system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 278system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 279system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 280system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 281system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 282system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 283system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 284system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 285system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 286system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 287system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 288system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 289system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 290system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 291system.cpu.l2cache.fast_writes 0 # number of fast writes performed 292system.cpu.l2cache.cache_copies 0 # number of cache copies performed 293system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 294system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses 295system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses 296system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 297system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 298system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 299system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 300system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 301system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 302system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 303system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 304system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles 305system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles 306system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles 307system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 308system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 309system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles 310system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles 311system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles 312system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles 313system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles 314system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles 315system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 316system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses 317system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses 318system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 319system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 320system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 321system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 322system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 323system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 324system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 325system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 326system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 327system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 328system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 329system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 330system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 331system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 332system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 333system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 334system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 335system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 336system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 337system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 338system.cpu.dcache.tags.replacements 935475 # number of replacements 339system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use 340system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. 341system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. 342system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. 343system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. 344system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor 345system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 346system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy 347system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 348system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 349system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id 350system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id 351system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 352system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 353system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses 354system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses 355system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 356system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 357system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 358system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 359system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 360system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 361system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 362system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 363system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 364system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 365system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 366system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 367system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 368system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 369system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 370system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 371system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 372system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 373system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 374system.cpu.dcache.overall_misses::total 939567 # number of overall misses 375system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles 376system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles 377system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 378system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 379system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 380system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles 381system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles 382system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles 383system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles 384system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles 385system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 386system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 387system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 388system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 389system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 390system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 391system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 392system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 393system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 394system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 395system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 396system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 397system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 398system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 399system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 400system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 401system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 402system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 403system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 404system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 405system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency 406system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency 407system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 408system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 409system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 410system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.fast_writes 0 # number of fast writes performed 422system.cpu.dcache.cache_copies 0 # number of cache copies performed 423system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 424system.cpu.dcache.writebacks::total 935266 # number of writebacks 425system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 426system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 427system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 428system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 429system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 430system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 431system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 432system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 433system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 434system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles 437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 439system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 440system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles 441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles 444system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles 445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 449system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 450system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 452system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 453system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 454system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 455system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency 456system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency 457system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 458system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency 459system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 460system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency 461system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 462system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 463system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 464system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 465system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 466system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s) 467system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) 477system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) 478system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) 479system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 480system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) 481system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 482system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 483system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 484system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 485system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 486 487---------- End Simulation Statistics ----------