1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.361489 # Number of seconds simulated
4sim_ticks 361488530000 # Number of ticks simulated
5final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1070091 # Simulator instruction rate (inst/s)
8host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1586487053 # Simulator tick rate (ticks/s)
10host_mem_usage 406976 # Number of bytes of host memory used
11host_seconds 227.85 # Real time elapsed on the host
12sim_insts 243825150 # Number of instructions simulated
13sim_ops 243835265 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
--- 4 unchanged lines hidden (view full) ---
24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 2762444 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 1036 # Transaction distribution
34system.membus.trans_dist::ReadResp 1036 # Transaction distribution
35system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
36system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
40system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
41system.membus.data_through_bus 998592 # Total data (bytes)
42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
43system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
45system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
46system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
47system.cpu_clk_domain.clock 500 # Clock period in ticks
48system.cpu.workload.num_syscalls 443 # Number of system calls
49system.cpu.numCycles 722977060 # number of cpu cycles simulated
50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
--- 407 unchanged lines hidden (view full) ---
458system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
459system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
460system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
461system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
462system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
463system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
464system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
465system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
466system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
467system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
468system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
474system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
475system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
476system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
477system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
478system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
479system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
480system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
481system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
482system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
483system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
484system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
485system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
486
487---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.361489 # Number of seconds simulated
4sim_ticks 361488530000 # Number of ticks simulated
5final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1070091 # Simulator instruction rate (inst/s)
8host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1586487053 # Simulator tick rate (ticks/s)
10host_mem_usage 406976 # Number of bytes of host memory used
11host_seconds 227.85 # Real time elapsed on the host
12sim_insts 243825150 # Number of instructions simulated
13sim_ops 243835265 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
--- 4 unchanged lines hidden (view full) ---
24system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 2762444 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 1036 # Transaction distribution
34system.membus.trans_dist::ReadResp 1036 # Transaction distribution
35system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
36system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
40system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
41system.membus.data_through_bus 998592 # Total data (bytes)
42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
43system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
45system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
46system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
47system.cpu_clk_domain.clock 500 # Clock period in ticks
48system.cpu.workload.num_syscalls 443 # Number of system calls
49system.cpu.numCycles 722977060 # number of cpu cycles simulated
50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
--- 407 unchanged lines hidden (view full) ---
458system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
459system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
460system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
461system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
462system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
463system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
464system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
465system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
466system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
467system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
468system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
474system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
475system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
476system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
477system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
478system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
479system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
480system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
481system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
482system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
483system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
484system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
485system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
486
487---------- End Simulation Statistics ----------