19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[0]
---
> system_port=system.membus.slave[0]
62c61
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
83c82
< mem_side=system.cpu.toL2Bus.port[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
91c90
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
112c111
< mem_side=system.cpu.toL2Bus.port[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
123c122
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
143,144c142,143
< cpu_side=system.cpu.toL2Bus.port[2]
< mem_side=system.membus.port[2]
---
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[1]
154c153,154
< port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
---
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
162c162
< cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
---
> cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
186c186,187
< port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
---
> master=system.physmem.port[0]
> slave=system.system_port system.cpu.l2cache.mem_side
189c190,191
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
190a193
> in_addr_map=true
196c199
< port=system.membus.port[1]
---
> port=system.membus.master[0]