| stats.txt (9924:31ef410b6843) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.026877 # Number of seconds simulated 4sim_ticks 26877484000 # Number of ticks simulated 5final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.026913 # Number of seconds simulated 4sim_ticks 26912680500 # Number of ticks simulated 5final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 158705 # Simulator instruction rate (inst/s) 8host_op_rate 159844 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47086787 # Simulator tick rate (ticks/s) 10host_mem_usage 380172 # Number of bytes of host memory used 11host_seconds 570.81 # Real time elapsed on the host | 7host_inst_rate 145850 # Simulator instruction rate (inst/s) 8host_op_rate 146897 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43329539 # Simulator tick rate (ticks/s) 10host_mem_usage 407732 # Number of bytes of host memory used 11host_seconds 621.12 # Real time elapsed on the host |
| 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated | 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992384 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34system.physmem.bytesRead 992384 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis 56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 74system.physmem.totGap 26877282500 # Total gap between requests 75system.physmem.readPktSize::0 0 # Categorize read packet sizes 76system.physmem.readPktSize::1 0 # Categorize read packet sizes 77system.physmem.readPktSize::2 0 # Categorize read packet sizes 78system.physmem.readPktSize::3 0 # Categorize read packet sizes 79system.physmem.readPktSize::4 0 # Categorize read packet sizes 80system.physmem.readPktSize::5 0 # Categorize read packet sizes 81system.physmem.readPktSize::6 15506 # Categorize read packet sizes 82system.physmem.writePktSize::0 0 # Categorize write packet sizes 83system.physmem.writePktSize::1 0 # Categorize write packet sizes 84system.physmem.writePktSize::2 0 # Categorize write packet sizes 85system.physmem.writePktSize::3 0 # Categorize write packet sizes 86system.physmem.writePktSize::4 0 # Categorize write packet sizes 87system.physmem.writePktSize::5 0 # Categorize write packet sizes 88system.physmem.writePktSize::6 0 # Categorize write packet sizes 89system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 14system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992896 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 15514 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 988 # Per bank write bursts 43system.physmem.perBankRdBursts::1 886 # Per bank write bursts 44system.physmem.perBankRdBursts::2 943 # Per bank write bursts 45system.physmem.perBankRdBursts::3 1028 # Per bank write bursts 46system.physmem.perBankRdBursts::4 1049 # Per bank write bursts 47system.physmem.perBankRdBursts::5 1105 # Per bank write bursts 48system.physmem.perBankRdBursts::6 1078 # Per bank write bursts 49system.physmem.perBankRdBursts::7 1078 # Per bank write bursts 50system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 51system.physmem.perBankRdBursts::9 956 # Per bank write bursts 52system.physmem.perBankRdBursts::10 938 # Per bank write bursts 53system.physmem.perBankRdBursts::11 899 # Per bank write bursts 54system.physmem.perBankRdBursts::12 904 # Per bank write bursts 55system.physmem.perBankRdBursts::13 865 # Per bank write bursts 56system.physmem.perBankRdBursts::14 877 # Per bank write bursts 57system.physmem.perBankRdBursts::15 896 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 26912480500 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 15514 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 96system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 153system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation 190system.physmem.totQLat 38456500 # Total cycles spent in queuing delays 191system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests 192system.physmem.totBusLat 77530000 # Total cycles spent in databus access 193system.physmem.totBankLat 172026250 # Total cycles spent in bank access 194system.physmem.avgQLat 2480.10 # Average queueing delay per request 195system.physmem.avgBankLat 11094.17 # Average bank access latency per request 196system.physmem.avgBusLat 5000.00 # Average bus latency per request 197system.physmem.avgMemAccLat 18574.28 # Average memory access latency 198system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s 199system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 200system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s 201system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 202system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 155system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation 263system.physmem.totQLat 103133500 # Total ticks spent queuing 264system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers 266system.physmem.totBankLat 175711250 # Total ticks spent accessing banks 267system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst 268system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 203system.physmem.busUtil 0.29 # Data bus utilization in percentage | 276system.physmem.busUtil 0.29 # Data bus utilization in percentage |
| 204system.physmem.avgRdQLen 0.01 # Average read queue length over time 205system.physmem.avgWrQLen 0.00 # Average write queue length over time 206system.physmem.readRowHits 15227 # Number of row buffer hits during reads | 277system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 281system.physmem.readRowHits 14897 # Number of row buffer hits during reads |
| 207system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 282system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 208system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads | 283system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads |
| 209system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 284system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 210system.physmem.avgGap 1733347.25 # Average gap between requests 211system.membus.throughput 36922504 # Throughput (bytes/s) 212system.membus.trans_dist::ReadReq 968 # Transaction distribution 213system.membus.trans_dist::ReadResp 968 # Transaction distribution 214system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 215system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 285system.physmem.avgGap 1734722.22 # Average gap between requests 286system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined 287system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state 288system.membus.throughput 36893241 # Throughput (bytes/s) 289system.membus.trans_dist::ReadReq 976 # Transaction distribution 290system.membus.trans_dist::ReadResp 976 # Transaction distribution |
| 216system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 217system.membus.trans_dist::ReadExResp 14538 # Transaction distribution | 291system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 292system.membus.trans_dist::ReadExResp 14538 # Transaction distribution |
| 218system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes) 219system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes) 220system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes) 221system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes) 222system.membus.data_through_bus 992384 # Total data (bytes) | 293system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes) 294system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes) 295system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) 296system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) 297system.membus.data_through_bus 992896 # Total data (bytes) |
| 223system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 298system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 224system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) | 299system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks) |
| 225system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 300system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 226system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) | 301system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks) |
| 227system.membus.respLayer1.utilization 0.5 # Layer utilization (%) | 302system.membus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 228system.cpu.branchPred.lookups 26677800 # Number of BP lookups 229system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted 230system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect 231system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups 232system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits | 303system.cpu.branchPred.lookups 26684421 # Number of BP lookups 304system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits |
| 233system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 234system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage 235system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target. 236system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions. | 309system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions. |
| 237system.cpu.dtb.inst_hits 0 # ITB inst hits 238system.cpu.dtb.inst_misses 0 # ITB inst misses 239system.cpu.dtb.read_hits 0 # DTB read hits 240system.cpu.dtb.read_misses 0 # DTB read misses 241system.cpu.dtb.write_hits 0 # DTB write hits 242system.cpu.dtb.write_misses 0 # DTB write misses 243system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 244system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 272system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 273system.cpu.itb.read_accesses 0 # DTB read accesses 274system.cpu.itb.write_accesses 0 # DTB write accesses 275system.cpu.itb.inst_accesses 0 # ITB inst accesses 276system.cpu.itb.hits 0 # DTB hits 277system.cpu.itb.misses 0 # DTB misses 278system.cpu.itb.accesses 0 # DTB accesses 279system.cpu.workload.num_syscalls 442 # Number of system calls | 312system.cpu.dtb.inst_hits 0 # ITB inst hits 313system.cpu.dtb.inst_misses 0 # ITB inst misses 314system.cpu.dtb.read_hits 0 # DTB read hits 315system.cpu.dtb.read_misses 0 # DTB read misses 316system.cpu.dtb.write_hits 0 # DTB write hits 317system.cpu.dtb.write_misses 0 # DTB write misses 318system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 347system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.itb.read_accesses 0 # DTB read accesses 349system.cpu.itb.write_accesses 0 # DTB write accesses 350system.cpu.itb.inst_accesses 0 # ITB inst accesses 351system.cpu.itb.hits 0 # DTB hits 352system.cpu.itb.misses 0 # DTB misses 353system.cpu.itb.accesses 0 # DTB accesses 354system.cpu.workload.num_syscalls 442 # Number of system calls |
| 280system.cpu.numCycles 53754969 # number of cpu cycles simulated | 355system.cpu.numCycles 53825362 # number of cpu cycles simulated |
| 281system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 282system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 356system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 357system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 283system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss 284system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed 285system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered 286system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken 287system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked 288system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing 289system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked 290system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 291system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps | 358system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss 359system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed 360system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered 361system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken 362system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked 363system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing 364system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked 365system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 366system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps |
| 292system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR | 367system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR |
| 293system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched 294system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed 295system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total) | 368system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched 369system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed 370system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total) |
| 298system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 373system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 299system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total) | 374system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total) |
| 308system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 383system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 311system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle 313system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle 314system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle 315system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked 316system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running 317system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking 318system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing 319system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch 320system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction 321system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode 322system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode 323system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing 324system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle 325system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking 326system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst 327system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running 328system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking 329system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename 330system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full 331system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full 332system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full 333system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers 334system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 499912232 # Number of integer rename lookups 337system.cpu.rename.fp_rename_lookups 925 # Number of floating rename lookups | 386system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle 388system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle 389system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle 390system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked 391system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running 392system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking 393system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing 394system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch 395system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction 396system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode 397system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode 398system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing 399system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle 400system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking 401system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst 402system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running 403system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking 404system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename 405system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 406system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full 407system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full 408system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers 409system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed 410system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made 411system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups 412system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups |
| 338system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed | 413system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed |
| 339system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing 340system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed 342system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit. 345system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads. 346system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores. 347system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec) 348system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ 349system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued 351system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph 353system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed 354system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle | 414system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing 415system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed 416system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed 417system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer 418system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit. 419system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit. 420system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads. 421system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores. 422system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec) 423system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ 424system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued 425system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued 426system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling 427system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph 428system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed 429system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle |
| 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 432system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 358system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle | 433system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle |
| 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 442system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 370system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle | 445system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle |
| 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 446system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 372system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available | 447system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available 448system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available 449system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available 450system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available 451system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available 452system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available 453system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available 454system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available 455system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available 476system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available 477system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available |
| 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 478system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 479system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 480system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 406system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued | 481system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued 482system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued |
| 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued | 483system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued 484system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued 485system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued 486system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued 487system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued 488system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued 489system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 496system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued |
| 429system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued | 504system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued |
| 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued | 505system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued |
| 431system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued | 506system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued |
| 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued | 507system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued |
| 435system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued | 510system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued 511system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 512system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 513system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 439system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued 440system.cpu.iq.rate 1.956085 # Inst issue rate 441system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested | 514system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued 515system.cpu.iq.rate 1.953624 # Inst issue rate 516system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested |
| 442system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) | 517system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) |
| 443system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses 446system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses 449system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses 450system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses 451system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores | 518system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads 519system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes 520system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses 521system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads 522system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes 523system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses 524system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses 525system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses 526system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores |
| 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 527system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 453system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed 454system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed 455system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations 456system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed | 528system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed 529system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed 530system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations 531system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed |
| 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled | 532system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 533system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 534system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled |
| 460system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked | 535system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked |
| 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 536system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 462system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking 465system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ 466system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch 467system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions 469system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions 470system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall 472system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly 474system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute | 537system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing 538system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking 539system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking 540system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ 541system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch 542system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions 543system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions 544system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions 545system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall 546system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall 547system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations 548system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly 549system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly 550system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute 551system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions 552system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed 553system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute |
| 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 12694 # number of nop insts executed | 554system.cpu.iew.exec_swp 0 # number of swp insts executed 555system.cpu.iew.exec_nop 12694 # number of nop insts executed |
| 481system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed 482system.cpu.iew.exec_branches 21323909 # Number of branches executed 483system.cpu.iew.exec_stores 5057786 # Number of stores executed 484system.cpu.iew.exec_rate 1.937974 # Inst execution rate 485system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 62240823 # num instructions producing a value 488system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value | 556system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed 557system.cpu.iew.exec_branches 21325110 # Number of branches executed 558system.cpu.iew.exec_stores 5056604 # Number of stores executed 559system.cpu.iew.exec_rate 1.935528 # Inst execution rate 560system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit 561system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back 562system.cpu.iew.wb_producers 62241416 # num instructions producing a value 563system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value |
| 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 564system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 490system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back | 565system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle 566system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back |
| 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 567system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 493system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit | 568system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit |
| 494system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards | 569system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards |
| 495system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle | 570system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted 571system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle |
| 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 574system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 500system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle | 575system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle |
| 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 584system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 512system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle | 587system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle |
| 513system.cpu.commit.committedInsts 90602407 # Number of instructions committed 514system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 516system.cpu.commit.refs 27318810 # Number of memory references committed 517system.cpu.commit.loads 22573966 # Number of loads committed 518system.cpu.commit.membars 3888 # Number of memory barriers committed 519system.cpu.commit.branches 18732304 # Number of branches committed 520system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 521system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. 522system.cpu.commit.function_calls 56148 # Number of function calls committed. | 588system.cpu.commit.committedInsts 90602407 # Number of instructions committed 589system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed 590system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 591system.cpu.commit.refs 27318810 # Number of memory references committed 592system.cpu.commit.loads 22573966 # Number of loads committed 593system.cpu.commit.membars 3888 # Number of memory barriers committed 594system.cpu.commit.branches 18732304 # Number of branches committed 595system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 596system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. 597system.cpu.commit.function_calls 56148 # Number of function calls committed. |
| 523system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached | 598system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached |
| 524system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 599system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 525system.cpu.rob.rob_reads 162398797 # The number of ROB reads 526system.cpu.rob.rob_writes 240250691 # The number of ROB writes 527system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself 528system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling | 600system.cpu.rob.rob_reads 162448377 # The number of ROB reads 601system.cpu.rob.rob_writes 240302265 # The number of ROB writes 602system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself 603system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 529system.cpu.committedInsts 90589798 # Number of Instructions Simulated 530system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated 531system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated | 604system.cpu.committedInsts 90589798 # Number of Instructions Simulated 605system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated 606system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated |
| 532system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction 533system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads 534system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle 535system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads 536system.cpu.int_regfile_reads 495533268 # number of integer regfile reads 537system.cpu.int_regfile_writes 120542090 # number of integer regfile writes 538system.cpu.fp_regfile_reads 173 # number of floating regfile reads 539system.cpu.fp_regfile_writes 448 # number of floating regfile writes 540system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads | 607system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction 608system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads 609system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle 610system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads 611system.cpu.int_regfile_reads 495553334 # number of integer regfile reads 612system.cpu.int_regfile_writes 120547287 # number of integer regfile writes 613system.cpu.fp_regfile_reads 170 # number of floating regfile reads 614system.cpu.fp_regfile_writes 410 # number of floating regfile writes 615system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads |
| 541system.cpu.misc_regfile_writes 7784 # number of misc regfile writes | 616system.cpu.misc_regfile_writes 7784 # number of misc regfile writes |
| 542system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) 543system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution 549system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution 550system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes) 551system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes) 552system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes) 555system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes) 556system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) 557system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) 558system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) | 617system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s) 618system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution 619system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution 620system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution 621system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution 625system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes) 626system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes) 627system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes) 628system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes) 629system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes) 630system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) 631system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) 632system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) 633system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks) |
| 559system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) | 634system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) |
| 560system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) | 635system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) |
| 561system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 636system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 562system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) | 637system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks) |
| 563system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) 564system.cpu.icache.tags.replacements 3 # number of replacements | 638system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) 639system.cpu.icache.tags.replacements 3 # number of replacements |
| 565system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use 566system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. 567system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. 568system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. | 640system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use 641system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks. 642system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks. 643system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks. |
| 569system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 644system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 570system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor 571system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy 572system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy 573system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits 574system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits 575system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits 576system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits 577system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits 578system.cpu.icache.overall_hits::total 13838909 # number of overall hits 579system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses 580system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses 581system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses 582system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses 583system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses 584system.cpu.icache.overall_misses::total 983 # number of overall misses 585system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles 586system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles 587system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles 588system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles 589system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles 590system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles 591system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses) 592system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses 594system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses 595system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses 596system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses | 645system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor 646system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy 647system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy 648system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits 649system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits 650system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits 651system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits 652system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits 653system.cpu.icache.overall_hits::total 13840808 # number of overall hits 654system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses 655system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses 656system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses 657system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses 658system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses 659system.cpu.icache.overall_misses::total 989 # number of overall misses 660system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles 661system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles 662system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles 663system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles 664system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles 665system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles 666system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses) 667system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses) 668system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses 669system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses 670system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses 671system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses |
| 597system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses 598system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses 599system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses 600system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses 601system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses 602system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses | 672system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses 673system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses 674system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses 675system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses 676system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses 677system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses |
| 603system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65672.429298 # average ReadReq miss latency 604system.cpu.icache.ReadReq_avg_miss_latency::total 65672.429298 # average ReadReq miss latency 605system.cpu.icache.demand_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency 606system.cpu.icache.demand_avg_miss_latency::total 65672.429298 # average overall miss latency 607system.cpu.icache.overall_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::total 65672.429298 # average overall miss latency 609system.cpu.icache.blocked_cycles::no_mshrs 629 # number of cycles access was blocked | 678system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency 679system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency 680system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency 681system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency 682system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency 683system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency 684system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked |
| 610system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 685system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 611system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked | 686system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked |
| 612system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 687system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 613system.cpu.icache.avg_blocked_cycles::no_mshrs 62.900000 # average number of cycles each access was blocked | 688system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked |
| 614system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 615system.cpu.icache.fast_writes 0 # number of fast writes performed 616system.cpu.icache.cache_copies 0 # number of cache copies performed | 689system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 690system.cpu.icache.fast_writes 0 # number of fast writes performed 691system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 617system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits 618system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits 619system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits 620system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits 621system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits 622system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits 623system.cpu.icache.ReadReq_mshr_misses::cpu.inst 729 # number of ReadReq MSHR misses 624system.cpu.icache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses 625system.cpu.icache.demand_mshr_misses::cpu.inst 729 # number of demand (read+write) MSHR misses 626system.cpu.icache.demand_mshr_misses::total 729 # number of demand (read+write) MSHR misses 627system.cpu.icache.overall_mshr_misses::cpu.inst 729 # number of overall MSHR misses 628system.cpu.icache.overall_mshr_misses::total 729 # number of overall MSHR misses 629system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49190750 # number of ReadReq MSHR miss cycles 630system.cpu.icache.ReadReq_mshr_miss_latency::total 49190750 # number of ReadReq MSHR miss cycles 631system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49190750 # number of demand (read+write) MSHR miss cycles 632system.cpu.icache.demand_mshr_miss_latency::total 49190750 # number of demand (read+write) MSHR miss cycles 633system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49190750 # number of overall MSHR miss cycles 634system.cpu.icache.overall_mshr_miss_latency::total 49190750 # number of overall MSHR miss cycles | 692system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits 693system.cpu.icache.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits 694system.cpu.icache.demand_mshr_hits::cpu.inst 256 # number of demand (read+write) MSHR hits 695system.cpu.icache.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits 696system.cpu.icache.overall_mshr_hits::cpu.inst 256 # number of overall MSHR hits 697system.cpu.icache.overall_mshr_hits::total 256 # number of overall MSHR hits 698system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses 699system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses 700system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses 701system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses 702system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses 703system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses 704system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50590750 # number of ReadReq MSHR miss cycles 705system.cpu.icache.ReadReq_mshr_miss_latency::total 50590750 # number of ReadReq MSHR miss cycles 706system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50590750 # number of demand (read+write) MSHR miss cycles 707system.cpu.icache.demand_mshr_miss_latency::total 50590750 # number of demand (read+write) MSHR miss cycles 708system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50590750 # number of overall MSHR miss cycles 709system.cpu.icache.overall_mshr_miss_latency::total 50590750 # number of overall MSHR miss cycles |
| 635system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses 636system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses 637system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses 638system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses 639system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses 640system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses | 710system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses 711system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses 712system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses 713system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses 714system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses 715system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses |
| 641system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency 642system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency 643system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency 644system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency 645system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency 646system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency | 716system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69018.758527 # average ReadReq mshr miss latency 717system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69018.758527 # average ReadReq mshr miss latency 718system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency 719system.cpu.icache.demand_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency 720system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency 721system.cpu.icache.overall_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency |
| 647system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 648system.cpu.l2cache.tags.replacements 0 # number of replacements | 722system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 723system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 649system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use 650system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. 651system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. 652system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. | 724system.cpu.l2cache.tags.tagsinuse 10730.387703 # Cycle average of tags in use 725system.cpu.l2cache.tags.total_refs 1831429 # Total number of references to valid blocks. 726system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks. 727system.cpu.l2cache.tags.avg_refs 118.179583 # Average number of references to valid blocks. |
| 653system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 728system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 654system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor 655system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor 656system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor 657system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy 658system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy 659system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy 660system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy 661system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 662system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits 663system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits 664system.cpu.l2cache.Writeback_hits::writebacks 942919 # number of Writeback hits 665system.cpu.l2cache.Writeback_hits::total 942919 # number of Writeback hits | 729system.cpu.l2cache.tags.occ_blocks::writebacks 9881.039169 # Average occupied blocks per requestor 730system.cpu.l2cache.tags.occ_blocks::cpu.inst 619.212620 # Average occupied blocks per requestor 731system.cpu.l2cache.tags.occ_blocks::cpu.data 230.135914 # Average occupied blocks per requestor 732system.cpu.l2cache.tags.occ_percent::writebacks 0.301545 # Average percentage of cache occupancy 733system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018897 # Average percentage of cache occupancy 734system.cpu.l2cache.tags.occ_percent::cpu.data 0.007023 # Average percentage of cache occupancy 735system.cpu.l2cache.tags.occ_percent::total 0.327465 # Average percentage of cache occupancy 736system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits 737system.cpu.l2cache.ReadReq_hits::cpu.data 903638 # number of ReadReq hits 738system.cpu.l2cache.ReadReq_hits::total 903662 # number of ReadReq hits 739system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits 740system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits |
| 666system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 667system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits | 741system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 742system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| 668system.cpu.l2cache.ReadExReq_hits::cpu.data 29198 # number of ReadExReq hits 669system.cpu.l2cache.ReadExReq_hits::total 29198 # number of ReadExReq hits 670system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits 671system.cpu.l2cache.demand_hits::cpu.data 932813 # number of demand (read+write) hits 672system.cpu.l2cache.demand_hits::total 932836 # number of demand (read+write) hits 673system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits 674system.cpu.l2cache.overall_hits::cpu.data 932813 # number of overall hits 675system.cpu.l2cache.overall_hits::total 932836 # number of overall hits 676system.cpu.l2cache.ReadReq_misses::cpu.inst 703 # number of ReadReq misses 677system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses 678system.cpu.l2cache.ReadReq_misses::total 979 # number of ReadReq misses 679system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 680system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses | 743system.cpu.l2cache.ReadExReq_hits::cpu.data 29160 # number of ReadExReq hits 744system.cpu.l2cache.ReadExReq_hits::total 29160 # number of ReadExReq hits 745system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 746system.cpu.l2cache.demand_hits::cpu.data 932798 # number of demand (read+write) hits 747system.cpu.l2cache.demand_hits::total 932822 # number of demand (read+write) hits 748system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits 749system.cpu.l2cache.overall_hits::cpu.data 932798 # number of overall hits 750system.cpu.l2cache.overall_hits::total 932822 # number of overall hits 751system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses 752system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses 753system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses |
| 681system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 682system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses | 754system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 755system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses |
| 683system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses 684system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses 685system.cpu.l2cache.demand_misses::total 15517 # number of demand (read+write) misses 686system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses 687system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses 688system.cpu.l2cache.overall_misses::total 15517 # number of overall misses 689system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48235000 # number of ReadReq miss cycles 690system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19323500 # number of ReadReq miss cycles 691system.cpu.l2cache.ReadReq_miss_latency::total 67558500 # number of ReadReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 897218750 # number of ReadExReq miss cycles 693system.cpu.l2cache.ReadExReq_miss_latency::total 897218750 # number of ReadExReq miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.inst 48235000 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::cpu.data 916542250 # number of demand (read+write) miss cycles 696system.cpu.l2cache.demand_miss_latency::total 964777250 # number of demand (read+write) miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.inst 48235000 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::cpu.data 916542250 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency::total 964777250 # number of overall miss cycles 700system.cpu.l2cache.ReadReq_accesses::cpu.inst 726 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadReq_accesses::cpu.data 903891 # number of ReadReq accesses(hits+misses) 702system.cpu.l2cache.ReadReq_accesses::total 904617 # number of ReadReq accesses(hits+misses) 703system.cpu.l2cache.Writeback_accesses::writebacks 942919 # number of Writeback accesses(hits+misses) 704system.cpu.l2cache.Writeback_accesses::total 942919 # number of Writeback accesses(hits+misses) 705system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 706system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 707system.cpu.l2cache.ReadExReq_accesses::cpu.data 43736 # number of ReadExReq accesses(hits+misses) 708system.cpu.l2cache.ReadExReq_accesses::total 43736 # number of ReadExReq accesses(hits+misses) 709system.cpu.l2cache.demand_accesses::cpu.inst 726 # number of demand (read+write) accesses 710system.cpu.l2cache.demand_accesses::cpu.data 947627 # number of demand (read+write) accesses 711system.cpu.l2cache.demand_accesses::total 948353 # number of demand (read+write) accesses 712system.cpu.l2cache.overall_accesses::cpu.inst 726 # number of overall (read+write) accesses 713system.cpu.l2cache.overall_accesses::cpu.data 947627 # number of overall (read+write) accesses 714system.cpu.l2cache.overall_accesses::total 948353 # number of overall (read+write) accesses 715system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968320 # miss rate for ReadReq accesses 716system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000305 # miss rate for ReadReq accesses 717system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses 718system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses 719system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses 720system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332404 # miss rate for ReadExReq accesses 721system.cpu.l2cache.ReadExReq_miss_rate::total 0.332404 # miss rate for ReadExReq accesses 722system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968320 # miss rate for demand accesses 723system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses 724system.cpu.l2cache.demand_miss_rate::total 0.016362 # miss rate for demand accesses 725system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968320 # miss rate for overall accesses 726system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses 727system.cpu.l2cache.overall_miss_rate::total 0.016362 # miss rate for overall accesses 728system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.086771 # average ReadReq miss latency 729system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70012.681159 # average ReadReq miss latency 730system.cpu.l2cache.ReadReq_avg_miss_latency::total 69007.660878 # average ReadReq miss latency 731system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61715.418214 # average ReadExReq miss latency 732system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61715.418214 # average ReadExReq miss latency 733system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency 734system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency 735system.cpu.l2cache.demand_avg_miss_latency::total 62175.501063 # average overall miss latency 736system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency 737system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::total 62175.501063 # average overall miss latency | 756system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses 757system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses 758system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses 759system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses 760system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses 761system.cpu.l2cache.overall_misses::total 15525 # number of overall misses 762system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49612500 # number of ReadReq miss cycles 763system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21119250 # number of ReadReq miss cycles 764system.cpu.l2cache.ReadReq_miss_latency::total 70731750 # number of ReadReq miss cycles 765system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962947000 # number of ReadExReq miss cycles 766system.cpu.l2cache.ReadExReq_miss_latency::total 962947000 # number of ReadExReq miss cycles 767system.cpu.l2cache.demand_miss_latency::cpu.inst 49612500 # number of demand (read+write) miss cycles 768system.cpu.l2cache.demand_miss_latency::cpu.data 984066250 # number of demand (read+write) miss cycles 769system.cpu.l2cache.demand_miss_latency::total 1033678750 # number of demand (read+write) miss cycles 770system.cpu.l2cache.overall_miss_latency::cpu.inst 49612500 # number of overall miss cycles 771system.cpu.l2cache.overall_miss_latency::cpu.data 984066250 # number of overall miss cycles 772system.cpu.l2cache.overall_miss_latency::total 1033678750 # number of overall miss cycles 773system.cpu.l2cache.ReadReq_accesses::cpu.inst 732 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadReq_accesses::cpu.data 903917 # number of ReadReq accesses(hits+misses) 775system.cpu.l2cache.ReadReq_accesses::total 904649 # number of ReadReq accesses(hits+misses) 776system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses) 777system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses) 778system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 779system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 780system.cpu.l2cache.ReadExReq_accesses::cpu.data 43698 # number of ReadExReq accesses(hits+misses) 781system.cpu.l2cache.ReadExReq_accesses::total 43698 # number of ReadExReq accesses(hits+misses) 782system.cpu.l2cache.demand_accesses::cpu.inst 732 # number of demand (read+write) accesses 783system.cpu.l2cache.demand_accesses::cpu.data 947615 # number of demand (read+write) accesses 784system.cpu.l2cache.demand_accesses::total 948347 # number of demand (read+write) accesses 785system.cpu.l2cache.overall_accesses::cpu.inst 732 # number of overall (read+write) accesses 786system.cpu.l2cache.overall_accesses::cpu.data 947615 # number of overall (read+write) accesses 787system.cpu.l2cache.overall_accesses::total 948347 # number of overall (read+write) accesses 788system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967213 # miss rate for ReadReq accesses 789system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses 790system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses 791system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332693 # miss rate for ReadExReq accesses 792system.cpu.l2cache.ReadExReq_miss_rate::total 0.332693 # miss rate for ReadExReq accesses 793system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967213 # miss rate for demand accesses 794system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses 795system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses 796system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967213 # miss rate for overall accesses 797system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses 798system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses 799system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70074.152542 # average ReadReq miss latency 800system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75696.236559 # average ReadReq miss latency 801system.cpu.l2cache.ReadReq_avg_miss_latency::total 71663.373860 # average ReadReq miss latency 802system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66236.552483 # average ReadExReq miss latency 803system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66236.552483 # average ReadExReq miss latency 804system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency 805system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency 806system.cpu.l2cache.demand_avg_miss_latency::total 66581.561997 # average overall miss latency 807system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency 808system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency 809system.cpu.l2cache.overall_avg_miss_latency::total 66581.561997 # average overall miss latency |
| 739system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 740system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 741system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 743system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 744system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 745system.cpu.l2cache.fast_writes 0 # number of fast writes performed 746system.cpu.l2cache.cache_copies 0 # number of cache copies performed 747system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 748system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 749system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 750system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 751system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 752system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 753system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 754system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 755system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits | 810system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 811system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 812system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 813system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 814system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 815system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 816system.cpu.l2cache.fast_writes 0 # number of fast writes performed 817system.cpu.l2cache.cache_copies 0 # number of cache copies performed 818system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 819system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 820system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 821system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 822system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 823system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 824system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 825system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 826system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits |
| 756system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 702 # number of ReadReq MSHR misses 757system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses 758system.cpu.l2cache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses 759system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 760system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses | 827system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses 828system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses 829system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses |
| 761system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 762system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses | 830system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 831system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses |
| 763system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses 764system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses 765system.cpu.l2cache.demand_mshr_misses::total 15506 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses 767system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses 768system.cpu.l2cache.overall_mshr_misses::total 15506 # number of overall MSHR misses 769system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39349250 # number of ReadReq MSHR miss cycles 770system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15357000 # number of ReadReq MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54706250 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 773system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714814750 # number of ReadExReq MSHR miss cycles 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714814750 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39349250 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730171750 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::total 769521000 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39349250 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730171750 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::total 769521000 # number of overall MSHR miss cycles 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001070 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses 786system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses 787system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332404 # mshr miss rate for ReadExReq accesses 788system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332404 # mshr miss rate for ReadExReq accesses 789system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for demand accesses 790system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses 791system.cpu.l2cache.demand_mshr_miss_rate::total 0.016350 # mshr miss rate for demand accesses 792system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for overall accesses 793system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses 794system.cpu.l2cache.overall_mshr_miss_rate::total 0.016350 # mshr miss rate for overall accesses 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56053.062678 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57733.082707 # average ReadReq mshr miss latency 797system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56514.721074 # average ReadReq mshr miss latency 798system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 799system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 800system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49168.713028 # average ReadExReq mshr miss latency 801system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency 804system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency 807system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency | 832system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses 833system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses 834system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses 836system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses 837system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses 838system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40706750 # number of ReadReq MSHR miss cycles 839system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17150500 # number of ReadReq MSHR miss cycles 840system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57857250 # number of ReadReq MSHR miss cycles 841system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780571000 # number of ReadExReq MSHR miss cycles 842system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780571000 # number of ReadExReq MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40706750 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797721500 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.demand_mshr_miss_latency::total 838428250 # number of demand (read+write) MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40706750 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797721500 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::total 838428250 # number of overall MSHR miss cycles 849system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for ReadReq accesses 850system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses 851system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses 852system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332693 # mshr miss rate for ReadExReq accesses 853system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332693 # mshr miss rate for ReadExReq accesses 854system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for demand accesses 855system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses 856system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses 857system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for overall accesses 858system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses 859system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses 860system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57576.732673 # average ReadReq mshr miss latency 861system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63756.505576 # average ReadReq mshr miss latency 862system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59279.969262 # average ReadReq mshr miss latency 863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53691.773284 # average ReadExReq mshr miss latency 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53691.773284 # average ReadExReq mshr miss latency 865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency |
| 808system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 871system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu.dcache.tags.replacements 943531 # number of replacements 810system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. 812system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. 813system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. 814system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. 815system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy 818system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits 819system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits 820system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits 821system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits 822system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits 823system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits | 872system.cpu.dcache.tags.replacements 943519 # number of replacements 873system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use 874system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks. 875system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks. 876system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks. 877system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit. 878system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor 879system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy 880system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy 881system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits 882system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits 883system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits 884system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits 885system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits 886system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits |
| 824system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 825system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits | 887system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 888system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits |
| 826system.cpu.dcache.demand_hits::cpu.data 28130035 # number of demand (read+write) hits 827system.cpu.dcache.demand_hits::total 28130035 # number of demand (read+write) hits 828system.cpu.dcache.overall_hits::cpu.data 28130035 # number of overall hits 829system.cpu.dcache.overall_hits::total 28130035 # number of overall hits 830system.cpu.dcache.ReadReq_misses::cpu.data 1173788 # number of ReadReq misses 831system.cpu.dcache.ReadReq_misses::total 1173788 # number of ReadReq misses 832system.cpu.dcache.WriteReq_misses::cpu.data 202076 # number of WriteReq misses 833system.cpu.dcache.WriteReq_misses::total 202076 # number of WriteReq misses 834system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses 835system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses 836system.cpu.dcache.demand_misses::cpu.data 1375864 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 1375864 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 1375864 # number of overall misses 839system.cpu.dcache.overall_misses::total 1375864 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887695479 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 13887695479 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 7918602355 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 7918602355 # number of WriteReq miss cycles 844system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251250 # number of LoadLockedReq miss cycles 845system.cpu.dcache.LoadLockedReq_miss_latency::total 251250 # number of LoadLockedReq miss cycles 846system.cpu.dcache.demand_miss_latency::cpu.data 21806297834 # number of demand (read+write) miss cycles 847system.cpu.dcache.demand_miss_latency::total 21806297834 # number of demand (read+write) miss cycles 848system.cpu.dcache.overall_miss_latency::cpu.data 21806297834 # number of overall miss cycles 849system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles 850system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses) 851system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses) | 889system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits 890system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits 891system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits 892system.cpu.dcache.overall_hits::total 28134098 # number of overall hits 893system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses 894system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses 895system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses 896system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses 897system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses 898system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses 899system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses 900system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses 901system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses 902system.cpu.dcache.overall_misses::total 1375894 # number of overall misses 903system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles 904system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles 905system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles 906system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles 907system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles 908system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles 909system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles 910system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles 911system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles 912system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles 913system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses) 914system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses) |
| 852system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 853system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) | 915system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 916system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) |
| 854system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3923 # number of LoadLockedReq accesses(hits+misses) 855system.cpu.dcache.LoadLockedReq_accesses::total 3923 # number of LoadLockedReq accesses(hits+misses) | 917system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses) 918system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses) |
| 856system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 857system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) | 919system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 920system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) |
| 858system.cpu.dcache.demand_accesses::cpu.data 29505899 # number of demand (read+write) accesses 859system.cpu.dcache.demand_accesses::total 29505899 # number of demand (read+write) accesses 860system.cpu.dcache.overall_accesses::cpu.data 29505899 # number of overall (read+write) accesses 861system.cpu.dcache.overall_accesses::total 29505899 # number of overall (read+write) accesses 862system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047386 # miss rate for ReadReq accesses 863system.cpu.dcache.ReadReq_miss_rate::total 0.047386 # miss rate for ReadReq accesses 864system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042677 # miss rate for WriteReq accesses 865system.cpu.dcache.WriteReq_miss_rate::total 0.042677 # miss rate for WriteReq accesses 866system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002039 # miss rate for LoadLockedReq accesses 867system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002039 # miss rate for LoadLockedReq accesses 868system.cpu.dcache.demand_miss_rate::cpu.data 0.046630 # miss rate for demand accesses 869system.cpu.dcache.demand_miss_rate::total 0.046630 # miss rate for demand accesses 870system.cpu.dcache.overall_miss_rate::cpu.data 0.046630 # miss rate for overall accesses 871system.cpu.dcache.overall_miss_rate::total 0.046630 # miss rate for overall accesses 872system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency 873system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency 874system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39186.258413 # average WriteReq miss latency 875system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency 876system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31406.250000 # average LoadLockedReq miss latency 877system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency 878system.cpu.dcache.demand_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency 879system.cpu.dcache.demand_avg_miss_latency::total 15849.166657 # average overall miss latency 880system.cpu.dcache.overall_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency 881system.cpu.dcache.overall_avg_miss_latency::total 15849.166657 # average overall miss latency 882system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked | 921system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses 922system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses 923system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses 924system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses 925system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses 926system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses 927system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses 928system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses 929system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses 930system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses 931system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses 932system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses 933system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses 934system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses 935system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency 936system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency 937system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency 938system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency 939system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency 940system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency 941system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency 942system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency 943system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency 944system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency 945system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked |
| 883system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 946system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 884system.cpu.dcache.blocked::no_mshrs 23950 # number of cycles access was blocked | 947system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked |
| 885system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 948system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 886system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.435532 # average number of cycles each access was blocked | 949system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked |
| 887system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 888system.cpu.dcache.fast_writes 0 # number of fast writes performed 889system.cpu.dcache.cache_copies 0 # number of cache copies performed | 950system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 951system.cpu.dcache.fast_writes 0 # number of fast writes performed 952system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 890system.cpu.dcache.writebacks::writebacks 942919 # number of writebacks 891system.cpu.dcache.writebacks::total 942919 # number of writebacks 892system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269877 # number of ReadReq MSHR hits 893system.cpu.dcache.ReadReq_mshr_hits::total 269877 # number of ReadReq MSHR hits 894system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158357 # number of WriteReq MSHR hits 895system.cpu.dcache.WriteReq_mshr_hits::total 158357 # number of WriteReq MSHR hits 896system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits 897system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits 898system.cpu.dcache.demand_mshr_hits::cpu.data 428234 # number of demand (read+write) MSHR hits 899system.cpu.dcache.demand_mshr_hits::total 428234 # number of demand (read+write) MSHR hits 900system.cpu.dcache.overall_mshr_hits::cpu.data 428234 # number of overall MSHR hits 901system.cpu.dcache.overall_mshr_hits::total 428234 # number of overall MSHR hits 902system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903911 # number of ReadReq MSHR misses 903system.cpu.dcache.ReadReq_mshr_misses::total 903911 # number of ReadReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43719 # number of WriteReq MSHR misses 905system.cpu.dcache.WriteReq_mshr_misses::total 43719 # number of WriteReq MSHR misses 906system.cpu.dcache.demand_mshr_misses::cpu.data 947630 # number of demand (read+write) MSHR misses 907system.cpu.dcache.demand_mshr_misses::total 947630 # number of demand (read+write) MSHR misses 908system.cpu.dcache.overall_mshr_misses::cpu.data 947630 # number of overall MSHR misses 909system.cpu.dcache.overall_mshr_misses::total 947630 # number of overall MSHR misses 910system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9992457010 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.ReadReq_mshr_miss_latency::total 9992457010 # number of ReadReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254142688 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254142688 # number of WriteReq MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11246599698 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.demand_mshr_miss_latency::total 11246599698 # number of demand (read+write) MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11246599698 # number of overall MSHR miss cycles 917system.cpu.dcache.overall_mshr_miss_latency::total 11246599698 # number of overall MSHR miss cycles 918system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036491 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036491 # mshr miss rate for ReadReq accesses 920system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009233 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009233 # mshr miss rate for WriteReq accesses 922system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses 923system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses 924system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses 925system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.691236 # average ReadReq mshr miss latency 927system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.691236 # average ReadReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28686.444978 # average WriteReq mshr miss latency 929system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28686.444978 # average WriteReq mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency 931system.cpu.dcache.demand_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency 933system.cpu.dcache.overall_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency | 953system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks 954system.cpu.dcache.writebacks::total 942911 # number of writebacks 955system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits 956system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits 957system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits 958system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits 959system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits 960system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits 961system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits 962system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits 963system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits 964system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits 965system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses 966system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses 967system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses 968system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses 969system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses 970system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses 971system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses 972system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses 973system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles 974system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles 975system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles 976system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles 977system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles 978system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles 979system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles 980system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles 981system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses 982system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses 983system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses 984system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses 985system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses 986system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses 987system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses 988system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses 989system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency 990system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency 991system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency 992system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency 993system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency 994system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency 995system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency 996system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency |
| 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935 936---------- End Simulation Statistics ---------- | 997system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 998 999---------- End Simulation Statistics ---------- |