| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026877 # Number of seconds simulated 4sim_ticks 26877484000 # Number of ticks simulated 5final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026877 # Number of seconds simulated 4sim_ticks 26877484000 # Number of ticks simulated 5final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 175198 # Simulator instruction rate (inst/s) 8host_op_rate 176456 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51980195 # Simulator tick rate (ticks/s) 10host_mem_usage 379404 # Number of bytes of host memory used 11host_seconds 517.07 # Real time elapsed on the host | 7host_inst_rate 190344 # Simulator instruction rate (inst/s) 8host_op_rate 191711 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56473959 # Simulator tick rate (ticks/s) 10host_mem_usage 375760 # Number of bytes of host memory used 11host_seconds 475.93 # Real time elapsed on the host |
| 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992384 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992384 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 15506 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady | 30system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
| 33system.physmem.bytesRead 992384 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() | 34system.physmem.bytesRead 992384 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() |
| 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q |
| 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis --- 163 unchanged lines hidden (view full) --- 209system.physmem.avgGap 1733347.25 # Average gap between requests 210system.membus.throughput 36922504 # Throughput (bytes/s) 211system.membus.trans_dist::ReadReq 968 # Transaction distribution 212system.membus.trans_dist::ReadResp 968 # Transaction distribution 213system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 214system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 215system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 216system.membus.trans_dist::ReadExResp 14538 # Transaction distribution | 39system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis --- 163 unchanged lines hidden (view full) --- 210system.physmem.avgGap 1733347.25 # Average gap between requests 211system.membus.throughput 36922504 # Throughput (bytes/s) 212system.membus.trans_dist::ReadReq 968 # Transaction distribution 213system.membus.trans_dist::ReadResp 968 # Transaction distribution 214system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 215system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 216system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 217system.membus.trans_dist::ReadExResp 14538 # Transaction distribution |
| 217system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes) 218system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes) 219system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes) 220system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes) | 218system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes) 219system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes) 220system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes) 221system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes) |
| 221system.membus.data_through_bus 992384 # Total data (bytes) 222system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 223system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) 224system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 225system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) 226system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 227system.cpu.branchPred.lookups 26677800 # Number of BP lookups 228system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted --- 312 unchanged lines hidden (view full) --- 541system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) 542system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution | 222system.membus.data_through_bus 992384 # Total data (bytes) 223system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 224system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) 225system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 226system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) 227system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 228system.cpu.branchPred.lookups 26677800 # Number of BP lookups 229system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted --- 312 unchanged lines hidden (view full) --- 542system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) 543system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution 549system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution |
| 549system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes) 550system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes) 551system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes) 552system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes) | 550system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes) 551system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes) 552system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes) 555system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes) |
| 555system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) 556system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) 557system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) 558system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) 559system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) 560system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 561system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) 562system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) | 556system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) 557system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) 558system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) 559system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) 560system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) 561system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 562system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) 563system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) |
| 563system.cpu.icache.tags.replacements 3 # number of replacements 564system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use 565system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. 566system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. 567system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. 568system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 569system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor 570system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy 571system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy | 564system.cpu.icache.tags.replacements 3 # number of replacements 565system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use 566system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. 567system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. 568system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. 569system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 570system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor 571system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy 572system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy |
| 572system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits 573system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits 574system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits 575system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits 576system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits 577system.cpu.icache.overall_hits::total 13838909 # number of overall hits 578system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses 579system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 639system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 640system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency 641system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency 642system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency 643system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency 644system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency 645system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency 646system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 573system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits 574system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits 575system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits 576system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits 577system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits 578system.cpu.icache.overall_hits::total 13838909 # number of overall hits 579system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses 580system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 640system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 641system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency 642system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency 643system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency 644system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency 645system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency 646system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency 647system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 647system.cpu.l2cache.tags.replacements 0 # number of replacements 648system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use 649system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. 650system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. 651system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. 652system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 648system.cpu.l2cache.tags.replacements 0 # number of replacements 649system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use 650system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. 651system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. 652system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. 653system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 653system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor | 654system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor |
| 654system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor 655system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor | 655system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor 656system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor |
| 656system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy 657system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy 658system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy | 657system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy 658system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy 659system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy |
| 659system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy | 660system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy |
| 660system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 661system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits 662system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits 663system.cpu.l2cache.Writeback_hits::writebacks 942919 # number of Writeback hits 664system.cpu.l2cache.Writeback_hits::total 942919 # number of Writeback hits 665system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 666system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 667system.cpu.l2cache.ReadExReq_hits::cpu.data 29198 # number of ReadExReq hits --- 132 unchanged lines hidden (view full) --- 800system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency 807system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 661system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 662system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits 663system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits 664system.cpu.l2cache.Writeback_hits::writebacks 942919 # number of Writeback hits 665system.cpu.l2cache.Writeback_hits::total 942919 # number of Writeback hits 666system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 667system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 668system.cpu.l2cache.ReadExReq_hits::cpu.data 29198 # number of ReadExReq hits --- 132 unchanged lines hidden (view full) --- 801system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency 804system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency 807system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency 808system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 808system.cpu.dcache.tags.replacements 943531 # number of replacements 809system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use 810system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. 811system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. 812system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. 813system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. 814system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor 815system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy 816system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy | 809system.cpu.dcache.tags.replacements 943531 # number of replacements 810system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. 812system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. 813system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. 814system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. 815system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy |
| 817system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits 818system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits 819system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits 820system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits 821system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits 822system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits 823system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 824system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits --- 111 unchanged lines hidden --- | 818system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits 819system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits 820system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits 821system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits 822system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits 823system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits 824system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 825system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits --- 111 unchanged lines hidden --- |