Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.026786 # Number of seconds simulated
4sim_ticks 26786364500 # Number of ticks simulated
5final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.026773 # Number of seconds simulated
4sim_ticks 26773408500 # Number of ticks simulated
5final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 55091 # Simulator instruction rate (inst/s)
8host_op_rate 55487 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 16288150 # Simulator tick rate (ticks/s)
10host_mem_usage 365372 # Number of bytes of host memory used
11host_seconds 1644.53 # Real time elapsed on the host
12sim_insts 90599358 # Number of instructions simulated
13sim_ops 91249911 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory
16system.physmem.bytes_read::total 992768 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15512 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1689218 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 35373221 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 37062439 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1689218 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1689218 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1689218 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 35373221 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 37062439 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 15512 # Total number of read requests seen

7host_inst_rate 153523 # Simulator instruction rate (inst/s)
8host_op_rate 154625 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 45373007 # Simulator tick rate (ticks/s)
10host_mem_usage 376436 # Number of bytes of host memory used
11host_seconds 590.07 # Real time elapsed on the host
12sim_insts 90589798 # Number of instructions simulated
13sim_ops 91240351 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory
16system.physmem.bytes_read::total 992576 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15509 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1680473 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 35392729 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 37073203 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1680473 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1680473 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1680473 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 35392729 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 37073203 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 15509 # Total number of read requests seen

31system.physmem.writeReqs 0 # Total number of write requests seen

32system.physmem.cpureqs 15514 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 992768 # Total number of bytes read from memory

32system.physmem.cpureqs 15512 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 992576 # Total number of bytes read from memory

34system.physmem.bytesWritten 0 # Total number of bytes written to memory

35system.physmem.bytesConsumedRd 992768 # bytesRead derated as per pkt->getSize()

35system.physmem.bytesConsumedRd 992576 # bytesRead derated as per pkt->getSize()

36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q

38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 1014 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 997 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis

38system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 999 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 964 # Track reads on a per bank basis

42system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 941 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 1012 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 976 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 936 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 991 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 1011 # Track reads on a per bank basis

49system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis

50system.physmem.perBankRdReqs::11 928 # Track reads on a per bank basis

50system.physmem.perBankRdReqs::11 930 # Track reads on a per bank basis

51system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::15 978 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::15 976 # Track reads on a per bank basis

55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

73system.physmem.totGap 26786186500 # Total gap between requests

73system.physmem.totGap 26773229500 # Total gap between requests

74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes

80system.physmem.readPktSize::6 15512 # Categorize read packet sizes

80system.physmem.readPktSize::6 15509 # Categorize read packet sizes

81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes
89system.physmem.writePktSize::6 0 # categorize write packet sizes
90system.physmem.writePktSize::7 0 # categorize write packet sizes
91system.physmem.writePktSize::8 0 # categorize write packet sizes
92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes

98system.physmem.neitherpktsize::6 2 # categorize neither packet sizes

98system.physmem.neitherpktsize::6 3 # categorize neither packet sizes

99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

101system.physmem.rdQLenPdf::0 10748 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::0 10802 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 4514 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see

104system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see

--- 47 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

167system.physmem.totQLat 45051479 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests
169system.physmem.totBusLat 62048000 # Total cycles spent in databus access
170system.physmem.totBankLat 172004000 # Total cycles spent in bank access
171system.physmem.avgQLat 2904.30 # Average queueing delay per request
172system.physmem.avgBankLat 11088.45 # Average bank access latency per request

167system.physmem.totQLat 45602981 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 279992981 # Sum of mem lat for all requests
169system.physmem.totBusLat 62036000 # Total cycles spent in databus access
170system.physmem.totBankLat 172354000 # Total cycles spent in bank access
171system.physmem.avgQLat 2940.42 # Average queueing delay per request
172system.physmem.avgBankLat 11113.16 # Average bank access latency per request

173system.physmem.avgBusLat 4000.00 # Average bus latency per request

174system.physmem.avgMemAccLat 17992.75 # Average memory access latency
175system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s

174system.physmem.avgMemAccLat 18053.58 # Average memory access latency
175system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s

176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s

177system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s

177system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s

178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 0.23 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.01 # Average read queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time

183system.physmem.readRowHits 15087 # Number of row buffer hits during reads

183system.physmem.readRowHits 15086 # Number of row buffer hits during reads

184system.physmem.writeRowHits 0 # Number of row buffer hits during writes

185system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads

185system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads

186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

187system.physmem.avgGap 1726804.18 # Average gap between requests

187system.physmem.avgGap 1726302.76 # Average gap between requests

188system.cpu.dtb.inst_hits 0 # ITB inst hits
189system.cpu.dtb.inst_misses 0 # ITB inst misses
190system.cpu.dtb.read_hits 0 # DTB read hits
191system.cpu.dtb.read_misses 0 # DTB read misses
192system.cpu.dtb.write_hits 0 # DTB write hits
193system.cpu.dtb.write_misses 0 # DTB write misses
194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
224system.cpu.itb.read_accesses 0 # DTB read accesses
225system.cpu.itb.write_accesses 0 # DTB write accesses
226system.cpu.itb.inst_accesses 0 # ITB inst accesses
227system.cpu.itb.hits 0 # DTB hits
228system.cpu.itb.misses 0 # DTB misses
229system.cpu.itb.accesses 0 # DTB accesses
230system.cpu.workload.num_syscalls 442 # Number of system calls

231system.cpu.numCycles 53572730 # number of cpu cycles simulated

231system.cpu.numCycles 53546818 # number of cpu cycles simulated

232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

234system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups
235system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted
236system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect
237system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups
238system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits

234system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups
235system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted
236system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect
237system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups
238system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits

239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

240system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target.
241system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
242system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss
243system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed
244system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered
245system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken
246system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked
247system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing
248system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked

240system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target.
241system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
242system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss
243system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed
244system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered
245system.cpu.fetch.predictedBranches 11338226 # Number of branches that fetch has predicted taken
246system.cpu.fetch.Cycles 24008993 # Number of cycles fetch has run and was not squashing or blocked
247system.cpu.fetch.SquashCycles 4747196 # Number of cycles fetch has spent squashing
248system.cpu.fetch.BlockedCycles 11262084 # Number of cycles fetch has spent blocked

249system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
250system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
251system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR

252system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched
253system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
254system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total)

252system.cpu.fetch.CacheLines 13843627 # Number of cache lines fetched
253system.cpu.fetch.IcacheSquashes 330314 # Number of outstanding Icache misses that were squashed
254system.cpu.fetch.rateDist::samples 53334178 # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::mean 2.412341 # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::stdev 3.215312 # Number of instructions fetched each cycle (Total)

257system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

258system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total)
259system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total)
261system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total)
265system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total)

258system.cpu.fetch.rateDist::0 29363698 55.06% 55.06% # Number of instructions fetched each cycle (Total)
259system.cpu.fetch.rateDist::1 3375400 6.33% 61.38% # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.rateDist::2 2026423 3.80% 65.18% # Number of instructions fetched each cycle (Total)
261system.cpu.fetch.rateDist::3 1553443 2.91% 68.10% # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::4 1668565 3.13% 71.23% # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::5 2920644 5.48% 76.70% # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.rateDist::6 1511002 2.83% 79.53% # Number of instructions fetched each cycle (Total)
265system.cpu.fetch.rateDist::7 1091875 2.05% 81.58% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::8 9823128 18.42% 100.00% # Number of instructions fetched each cycle (Total)

267system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
268system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
269system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

270system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle
272system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle
273system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle
274system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked
275system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running
276system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking
277system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing
278system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch
279system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction
280system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode
281system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode
282system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing
283system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle
284system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking
285system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst
286system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running
287system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking
288system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename

270system.cpu.fetch.rateDist::total 53334178 # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.branchRate 0.498108 # Number of branch fetches per cycle
272system.cpu.fetch.rate 2.386304 # Number of inst fetches per cycle
273system.cpu.decode.IdleCycles 16944806 # Number of cycles decode is idle
274system.cpu.decode.BlockedCycles 9096910 # Number of cycles decode is blocked
275system.cpu.decode.RunCycles 22405465 # Number of cycles decode is running
276system.cpu.decode.UnblockCycles 1004110 # Number of cycles decode is unblocking
277system.cpu.decode.SquashCycles 3882887 # Number of cycles decode is squashing
278system.cpu.decode.BranchResolved 4441553 # Number of times decode resolved a branch
279system.cpu.decode.BranchMispred 8682 # Number of times decode detected a branch misprediction
280system.cpu.decode.DecodedInsts 125956281 # Number of instructions handled by decode
281system.cpu.decode.SquashedInsts 42689 # Number of squashed instructions handled by decode
282system.cpu.rename.SquashCycles 3882887 # Number of cycles rename is squashing
283system.cpu.rename.IdleCycles 18731656 # Number of cycles rename is idle
284system.cpu.rename.BlockCycles 3549082 # Number of cycles rename is blocking
285system.cpu.rename.serializeStallCycles 155235 # count of cycles rename stalled for serializing inst
286system.cpu.rename.RunCycles 21520684 # Number of cycles rename is running
287system.cpu.rename.UnblockCycles 5494634 # Number of cycles rename is unblocking
288system.cpu.rename.RenamedInsts 123060237 # Number of instructions processed by rename

289system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full

290system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full
291system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full
292system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers
293system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed
294system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made
295system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups
296system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups
297system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
298system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing
299system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed
300system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed
301system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer
302system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit.
303system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit.
304system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads.
305system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores.
306system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec)
307system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ
308system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued
309system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued
310system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling
311system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph
312system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed
313system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle

290system.cpu.rename.IQFullEvents 429079 # Number of times rename has blocked due to IQ full
291system.cpu.rename.LSQFullEvents 4593412 # Number of times rename has blocked due to LSQ full
292system.cpu.rename.FullRegisterEvents 1240 # Number of times there has been no free registers
293system.cpu.rename.RenamedOperands 143474506 # Number of destination operands rename has renamed
294system.cpu.rename.RenameLookups 536032151 # Number of register rename lookups that rename has made
295system.cpu.rename.int_rename_lookups 536027496 # Number of integer rename lookups
296system.cpu.rename.fp_rename_lookups 4655 # Number of floating rename lookups
297system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
298system.cpu.rename.UndoneMaps 36060320 # Number of HB maps that are undone due to squashing
299system.cpu.rename.serializingInsts 4617 # count of serializing insts renamed
300system.cpu.rename.tempSerializingInsts 4615 # count of temporary serializing insts renamed
301system.cpu.rename.skidInsts 12531131 # count of insts added to the skid buffer
302system.cpu.memDep0.insertedLoads 29463379 # Number of loads inserted to the mem dependence unit.
303system.cpu.memDep0.insertedStores 5514746 # Number of stores inserted to the mem dependence unit.
304system.cpu.memDep0.conflictingLoads 2152870 # Number of conflicting loads.
305system.cpu.memDep0.conflictingStores 1249780 # Number of conflicting stores.
306system.cpu.iq.iqInstsAdded 118072720 # Number of instructions added to the IQ (excludes non-spec)
307system.cpu.iq.iqNonSpecInstsAdded 8484 # Number of non-speculative instructions added to the IQ
308system.cpu.iq.iqInstsIssued 105142122 # Number of instructions issued
309system.cpu.iq.iqSquashedInstsIssued 71988 # Number of squashed instructions issued
310system.cpu.iq.iqSquashedInstsExamined 26643181 # Number of squashed instructions iterated over during squash; mainly for profiling
311system.cpu.iq.iqSquashedOperandsExamined 65222929 # Number of squashed operands that are examined and possibly removed from graph
312system.cpu.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed
313system.cpu.iq.issued_per_cycle::samples 53334178 # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::mean 1.971384 # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::stdev 1.909777 # Number of insts issued each cycle

316system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

317system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle
318system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle
319system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle
322system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle
323system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle

317system.cpu.iq.issued_per_cycle::0 15298443 28.68% 28.68% # Number of insts issued each cycle
318system.cpu.iq.issued_per_cycle::1 11631181 21.81% 50.49% # Number of insts issued each cycle
319system.cpu.iq.issued_per_cycle::2 8279084 15.52% 66.02% # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::3 6786399 12.72% 78.74% # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::4 4950529 9.28% 88.02% # Number of insts issued each cycle
322system.cpu.iq.issued_per_cycle::5 2953624 5.54% 93.56% # Number of insts issued each cycle
323system.cpu.iq.issued_per_cycle::6 2464815 4.62% 98.18% # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::7 526374 0.99% 99.17% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::8 443729 0.83% 100.00% # Number of insts issued each cycle

326system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

329system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle

329system.cpu.iq.issued_per_cycle::total 53334178 # Number of insts issued each cycle

330system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

331system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available
332system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available
333system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available
334system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available
335system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available
336system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available
337system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available
338system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available
339system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available
347system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available
348system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available
349system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available
353system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available
354system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available
355system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
360system.cpu.iq.fu_full::MemRead 340422 51.49% 58.35% # attempts to use FU when none available
361system.cpu.iq.fu_full::MemWrite 275350 41.65% 100.00% # attempts to use FU when none available

331system.cpu.iq.fu_full::IntAlu 44991 6.81% 6.81% # attempts to use FU when none available
332system.cpu.iq.fu_full::IntMult 27 0.00% 6.82% # attempts to use FU when none available
333system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available
334system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available
335system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available
336system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available
337system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available
338system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available
339system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available
347system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available
348system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available
349system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available
353system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available
354system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available
355system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
360system.cpu.iq.fu_full::MemRead 339313 51.37% 58.19% # attempts to use FU when none available
361system.cpu.iq.fu_full::MemWrite 276174 41.81% 100.00% # attempts to use FU when none available

362system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
363system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
364system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

365system.cpu.iq.FU_type_0::IntAlu 74420683 70.77% 70.77% # Type of FU issued
366system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued

365system.cpu.iq.FU_type_0::IntAlu 74410825 70.77% 70.77% # Type of FU issued
366system.cpu.iq.FU_type_0::IntMult 10970 0.01% 70.78% # Type of FU issued

367system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
368system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
369system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
370system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
371system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
372system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
373system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued

--- 5 unchanged lines hidden (view full) ---

380system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued

388system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued

388system.cpu.iq.FU_type_0::SimdFloatCvt 146 0.00% 70.78% # Type of FU issued

389system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued

390system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued

390system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.78% # Type of FU issued

391system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued

392system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued

392system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued

393system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued

394system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued
395system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued

394system.cpu.iq.FU_type_0::MemRead 25604346 24.35% 95.13% # Type of FU issued
395system.cpu.iq.FU_type_0::MemWrite 5115650 4.87% 100.00% # Type of FU issued

396system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
397system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

398system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued
399system.cpu.iq.rate 1.962950 # Inst issue rate
400system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested
401system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst)
402system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads
403system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes
404system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses
405system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads
406system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes
407system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses
408system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses
409system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses
410system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores

398system.cpu.iq.FU_type_0::total 105142122 # Type of FU issued
399system.cpu.iq.rate 1.963555 # Inst issue rate
400system.cpu.iq.fu_busy_cnt 660505 # FU busy when requested
401system.cpu.iq.fu_busy_rate 0.006282 # FU busy rate (busy events/executed inst)
402system.cpu.iq.int_inst_queue_reads 264350195 # Number of integer instruction queue reads
403system.cpu.iq.int_inst_queue_writes 144728935 # Number of integer instruction queue writes
404system.cpu.iq.int_inst_queue_wakeup_accesses 102671361 # Number of integer instruction queue wakeup accesses
405system.cpu.iq.fp_inst_queue_reads 720 # Number of floating instruction queue reads
406system.cpu.iq.fp_inst_queue_writes 1005 # Number of floating instruction queue writes
407system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses
408system.cpu.iq.int_alu_accesses 105802266 # Number of integer alu accesses
409system.cpu.iq.fp_alu_accesses 361 # Number of floating point alu accesses
410system.cpu.iew.lsq.thread0.forwLoads 442877 # Number of loads that had data forwarded from stores

411system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

412system.cpu.iew.lsq.thread0.squashedLoads 6895024 # Number of loads squashed
413system.cpu.iew.lsq.thread0.ignoredResponses 7123 # Number of memory responses ignored because the instruction is squashed
414system.cpu.iew.lsq.thread0.memOrderViolation 6272 # Number of memory ordering violations
415system.cpu.iew.lsq.thread0.squashedStores 778037 # Number of stores squashed

412system.cpu.iew.lsq.thread0.squashedLoads 6889413 # Number of loads squashed
413system.cpu.iew.lsq.thread0.ignoredResponses 6770 # Number of memory responses ignored because the instruction is squashed
414system.cpu.iew.lsq.thread0.memOrderViolation 6285 # Number of memory ordering violations
415system.cpu.iew.lsq.thread0.squashedStores 769902 # Number of stores squashed

416system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
417system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
418system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled

419system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked

419system.cpu.iew.lsq.thread0.cacheBlocked 27948 # Number of times an access to memory failed due to the cache being blocked

420system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

421system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing
422system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking
423system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking
424system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ
425system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch
426system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions
427system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions
428system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions
429system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall
430system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall
431system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations
432system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly
433system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly
434system.cpu.iew.branchMispredicts 891809 # Number of branch mispredicts detected at execute
435system.cpu.iew.iewExecutedInsts 104181304 # Number of executed instructions
436system.cpu.iew.iewExecLoadInsts 25288567 # Number of load instructions executed
437system.cpu.iew.iewExecSquashedInsts 979289 # Number of squashed instructions skipped in execute

421system.cpu.iew.iewSquashCycles 3882887 # Number of cycles IEW is squashing
422system.cpu.iew.iewBlockCycles 927098 # Number of cycles IEW is blocking
423system.cpu.iew.iewUnblockCycles 127053 # Number of cycles IEW is unblocking
424system.cpu.iew.iewDispatchedInsts 118093920 # Number of instructions dispatched to IQ
425system.cpu.iew.iewDispSquashedInsts 309711 # Number of squashed instructions skipped by dispatch
426system.cpu.iew.iewDispLoadInsts 29463379 # Number of dispatched load instructions
427system.cpu.iew.iewDispStoreInsts 5514746 # Number of dispatched store instructions
428system.cpu.iew.iewDispNonSpecInsts 4596 # Number of dispatched non-speculative instructions
429system.cpu.iew.iewIQFullEvents 66094 # Number of times the IQ has become full, causing a stall
430system.cpu.iew.iewLSQFullEvents 6965 # Number of times the LSQ has become full, causing a stall
431system.cpu.iew.memOrderViolationEvents 6285 # Number of memory order violations
432system.cpu.iew.predictedTakenIncorrect 446526 # Number of branches that were predicted taken incorrectly
433system.cpu.iew.predictedNotTakenIncorrect 446132 # Number of branches that were predicted not taken incorrectly
434system.cpu.iew.branchMispredicts 892658 # Number of branch mispredicts detected at execute
435system.cpu.iew.iewExecutedInsts 104164248 # Number of executed instructions
436system.cpu.iew.iewExecLoadInsts 25284832 # Number of load instructions executed
437system.cpu.iew.iewExecSquashedInsts 977874 # Number of squashed instructions skipped in execute

438system.cpu.iew.exec_swp 0 # number of swp insts executed

439system.cpu.iew.exec_nop 12695 # number of nop insts executed
440system.cpu.iew.exec_refs 30349931 # number of memory reference insts executed
441system.cpu.iew.exec_branches 21325057 # Number of branches executed
442system.cpu.iew.exec_stores 5061364 # Number of stores executed
443system.cpu.iew.exec_rate 1.944670 # Inst execution rate
444system.cpu.iew.wb_sent 102965645 # cumulative count of insts sent to commit
445system.cpu.iew.wb_count 102686542 # cumulative count of insts written-back
446system.cpu.iew.wb_producers 62242061 # num instructions producing a value
447system.cpu.iew.wb_consumers 104289210 # num instructions consuming a value

439system.cpu.iew.exec_nop 12716 # number of nop insts executed
440system.cpu.iew.exec_refs 30343472 # number of memory reference insts executed
441system.cpu.iew.exec_branches 21324084 # Number of branches executed
442system.cpu.iew.exec_stores 5058640 # Number of stores executed
443system.cpu.iew.exec_rate 1.945293 # Inst execution rate
444system.cpu.iew.wb_sent 102950061 # cumulative count of insts sent to commit
445system.cpu.iew.wb_count 102671670 # cumulative count of insts written-back
446system.cpu.iew.wb_producers 62244850 # num instructions producing a value
447system.cpu.iew.wb_consumers 104302213 # num instructions consuming a value

448system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

449system.cpu.iew.wb_rate 1.916769 # insts written-back per cycle
450system.cpu.iew.wb_fanout 0.596822 # average fanout of values written-back

449system.cpu.iew.wb_rate 1.917419 # insts written-back per cycle
450system.cpu.iew.wb_fanout 0.596774 # average fanout of values written-back

451system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

452system.cpu.commit.commitSquashedInsts 26913567 # The number of squashed insts skipped by commit
453system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
454system.cpu.commit.branchMispredicts 833602 # The number of times a branch was mispredicted
455system.cpu.commit.committed_per_cycle::samples 49467817 # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::mean 1.844887 # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::stdev 2.541636 # Number of insts commited each cycle

452system.cpu.commit.commitSquashedInsts 26843909 # The number of squashed insts skipped by commit
453system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
454system.cpu.commit.branchMispredicts 834006 # The number of times a branch was mispredicted
455system.cpu.commit.committed_per_cycle::samples 49451291 # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::mean 1.845310 # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::stdev 2.541193 # Number of insts commited each cycle

458system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

459system.cpu.commit.committed_per_cycle::0 19986876 40.40% 40.40% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::1 13133000 26.55% 66.95% # Number of insts commited each cycle
461system.cpu.commit.committed_per_cycle::2 4163273 8.42% 75.37% # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::3 3434953 6.94% 82.31% # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::4 1533681 3.10% 85.41% # Number of insts commited each cycle
464system.cpu.commit.committed_per_cycle::5 739386 1.49% 86.91% # Number of insts commited each cycle
465system.cpu.commit.committed_per_cycle::6 948988 1.92% 88.83% # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::7 248747 0.50% 89.33% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::8 5278913 10.67% 100.00% # Number of insts commited each cycle

459system.cpu.commit.committed_per_cycle::0 19963736 40.37% 40.37% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::1 13137085 26.57% 66.94% # Number of insts commited each cycle
461system.cpu.commit.committed_per_cycle::2 4166734 8.43% 75.36% # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::3 3433201 6.94% 82.30% # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::4 1540600 3.12% 85.42% # Number of insts commited each cycle
464system.cpu.commit.committed_per_cycle::5 738938 1.49% 86.91% # Number of insts commited each cycle
465system.cpu.commit.committed_per_cycle::6 946959 1.91% 88.83% # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::7 248344 0.50% 89.33% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::8 5275694 10.67% 100.00% # Number of insts commited each cycle

468system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

471system.cpu.commit.committed_per_cycle::total 49467817 # Number of insts commited each cycle
472system.cpu.commit.committedInsts 90611967 # Number of instructions committed
473system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed

471system.cpu.commit.committed_per_cycle::total 49451291 # Number of insts commited each cycle
472system.cpu.commit.committedInsts 90602407 # Number of instructions committed
473system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed

474system.cpu.commit.swp_count 0 # Number of s/w prefetches committed

475system.cpu.commit.refs 27322634 # Number of memory references committed
476system.cpu.commit.loads 22575878 # Number of loads committed

475system.cpu.commit.refs 27318810 # Number of memory references committed
476system.cpu.commit.loads 22573966 # Number of loads committed

477system.cpu.commit.membars 3888 # Number of memory barriers committed

478system.cpu.commit.branches 18734216 # Number of branches committed

478system.cpu.commit.branches 18732304 # Number of branches committed

479system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.

480system.cpu.commit.int_insts 72533322 # Number of committed integer instructions.

480system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.

481system.cpu.commit.function_calls 56148 # Number of function calls committed.

482system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached

482system.cpu.commit.bw_lim_events 5275694 # number cycles where commit BW limit reached

483system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

484system.cpu.rob.rob_reads 162359257 # The number of ROB reads
485system.cpu.rob.rob_writes 240263976 # The number of ROB writes
486system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself
487system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling
488system.cpu.committedInsts 90599358 # Number of Instructions Simulated
489system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated
490system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated
491system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction
492system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads
493system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle
494system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads
495system.cpu.int_regfile_reads 495578845 # number of integer regfile reads
496system.cpu.int_regfile_writes 120555497 # number of integer regfile writes
497system.cpu.fp_regfile_reads 176 # number of floating regfile reads
498system.cpu.fp_regfile_writes 427 # number of floating regfile writes
499system.cpu.misc_regfile_reads 29099412 # number of misc regfile reads
500system.cpu.misc_regfile_writes 11608 # number of misc regfile writes
501system.cpu.icache.replacements 4 # number of replacements
502system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use
503system.cpu.icache.total_refs 13840965 # Total number of references to valid blocks.
504system.cpu.icache.sampled_refs 735 # Sample count of references to valid blocks.
505system.cpu.icache.avg_refs 18831.244898 # Average number of references to valid blocks.

484system.cpu.rob.rob_reads 162266732 # The number of ROB reads
485system.cpu.rob.rob_writes 240096387 # The number of ROB writes
486system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself
487system.cpu.idleCycles 212640 # Total number of cycles that the CPU has spent unscheduled due to idling
488system.cpu.committedInsts 90589798 # Number of Instructions Simulated
489system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
490system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
491system.cpu.cpi 0.591091 # CPI: Cycles Per Instruction
492system.cpu.cpi_total 0.591091 # CPI: Total CPI of All Threads
493system.cpu.ipc 1.691787 # IPC: Instructions Per Cycle
494system.cpu.ipc_total 1.691787 # IPC: Total IPC of All Threads
495system.cpu.int_regfile_reads 495496065 # number of integer regfile reads
496system.cpu.int_regfile_writes 120529637 # number of integer regfile writes
497system.cpu.fp_regfile_reads 153 # number of floating regfile reads
498system.cpu.fp_regfile_writes 387 # number of floating regfile writes
499system.cpu.misc_regfile_reads 29090556 # number of misc regfile reads
500system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
501system.cpu.icache.replacements 5 # number of replacements
502system.cpu.icache.tagsinuse 628.046446 # Cycle average of tags in use
503system.cpu.icache.total_refs 13842647 # Total number of references to valid blocks.
504system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks.
505system.cpu.icache.avg_refs 18962.530137 # Average number of references to valid blocks.

506system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

507system.cpu.icache.occ_blocks::cpu.inst 632.599736 # Average occupied blocks per requestor
508system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy
509system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy
510system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits
511system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits
512system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits
513system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits
514system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits
515system.cpu.icache.overall_hits::total 13840965 # number of overall hits
516system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
517system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
518system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
519system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
520system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
521system.cpu.icache.overall_misses::total 984 # number of overall misses
522system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles
523system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles
524system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles
525system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles
526system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles
527system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles
528system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses)
529system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses)
530system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses
531system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses
532system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses
533system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses

507system.cpu.icache.occ_blocks::cpu.inst 628.046446 # Average occupied blocks per requestor
508system.cpu.icache.occ_percent::cpu.inst 0.306663 # Average percentage of cache occupancy
509system.cpu.icache.occ_percent::total 0.306663 # Average percentage of cache occupancy
510system.cpu.icache.ReadReq_hits::cpu.inst 13842647 # number of ReadReq hits
511system.cpu.icache.ReadReq_hits::total 13842647 # number of ReadReq hits
512system.cpu.icache.demand_hits::cpu.inst 13842647 # number of demand (read+write) hits
513system.cpu.icache.demand_hits::total 13842647 # number of demand (read+write) hits
514system.cpu.icache.overall_hits::cpu.inst 13842647 # number of overall hits
515system.cpu.icache.overall_hits::total 13842647 # number of overall hits
516system.cpu.icache.ReadReq_misses::cpu.inst 979 # number of ReadReq misses
517system.cpu.icache.ReadReq_misses::total 979 # number of ReadReq misses
518system.cpu.icache.demand_misses::cpu.inst 979 # number of demand (read+write) misses
519system.cpu.icache.demand_misses::total 979 # number of demand (read+write) misses
520system.cpu.icache.overall_misses::cpu.inst 979 # number of overall misses
521system.cpu.icache.overall_misses::total 979 # number of overall misses
522system.cpu.icache.ReadReq_miss_latency::cpu.inst 47680999 # number of ReadReq miss cycles
523system.cpu.icache.ReadReq_miss_latency::total 47680999 # number of ReadReq miss cycles
524system.cpu.icache.demand_miss_latency::cpu.inst 47680999 # number of demand (read+write) miss cycles
525system.cpu.icache.demand_miss_latency::total 47680999 # number of demand (read+write) miss cycles
526system.cpu.icache.overall_miss_latency::cpu.inst 47680999 # number of overall miss cycles
527system.cpu.icache.overall_miss_latency::total 47680999 # number of overall miss cycles
528system.cpu.icache.ReadReq_accesses::cpu.inst 13843626 # number of ReadReq accesses(hits+misses)
529system.cpu.icache.ReadReq_accesses::total 13843626 # number of ReadReq accesses(hits+misses)
530system.cpu.icache.demand_accesses::cpu.inst 13843626 # number of demand (read+write) accesses
531system.cpu.icache.demand_accesses::total 13843626 # number of demand (read+write) accesses
532system.cpu.icache.overall_accesses::cpu.inst 13843626 # number of overall (read+write) accesses
533system.cpu.icache.overall_accesses::total 13843626 # number of overall (read+write) accesses

534system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
535system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
536system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
537system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
538system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
539system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses

540system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency
541system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency
542system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
543system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency
544system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
545system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency
546system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked

540system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48703.778345 # average ReadReq miss latency
541system.cpu.icache.ReadReq_avg_miss_latency::total 48703.778345 # average ReadReq miss latency
542system.cpu.icache.demand_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency
543system.cpu.icache.demand_avg_miss_latency::total 48703.778345 # average overall miss latency
544system.cpu.icache.overall_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency
545system.cpu.icache.overall_avg_miss_latency::total 48703.778345 # average overall miss latency
546system.cpu.icache.blocked_cycles::no_mshrs 1057 # number of cycles access was blocked

547system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

548system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked

548system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked

549system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

550system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked

550system.cpu.icache.avg_blocked_cycles::no_mshrs 132.125000 # average number of cycles each access was blocked

551system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
552system.cpu.icache.fast_writes 0 # number of fast writes performed
553system.cpu.icache.cache_copies 0 # number of cache copies performed

554system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
555system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
556system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
557system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
558system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
559system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
560system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses
561system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
562system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses
563system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses
564system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses
565system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses
566system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles
567system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles
568system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36763999 # number of demand (read+write) MSHR miss cycles
569system.cpu.icache.demand_mshr_miss_latency::total 36763999 # number of demand (read+write) MSHR miss cycles
570system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36763999 # number of overall MSHR miss cycles
571system.cpu.icache.overall_mshr_miss_latency::total 36763999 # number of overall MSHR miss cycles

554system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits
555system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits
556system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits
557system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits
558system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits
559system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits
560system.cpu.icache.ReadReq_mshr_misses::cpu.inst 736 # number of ReadReq MSHR misses
561system.cpu.icache.ReadReq_mshr_misses::total 736 # number of ReadReq MSHR misses
562system.cpu.icache.demand_mshr_misses::cpu.inst 736 # number of demand (read+write) MSHR misses
563system.cpu.icache.demand_mshr_misses::total 736 # number of demand (read+write) MSHR misses
564system.cpu.icache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses
565system.cpu.icache.overall_mshr_misses::total 736 # number of overall MSHR misses
566system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36881499 # number of ReadReq MSHR miss cycles
567system.cpu.icache.ReadReq_mshr_miss_latency::total 36881499 # number of ReadReq MSHR miss cycles
568system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36881499 # number of demand (read+write) MSHR miss cycles
569system.cpu.icache.demand_mshr_miss_latency::total 36881499 # number of demand (read+write) MSHR miss cycles
570system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36881499 # number of overall MSHR miss cycles
571system.cpu.icache.overall_mshr_miss_latency::total 36881499 # number of overall MSHR miss cycles

572system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
573system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
574system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
575system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
576system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
577system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses

578system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency
579system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency
580system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
581system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
582system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
583system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency

578system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50110.732337 # average ReadReq mshr miss latency
579system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50110.732337 # average ReadReq mshr miss latency
580system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50110.732337 # average overall mshr miss latency
581system.cpu.icache.demand_avg_mshr_miss_latency::total 50110.732337 # average overall mshr miss latency
582system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50110.732337 # average overall mshr miss latency
583system.cpu.icache.overall_avg_mshr_miss_latency::total 50110.732337 # average overall mshr miss latency

584system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
585system.cpu.l2cache.replacements 0 # number of replacements

586system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use
587system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks.
588system.cpu.l2cache.sampled_refs 15495 # Sample count of references to valid blocks.
589system.cpu.l2cache.avg_refs 118.204389 # Average number of references to valid blocks.

586system.cpu.l2cache.tagsinuse 10753.787998 # Cycle average of tags in use
587system.cpu.l2cache.total_refs 1831539 # Total number of references to valid blocks.
588system.cpu.l2cache.sampled_refs 15492 # Sample count of references to valid blocks.
589system.cpu.l2cache.avg_refs 118.224826 # Average number of references to valid blocks.

590system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

591system.cpu.l2cache.occ_blocks::writebacks 9910.182329 # Average occupied blocks per requestor
592system.cpu.l2cache.occ_blocks::cpu.inst 617.983134 # Average occupied blocks per requestor
593system.cpu.l2cache.occ_blocks::cpu.data 229.622878 # Average occupied blocks per requestor
594system.cpu.l2cache.occ_percent::writebacks 0.302435 # Average percentage of cache occupancy
595system.cpu.l2cache.occ_percent::cpu.inst 0.018859 # Average percentage of cache occupancy
596system.cpu.l2cache.occ_percent::cpu.data 0.007008 # Average percentage of cache occupancy
597system.cpu.l2cache.occ_percent::total 0.328302 # Average percentage of cache occupancy
598system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
599system.cpu.l2cache.ReadReq_hits::cpu.data 903798 # number of ReadReq hits
600system.cpu.l2cache.ReadReq_hits::total 903825 # number of ReadReq hits
601system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits
602system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits
603system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
604system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
605system.cpu.l2cache.ReadExReq_hits::cpu.data 28978 # number of ReadExReq hits
606system.cpu.l2cache.ReadExReq_hits::total 28978 # number of ReadExReq hits
607system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
608system.cpu.l2cache.demand_hits::cpu.data 932776 # number of demand (read+write) hits
609system.cpu.l2cache.demand_hits::total 932803 # number of demand (read+write) hits
610system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
611system.cpu.l2cache.overall_hits::cpu.data 932776 # number of overall hits
612system.cpu.l2cache.overall_hits::total 932803 # number of overall hits
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734system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38712.355670 # average ReadReq mshr miss latency

735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
736system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency

737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency
738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency
739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
740system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
741system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency

737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28984.037348 # average ReadExReq mshr miss latency
738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28984.037348 # average ReadExReq mshr miss latency
739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency
740system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency
741system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency
742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency
743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency
744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency

745system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

746system.cpu.dcache.replacements 943495 # number of replacements
747system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
748system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
749system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
750system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
751system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
752system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
753system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
754system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
755system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
756system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
757system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
758system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
759system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
760system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
761system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
762system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
763system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
764system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
765system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
766system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
767system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
768system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
769system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
770system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
771system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
772system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
773system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
774system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
775system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
776system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
777system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles
778system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles
779system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
780system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
781system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
782system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
783system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles
784system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles
785system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles
786system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles
787system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
788system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)

746system.cpu.dcache.replacements 943481 # number of replacements
747system.cpu.dcache.tagsinuse 3674.468837 # Cycle average of tags in use
748system.cpu.dcache.total_refs 28144290 # Total number of references to valid blocks.
749system.cpu.dcache.sampled_refs 947577 # Sample count of references to valid blocks.
750system.cpu.dcache.avg_refs 29.701322 # Average number of references to valid blocks.
751system.cpu.dcache.warmup_cycle 7935444000 # Cycle when the warmup percentage was hit.
752system.cpu.dcache.occ_blocks::cpu.data 3674.468837 # Average occupied blocks per requestor
753system.cpu.dcache.occ_percent::cpu.data 0.897087 # Average percentage of cache occupancy
754system.cpu.dcache.occ_percent::total 0.897087 # Average percentage of cache occupancy
755system.cpu.dcache.ReadReq_hits::cpu.data 23599200 # number of ReadReq hits
756system.cpu.dcache.ReadReq_hits::total 23599200 # number of ReadReq hits
757system.cpu.dcache.WriteReq_hits::cpu.data 4537276 # number of WriteReq hits
758system.cpu.dcache.WriteReq_hits::total 4537276 # number of WriteReq hits
759system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits
760system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits
761system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
762system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
763system.cpu.dcache.demand_hits::cpu.data 28136476 # number of demand (read+write) hits
764system.cpu.dcache.demand_hits::total 28136476 # number of demand (read+write) hits
765system.cpu.dcache.overall_hits::cpu.data 28136476 # number of overall hits
766system.cpu.dcache.overall_hits::total 28136476 # number of overall hits
767system.cpu.dcache.ReadReq_misses::cpu.data 1173036 # number of ReadReq misses
768system.cpu.dcache.ReadReq_misses::total 1173036 # number of ReadReq misses
769system.cpu.dcache.WriteReq_misses::cpu.data 197705 # number of WriteReq misses
770system.cpu.dcache.WriteReq_misses::total 197705 # number of WriteReq misses
771system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
772system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
773system.cpu.dcache.demand_misses::cpu.data 1370741 # number of demand (read+write) misses
774system.cpu.dcache.demand_misses::total 1370741 # number of demand (read+write) misses
775system.cpu.dcache.overall_misses::cpu.data 1370741 # number of overall misses
776system.cpu.dcache.overall_misses::total 1370741 # number of overall misses
777system.cpu.dcache.ReadReq_miss_latency::cpu.data 13886322000 # number of ReadReq miss cycles
778system.cpu.dcache.ReadReq_miss_latency::total 13886322000 # number of ReadReq miss cycles
779system.cpu.dcache.WriteReq_miss_latency::cpu.data 5375913921 # number of WriteReq miss cycles
780system.cpu.dcache.WriteReq_miss_latency::total 5375913921 # number of WriteReq miss cycles
781system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles
782system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles
783system.cpu.dcache.demand_miss_latency::cpu.data 19262235921 # number of demand (read+write) miss cycles
784system.cpu.dcache.demand_miss_latency::total 19262235921 # number of demand (read+write) miss cycles
785system.cpu.dcache.overall_miss_latency::cpu.data 19262235921 # number of overall miss cycles
786system.cpu.dcache.overall_miss_latency::total 19262235921 # number of overall miss cycles
787system.cpu.dcache.ReadReq_accesses::cpu.data 24772236 # number of ReadReq accesses(hits+misses)
788system.cpu.dcache.ReadReq_accesses::total 24772236 # number of ReadReq accesses(hits+misses)

789system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
790system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)

791system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
792system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
793system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
794system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
795system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
796system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
797system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
798system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
799system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
800system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
801system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
802system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
803system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
804system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
805system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
806system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
807system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
808system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
809system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency
810system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency
811system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
812system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
813system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
814system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
815system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
816system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency
817system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
818system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency
819system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked

791system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses)
792system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses)
793system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
794system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
795system.cpu.dcache.demand_accesses::cpu.data 29507217 # number of demand (read+write) accesses
796system.cpu.dcache.demand_accesses::total 29507217 # number of demand (read+write) accesses
797system.cpu.dcache.overall_accesses::cpu.data 29507217 # number of overall (read+write) accesses
798system.cpu.dcache.overall_accesses::total 29507217 # number of overall (read+write) accesses
799system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047353 # miss rate for ReadReq accesses
800system.cpu.dcache.ReadReq_miss_rate::total 0.047353 # miss rate for ReadReq accesses
801system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041754 # miss rate for WriteReq accesses
802system.cpu.dcache.WriteReq_miss_rate::total 0.041754 # miss rate for WriteReq accesses
803system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses
804system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses
805system.cpu.dcache.demand_miss_rate::cpu.data 0.046454 # miss rate for demand accesses
806system.cpu.dcache.demand_miss_rate::total 0.046454 # miss rate for demand accesses
807system.cpu.dcache.overall_miss_rate::cpu.data 0.046454 # miss rate for overall accesses
808system.cpu.dcache.overall_miss_rate::total 0.046454 # miss rate for overall accesses
809system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.933363 # average ReadReq miss latency
810system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.933363 # average ReadReq miss latency
811system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27191.593136 # average WriteReq miss latency
812system.cpu.dcache.WriteReq_avg_miss_latency::total 27191.593136 # average WriteReq miss latency
813system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29214.285714 # average LoadLockedReq miss latency
814system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29214.285714 # average LoadLockedReq miss latency
815system.cpu.dcache.demand_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency
816system.cpu.dcache.demand_avg_miss_latency::total 14052.425601 # average overall miss latency
817system.cpu.dcache.overall_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency
818system.cpu.dcache.overall_avg_miss_latency::total 14052.425601 # average overall miss latency
819system.cpu.dcache.blocked_cycles::no_mshrs 132657 # number of cycles access was blocked

820system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

821system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked

821system.cpu.dcache.blocked::no_mshrs 23814 # number of cycles access was blocked

822system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

823system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked

823system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.570547 # average number of cycles each access was blocked

824system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
825system.cpu.dcache.fast_writes 0 # number of fast writes performed
826system.cpu.dcache.cache_copies 0 # number of cache copies performed

827system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
828system.cpu.dcache.writebacks::total 942892 # number of writebacks
829system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
830system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
831system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
832system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
833system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
834system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
835system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
836system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
837system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
838system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
839system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
840system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
841system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
842system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
843system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
844system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
845system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
846system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
847system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles
848system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles
849system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
850system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
851system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles
852system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles
853system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles
854system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles
855system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
856system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
857system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
858system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
859system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
860system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
861system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
862system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency
864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency
865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
867system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
868system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
869system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
870system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency

827system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks
828system.cpu.dcache.writebacks::total 942884 # number of writebacks
829system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268972 # number of ReadReq MSHR hits
830system.cpu.dcache.ReadReq_mshr_hits::total 268972 # number of ReadReq MSHR hits
831system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154186 # number of WriteReq MSHR hits
832system.cpu.dcache.WriteReq_mshr_hits::total 154186 # number of WriteReq MSHR hits
833system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
834system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
835system.cpu.dcache.demand_mshr_hits::cpu.data 423158 # number of demand (read+write) MSHR hits
836system.cpu.dcache.demand_mshr_hits::total 423158 # number of demand (read+write) MSHR hits
837system.cpu.dcache.overall_mshr_hits::cpu.data 423158 # number of overall MSHR hits
838system.cpu.dcache.overall_mshr_hits::total 423158 # number of overall MSHR hits
839system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904064 # number of ReadReq MSHR misses
840system.cpu.dcache.ReadReq_mshr_misses::total 904064 # number of ReadReq MSHR misses
841system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43519 # number of WriteReq MSHR misses
842system.cpu.dcache.WriteReq_mshr_misses::total 43519 # number of WriteReq MSHR misses
843system.cpu.dcache.demand_mshr_misses::cpu.data 947583 # number of demand (read+write) MSHR misses
844system.cpu.dcache.demand_mshr_misses::total 947583 # number of demand (read+write) MSHR misses
845system.cpu.dcache.overall_mshr_misses::cpu.data 947583 # number of overall MSHR misses
846system.cpu.dcache.overall_mshr_misses::total 947583 # number of overall MSHR misses
847system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9987518000 # number of ReadReq MSHR miss cycles
848system.cpu.dcache.ReadReq_mshr_miss_latency::total 9987518000 # number of ReadReq MSHR miss cycles
849system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 958248463 # number of WriteReq MSHR miss cycles
850system.cpu.dcache.WriteReq_mshr_miss_latency::total 958248463 # number of WriteReq MSHR miss cycles
851system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945766463 # number of demand (read+write) MSHR miss cycles
852system.cpu.dcache.demand_mshr_miss_latency::total 10945766463 # number of demand (read+write) MSHR miss cycles
853system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945766463 # number of overall MSHR miss cycles
854system.cpu.dcache.overall_mshr_miss_latency::total 10945766463 # number of overall MSHR miss cycles
855system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036495 # mshr miss rate for ReadReq accesses
856system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036495 # mshr miss rate for ReadReq accesses
857system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009191 # mshr miss rate for WriteReq accesses
858system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009191 # mshr miss rate for WriteReq accesses
859system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for demand accesses
860system.cpu.dcache.demand_mshr_miss_rate::total 0.032114 # mshr miss rate for demand accesses
861system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for overall accesses
862system.cpu.dcache.overall_mshr_miss_rate::total 0.032114 # mshr miss rate for overall accesses
863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11047.357267 # average ReadReq mshr miss latency
864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11047.357267 # average ReadReq mshr miss latency
865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22019.082768 # average WriteReq mshr miss latency
866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22019.082768 # average WriteReq mshr miss latency
867system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency
868system.cpu.dcache.demand_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency
869system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency
870system.cpu.dcache.overall_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency