| stats.txt (9378:36ed6d4654bb) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026786 # Number of seconds simulated 4sim_ticks 26786364500 # Number of ticks simulated 5final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026786 # Number of seconds simulated 4sim_ticks 26786364500 # Number of ticks simulated 5final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 184396 # Simulator instruction rate (inst/s) 8host_op_rate 185720 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54518089 # Simulator tick rate (ticks/s) 10host_mem_usage 410024 # Number of bytes of host memory used 11host_seconds 491.33 # Real time elapsed on the host | 7host_inst_rate 55091 # Simulator instruction rate (inst/s) 8host_op_rate 55487 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16288150 # Simulator tick rate (ticks/s) 10host_mem_usage 365372 # Number of bytes of host memory used 11host_seconds 1644.53 # Real time elapsed on the host |
| 12sim_insts 90599358 # Number of instructions simulated 13sim_ops 91249911 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992768 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory --- 45 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 12sim_insts 90599358 # Number of instructions simulated 13sim_ops 91249911 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992768 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory --- 45 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 26786185500 # Total gap between requests | 73system.physmem.totGap 26786186500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 15512 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 15512 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 45050979 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests | 167system.physmem.totQLat 45051479 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests |
| 169system.physmem.totBusLat 62048000 # Total cycles spent in databus access 170system.physmem.totBankLat 172004000 # Total cycles spent in bank access | 169system.physmem.totBusLat 62048000 # Total cycles spent in databus access 170system.physmem.totBankLat 172004000 # Total cycles spent in bank access |
| 171system.physmem.avgQLat 2904.27 # Average queueing delay per request | 171system.physmem.avgQLat 2904.30 # Average queueing delay per request |
| 172system.physmem.avgBankLat 11088.45 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request | 172system.physmem.avgBankLat 11088.45 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 174system.physmem.avgMemAccLat 17992.71 # Average memory access latency | 174system.physmem.avgMemAccLat 17992.75 # Average memory access latency |
| 175system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.23 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.01 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 15087 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 175system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.23 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.01 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 15087 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 1726804.12 # Average gap between requests | 187system.physmem.avgGap 1726804.18 # Average gap between requests |
| 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 38 unchanged lines hidden (view full) --- 234system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. | 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 38 unchanged lines hidden (view full) --- 234system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. |
| 242system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss | 242system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss |
| 243system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing | 243system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing |
| 248system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 248system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 250system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps 251system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR | 250system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps 251system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR |
| 252system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched 253system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed 254system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total) | 252system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched 253system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed 254system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total) |
| 255system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 255system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 258system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total) | 258system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total) |
| 259system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 259system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 270system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total) | 270system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total) |
| 271system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle 272system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle 273system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle | 271system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle 272system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle 273system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle |
| 274system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked | 274system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked |
| 275system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running 276system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking 277system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing 278system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch 279system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction 280system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode 281system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode 282system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing 283system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle 284system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking 285system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst | 275system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running 276system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking 277system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing 278system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch 279system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction 280system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode 281system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode 282system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing 283system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle 284system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking 285system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst |
| 286system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running | 286system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running |
| 287system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking | 287system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking |
| 288system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename | 288system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename |
| 289system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full 290system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full 291system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full 292system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers | 289system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full 290system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full 291system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full 292system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers |
| 293system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed 294system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made 295system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups | 293system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed 294system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made 295system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups |
| 296system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups 297system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed | 296system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups 297system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed |
| 298system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing | 298system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing |
| 299system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed 300system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed 301system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer 302system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit. 303system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit. 304system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads. 305system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores. 306system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec) 307system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ 308system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued 309system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued 310system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling 311system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph 312system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed | 299system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed 300system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed 301system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer 302system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit. 303system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit. 304system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads. 305system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores. 306system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec) 307system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ 308system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued 309system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued 310system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling 311system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph 312system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed |
| 313system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle | 313system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle |
| 314system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 314system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 317system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle | 317system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle |
| 318system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 318system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 329system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle | 329system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle |
| 330system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 331system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available 332system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 394system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued 395system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued 396system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 397system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued 399system.cpu.iq.rate 1.962950 # Inst issue rate 400system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested 401system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) | 330system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 331system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available 332system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 394system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued 395system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued 396system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 397system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued 399system.cpu.iq.rate 1.962950 # Inst issue rate 400system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested 401system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) |
| 402system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads | 402system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads |
| 403system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes 404system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses 405system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads 406system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes 407system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses 408system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses 409system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses 410system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 417system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 418system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 419system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked 420system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 421system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing 422system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking 423system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking 424system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ | 403system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes 404system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses 405system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads 406system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes 407system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses 408system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses 409system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses 410system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 417system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 418system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 419system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked 420system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 421system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing 422system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking 423system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking 424system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ |
| 425system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch | 425system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch |
| 426system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions 427system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions 428system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions 429system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall 430system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall 431system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations 432system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly 433system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly --- 45 unchanged lines hidden (view full) --- 479system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 480system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. 481system.cpu.commit.function_calls 56148 # Number of function calls committed. 482system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached 483system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 484system.cpu.rob.rob_reads 162359257 # The number of ROB reads 485system.cpu.rob.rob_writes 240263976 # The number of ROB writes 486system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself | 426system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions 427system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions 428system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions 429system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall 430system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall 431system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations 432system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly 433system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly --- 45 unchanged lines hidden (view full) --- 479system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 480system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. 481system.cpu.commit.function_calls 56148 # Number of function calls committed. 482system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached 483system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 484system.cpu.rob.rob_reads 162359257 # The number of ROB reads 485system.cpu.rob.rob_writes 240263976 # The number of ROB writes 486system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 487system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling | 487system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 488system.cpu.committedInsts 90599358 # Number of Instructions Simulated 489system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated 490system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated 491system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction 492system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads 493system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle 494system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads 495system.cpu.int_regfile_reads 495578845 # number of integer regfile reads --- 12 unchanged lines hidden (view full) --- 508system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy 509system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy 510system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits 511system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits 512system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits 513system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits 514system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits 515system.cpu.icache.overall_hits::total 13840965 # number of overall hits | 488system.cpu.committedInsts 90599358 # Number of Instructions Simulated 489system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated 490system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated 491system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction 492system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads 493system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle 494system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads 495system.cpu.int_regfile_reads 495578845 # number of integer regfile reads --- 12 unchanged lines hidden (view full) --- 508system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy 509system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy 510system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits 511system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits 512system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits 513system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits 514system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits 515system.cpu.icache.overall_hits::total 13840965 # number of overall hits |
| 516system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses 517system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses 518system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses 519system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses 520system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses 521system.cpu.icache.overall_misses::total 983 # number of overall misses 522system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles 523system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles 524system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles 525system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles 526system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles 527system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles 528system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses) 529system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses 531system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses 532system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses 533system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses | 516system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses 517system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses 518system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses 519system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses 520system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses 521system.cpu.icache.overall_misses::total 984 # number of overall misses 522system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles 523system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles 524system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles 525system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles 526system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles 527system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles 528system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses) 529system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses 531system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses 532system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses 533system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses |
| 534system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses 535system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses 536system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses 537system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses 538system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses 539system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses | 534system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses 535system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses 536system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses 537system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses 538system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses 539system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses |
| 540system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency 541system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency 542system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency 543system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency 544system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency | 540system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency 541system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency 542system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency 543system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency 544system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency |
| 546system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked 547system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked 549system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked 551system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 552system.cpu.icache.fast_writes 0 # number of fast writes performed 553system.cpu.icache.cache_copies 0 # number of cache copies performed | 546system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked 547system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked 549system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked 551system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 552system.cpu.icache.fast_writes 0 # number of fast writes performed 553system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 554system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits 555system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits 556system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits 557system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits 558system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits 559system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits | 554system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits 555system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits 556system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits 557system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits 558system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits 559system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits |
| 560system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses 561system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses 562system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses 563system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses 564system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses 565system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses 566system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles 567system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles --- 9 unchanged lines hidden (view full) --- 577system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 578system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency 580system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency 582system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency 584system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 560system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses 561system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses 562system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses 563system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses 564system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses 565system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses 566system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles 567system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles --- 9 unchanged lines hidden (view full) --- 577system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 578system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency 580system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency 582system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency 584system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 585system.cpu.dcache.replacements 943495 # number of replacements 586system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use 587system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. 588system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. 589system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. 590system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. 591system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor 592system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy 593system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy 594system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits 598system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits 599system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits 600system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits 601system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits 602system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits 603system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits 604system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits 605system.cpu.dcache.overall_hits::total 28133775 # number of overall hits 606system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses 607system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses 608system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses 609system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses 610system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses 611system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses 612system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses 613system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses 614system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses 615system.cpu.dcache.overall_misses::total 1370806 # number of overall misses 616system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles 617system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles 618system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles 619system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles 620system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles 621system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles 622system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles 623system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles 624system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles 625system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles 626system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) 627system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) 628system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 629system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 630system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) 631system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) 632system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) 633system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) 634system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses 635system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses 636system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses 637system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses 638system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses 639system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses 640system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses 641system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses 642system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses 643system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses 644system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses 645system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses 646system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses 647system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses 648system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency 649system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency 650system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency 651system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency 652system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency 653system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency 654system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency 655system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency 656system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency 658system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked 659system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 660system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked 661system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 662system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked 663system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 664system.cpu.dcache.fast_writes 0 # number of fast writes performed 665system.cpu.dcache.cache_copies 0 # number of cache copies performed 666system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks 667system.cpu.dcache.writebacks::total 942892 # number of writebacks 668system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits 669system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits 670system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits 671system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits 672system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits 673system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits 674system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits 675system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits 676system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits 677system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits 678system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses 679system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses 680system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses 681system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses 682system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses 683system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses 684system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses 685system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses 686system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles 687system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles 691system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles 694system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses 695system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses 697system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses 699system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses 700system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses 701system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses 702system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency 704system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency 706system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency 708system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency 710system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 711system.cpu.l2cache.replacements 0 # number of replacements 712system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use 713system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks. 714system.cpu.l2cache.sampled_refs 15495 # Sample count of references to valid blocks. 715system.cpu.l2cache.avg_refs 118.204389 # Average number of references to valid blocks. 716system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 717system.cpu.l2cache.occ_blocks::writebacks 9910.182329 # Average occupied blocks per requestor 718system.cpu.l2cache.occ_blocks::cpu.inst 617.983134 # Average occupied blocks per requestor --- 26 unchanged lines hidden (view full) --- 745system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 746system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses 747system.cpu.l2cache.demand_misses::cpu.data 14815 # number of demand (read+write) misses 748system.cpu.l2cache.demand_misses::total 15523 # number of demand (read+write) misses 749system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses 751system.cpu.l2cache.overall_misses::total 15523 # number of overall misses 752system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles | 585system.cpu.l2cache.replacements 0 # number of replacements 586system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use 587system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks. 588system.cpu.l2cache.sampled_refs 15495 # Sample count of references to valid blocks. 589system.cpu.l2cache.avg_refs 118.204389 # Average number of references to valid blocks. 590system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 591system.cpu.l2cache.occ_blocks::writebacks 9910.182329 # Average occupied blocks per requestor 592system.cpu.l2cache.occ_blocks::cpu.inst 617.983134 # Average occupied blocks per requestor --- 26 unchanged lines hidden (view full) --- 619system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 620system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::cpu.data 14815 # number of demand (read+write) misses 622system.cpu.l2cache.demand_misses::total 15523 # number of demand (read+write) misses 623system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses 624system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses 625system.cpu.l2cache.overall_misses::total 15523 # number of overall misses 626system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles |
| 753system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles 754system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles | 627system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles |
| 755system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles 756system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles 757system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles | 629system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles 630system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles |
| 758system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles | 632system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles 633system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles |
| 760system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles | 634system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles |
| 761system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles | 635system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles 636system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles |
| 763system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) 764system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses) 765system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses) 767system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses) 768system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) 769system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) 770system.cpu.l2cache.ReadExReq_accesses::cpu.data 43516 # number of ReadExReq accesses(hits+misses) --- 13 unchanged lines hidden (view full) --- 784system.cpu.l2cache.ReadExReq_miss_rate::total 0.334084 # miss rate for ReadExReq accesses 785system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963265 # miss rate for demand accesses 786system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses 787system.cpu.l2cache.demand_miss_rate::total 0.016369 # miss rate for demand accesses 788system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses 790system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses 791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency | 637system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses) 640system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses) 641system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses) 642system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) 643system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) 644system.cpu.l2cache.ReadExReq_accesses::cpu.data 43516 # number of ReadExReq accesses(hits+misses) --- 13 unchanged lines hidden (view full) --- 658system.cpu.l2cache.ReadExReq_miss_rate::total 0.334084 # miss rate for ReadExReq accesses 659system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963265 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses 661system.cpu.l2cache.demand_miss_rate::total 0.016369 # miss rate for demand accesses 662system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses 664system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency |
| 792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency 793system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency | 666system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency 667system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency |
| 794system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency 795system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency 796system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency | 668system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency 669system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency 670system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency |
| 797system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency 798system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency | 671system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency 672system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency |
| 799system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency | 673system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency |
| 800system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency | 674system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency 675system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency |
| 802system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 806system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 807system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 808system.cpu.l2cache.fast_writes 0 # number of fast writes performed 809system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 824system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 825system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::total 15512 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses | 676system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.l2cache.fast_writes 0 # number of fast writes performed 683system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 698system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 699system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.demand_mshr_misses::total 15512 # number of demand (read+write) MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses 705system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses |
| 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles | 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles |
| 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles | 707system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles |
| 834system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles | 708system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles |
| 835system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles | 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 710system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles |
| 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles | 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles |
| 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles | 714system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles |
| 841system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles | 715system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles |
| 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles | 717system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles |
| 844system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles | 718system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles |
| 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses 848system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 849system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 850system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334084 # mshr miss rate for ReadExReq accesses 851system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334084 # mshr miss rate for ReadExReq accesses 852system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for demand accesses 853system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for demand accesses 854system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 # mshr miss rate for demand accesses 855system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses 856system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses 857system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses | 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses 721system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 723system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334084 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334084 # mshr miss rate for ReadExReq accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for demand accesses 728system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 # mshr miss rate for demand accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses 731system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses |
| 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency | 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency |
| 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency | 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency |
| 860system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency | 734system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency |
| 861system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 862system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency | 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 736system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency 738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency |
| 865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency | 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency |
| 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency | 740system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency |
| 867system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency | 741system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency |
| 869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency | 743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency |
| 870system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency | 744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency |
| 871system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 745system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 746system.cpu.dcache.replacements 943495 # number of replacements 747system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use 748system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. 749system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. 750system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. 751system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. 752system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor 753system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy 754system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy 755system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits 756system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits 757system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits 758system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits 759system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits 760system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits 761system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits 762system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits 763system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits 764system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits 765system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits 766system.cpu.dcache.overall_hits::total 28133775 # number of overall hits 767system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses 768system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses 769system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses 770system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses 771system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses 772system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses 773system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses 774system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses 775system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses 776system.cpu.dcache.overall_misses::total 1370806 # number of overall misses 777system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles 778system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles 780system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles 782system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles 783system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles 784system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles 785system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles 786system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles 787system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) 794system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) 795system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses 796system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses 797system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses 798system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses 799system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses 800system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses 801system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses 802system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses 805system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses 806system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses 807system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses 808system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses 809system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency 810system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency 812system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency 814system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency 815system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency 816system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency 818system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency 819system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked 820system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked 822system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked 824system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 825system.cpu.dcache.fast_writes 0 # number of fast writes performed 826system.cpu.dcache.cache_copies 0 # number of cache copies performed 827system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks 828system.cpu.dcache.writebacks::total 942892 # number of writebacks 829system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits 830system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits 832system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits 834system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits 835system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits 836system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits 837system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits 838system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits 839system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses 840system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses 842system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses 843system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses 844system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses 845system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses 846system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses 847system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles 854system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles 855system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses 859system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses 860system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses 861system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses 862system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency 868system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency 870system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency 871system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
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| 872 873---------- End Simulation Statistics ---------- | 872 873---------- End Simulation Statistics ---------- |